chore: more detailed panic message
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@@ -17,7 +17,7 @@ pub fn format1(comptime op: u2, comptime offset: u5) InstrFn {
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0b00 => shifter.logicalLeft(true, &cpu.cpsr, cpu.r[rs], offset), // LSL
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0b01 => shifter.logicalRight(true, &cpu.cpsr, cpu.r[rs], offset), // LSR
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0b10 => shifter.arithmeticRight(true, &cpu.cpsr, cpu.r[rs], offset), // ASR
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else => std.debug.panic("[CPU|THUMB|Fmt1] {} is an invalid op", .{op}),
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else => cpu.panic("[CPU|THUMB|Fmt1] {} is an invalid op", .{op}),
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};
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// Equivalent to an ARM MOVS
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@@ -6,8 +6,8 @@ const InstrFn = @import("../../cpu.zig").ThumbInstrFn;
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pub fn format13(comptime _: bool) InstrFn {
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return struct {
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fn inner(_: *Arm7tdmi, _: *Bus, _: u16) void {
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std.debug.panic("[CPU|THUMB|Fmt13] Implement Format 13 THUMB Instructions", .{});
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fn inner(cpu: *Arm7tdmi, _: *Bus, _: u16) void {
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cpu.panic("[CPU|THUMB|Fmt13] Implement Format 13 THUMB Instructions", .{});
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}
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}.inner;
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}
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@@ -14,7 +14,7 @@ pub fn format16(comptime cond: u4) InstrFn {
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const offset = u32SignExtend(8, opcode & 0xFF) << 1;
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const should_execute = switch (cond) {
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0xE, 0xF => std.debug.panic("[CPU/THUMB] Undefined conditional branch with condition {}", .{cond}),
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0xE, 0xF => cpu.panic("[CPU/THUMB] Undefined conditional branch with condition {}", .{cond}),
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else => checkCond(cpu.cpsr, cond),
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};
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@@ -20,7 +20,7 @@ pub fn format5(comptime op: u2, comptime h1: u1, comptime h2: u1) InstrFn {
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cpu.cpsr.t.write(cpu.r[src] & 1 == 1);
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cpu.r[15] = cpu.r[src] & 0xFFFF_FFFE;
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},
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else => std.debug.panic("[CPU|THUMB|Fmt5] {} is an invalid op", .{op}),
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else => cpu.panic("[CPU|THUMB|Fmt5] {} is an invalid op", .{op}),
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}
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}
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}.inner;
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