paoda/zba
1
0
Fork 0
Code Issues Pull Requests Projects Releases Wiki Activity

chore: more detailed panic message

Browse Source
This commit is contained in:
Rekai Nyangadzayi Musuka
2022-02-01 18:38:09 -04:00
parent ca41f6a85c
commit 0d7600ed7a
8 changed files with 71 additions and 21 deletions
Download Patch File Download Diff File Expand all files Collapse all files

6
src/cpu/arm/block_data_transfer.zig
View File

@@ -10,7 +10,7 @@ pub fn blockDataTransfer(comptime P: bool, comptime U: bool, comptime S: bool, c
const rn = opcode >> 16 & 0xF;
const base = cpu.r[rn];
if (S and opcode >> 15 & 1 == 0) std.debug.panic("[CPU] TODO: STM/LDM with S set but R15 not in transfer list", .{});
if (S and opcode >> 15 & 1 == 0) cpu.panic("[CPU] TODO: STM/LDM with S set but R15 not in transfer list", .{});
var address: u32 = undefined;
if (U) {
@@ -45,14 +45,14 @@ pub fn blockDataTransfer(comptime P: bool, comptime U: bool, comptime S: bool, c
fn transfer(cpu: *Arm7tdmi, bus: *Bus, i: u5, address: u32) void {
if (L) {
cpu.r[i] = bus.read32(address);
if (S and i == 0xF) std.debug.panic("[CPU] TODO: SPSR_<mode> is transferred to CPSR", .{});
if (S and i == 0xF) cpu.panic("[CPU] TODO: SPSR_<mode> is transferred to CPSR", .{});
} else {
if (i == 0xF) {
if (!S) {
// TODO: Assure that this is Address of STM instruction + 12
bus.write32(address, cpu.r[i] + (12 - 4));
} else {
std.debug.panic("[CPU] TODO: STM with S set and R15 in transfer list", .{});
cpu.panic("[CPU] TODO: STM with S set and R15 in transfer list", .{});
}
} else {
bus.write32(address, cpu.r[i]);

4
src/cpu/arm/half_signed_data_transfer.zig
View File

@@ -47,12 +47,12 @@ pub fn halfAndSignedDataTransfer(comptime P: bool, comptime U: bool, comptime I:
0b10 => {
// LDRSB
cpu.r[rd] = util.u32SignExtend(8, @as(u32, bus.read8(address)));
std.debug.panic("[CPU|ARM|LDRSB] TODO: Affect the CPSR", .{});
cpu.panic("[CPU|ARM|LDRSB] TODO: Affect the CPSR", .{});
},
0b11 => {
// LDRSH
cpu.r[rd] = util.u32SignExtend(16, @as(u32, bus.read16(address)));
std.debug.panic("[CPU|ARM|LDRSH] TODO: Affect the CPSR", .{});
cpu.panic("[CPU|ARM|LDRSH] TODO: Affect the CPSR", .{});
},
}
} else {

2
src/cpu/arm/psr_transfer.zig
View File

@@ -30,7 +30,7 @@ pub fn psrTransfer(comptime I: bool, comptime R: bool, comptime kind: u2) InstrF
if (cpu.isPrivileged()) cpu.setCpsr(fieldMask(&cpu.cpsr, field_mask, right));
}
},
else => std.debug.panic("[CPU/PSR Transfer] Bits 21:220 of {X:0>8} are undefined", .{opcode}),
else => cpu.panic("[CPU/PSR Transfer] Bits 21:220 of {X:0>8} are undefined", .{opcode}),
}
}
}.inner;

2
src/cpu/thumb/format1.zig
View File

@@ -17,7 +17,7 @@ pub fn format1(comptime op: u2, comptime offset: u5) InstrFn {
0b00 => shifter.logicalLeft(true, &cpu.cpsr, cpu.r[rs], offset), // LSL
0b01 => shifter.logicalRight(true, &cpu.cpsr, cpu.r[rs], offset), // LSR
0b10 => shifter.arithmeticRight(true, &cpu.cpsr, cpu.r[rs], offset), // ASR
else => std.debug.panic("[CPU|THUMB|Fmt1] {} is an invalid op", .{op}),
else => cpu.panic("[CPU|THUMB|Fmt1] {} is an invalid op", .{op}),
};
// Equivalent to an ARM MOVS

4
src/cpu/thumb/format13.zig
View File

@@ -6,8 +6,8 @@ const InstrFn = @import("../../cpu.zig").ThumbInstrFn;
pub fn format13(comptime _: bool) InstrFn {
return struct {
fn inner(_: *Arm7tdmi, _: *Bus, _: u16) void {
std.debug.panic("[CPU|THUMB|Fmt13] Implement Format 13 THUMB Instructions", .{});
fn inner(cpu: *Arm7tdmi, _: *Bus, _: u16) void {
cpu.panic("[CPU|THUMB|Fmt13] Implement Format 13 THUMB Instructions", .{});
}
}.inner;
}

2
src/cpu/thumb/format16.zig
View File

@@ -14,7 +14,7 @@ pub fn format16(comptime cond: u4) InstrFn {
const offset = u32SignExtend(8, opcode & 0xFF) << 1;
const should_execute = switch (cond) {
0xE, 0xF => std.debug.panic("[CPU/THUMB] Undefined conditional branch with condition {}", .{cond}),
0xE, 0xF => cpu.panic("[CPU/THUMB] Undefined conditional branch with condition {}", .{cond}),
else => checkCond(cpu.cpsr, cond),
};

2
src/cpu/thumb/format5.zig
View File

@@ -20,7 +20,7 @@ pub fn format5(comptime op: u2, comptime h1: u1, comptime h2: u1) InstrFn {
cpu.cpsr.t.write(cpu.r[src] & 1 == 1);
cpu.r[15] = cpu.r[src] & 0xFFFF_FFFE;
},
else => std.debug.panic("[CPU|THUMB|Fmt5] {} is an invalid op", .{op}),
else => cpu.panic("[CPU|THUMB|Fmt5] {} is an invalid op", .{op}),
}
}
}.inner;