feat: implement RTC Read/Writes
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parent
c977f3f965
commit
089c5fa025
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@ -231,22 +231,18 @@ const Gpio = struct {
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const Device = struct {
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ptr: ?*anyopaque,
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// TODO: Maybe make this comptime known? Removes some if statements
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kind: Kind,
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kind: Kind, // TODO: Make comptime known?
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const Kind = enum {
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Rtc,
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None,
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};
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const Kind = enum { Rtc, None };
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fn step(self: *Device, value: u4) void {
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switch (self.kind) {
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.Rtc => {
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fn step(self: *Device, value: u4) u4 {
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return switch (self.kind) {
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.Rtc => blk: {
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const clock = @ptrCast(*Clock, @alignCast(@alignOf(*Clock), self.ptr.?));
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clock.step(Clock.Data{ .raw = value });
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break :blk clock.step(Clock.Data{ .raw = value });
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},
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.None => {},
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}
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.None => value,
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};
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}
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fn init(kind: Kind, ptr: ?*anyopaque) Device {
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@ -294,17 +290,13 @@ const Gpio = struct {
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}
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fn write(self: *This, comptime reg: Register, value: if (reg == .Control) u1 else u4) void {
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log.debug("RTC: Wrote 0b{b:0>4} to {}", .{ value, reg });
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// if (reg == .Data)
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// log.err("original: 0b{b:0>4} masked: 0b{b:0>4} result: 0b{b:0>4}", .{ self.data, value & self.direction, self.data | (value & self.direction) });
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switch (reg) {
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.Data => {
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const masked_value = value & self.direction;
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self.device.step(masked_value);
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self.data = masked_value;
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// The value which is actually stored in the GPIO register
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// might be modified by the device implementing the GPIO interface e.g. RTC reads
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self.data = self.device.step(masked_value);
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},
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.Direction => self.direction = value,
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.Control => self.cnt = value,
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@ -328,6 +320,7 @@ const Clock = struct {
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cmd: Command,
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writer: Writer,
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reader: Reader,
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state: State,
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cnt: Control,
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@ -355,49 +348,162 @@ const Clock = struct {
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Read: Register,
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};
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const Reader = struct {
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i: u4,
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count: u8,
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/// Reads a bit from RTC registers. Which bit it reads is dependent on
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///
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/// 1. The RTC State Machine, whitch tells us which register we're accessing
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/// 2. A `count`, which keeps track of which byte is currently being read
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/// 3. An index, which keeps track of which bit of the byte determined by `count` is being read
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fn read(self: *Reader, clock: *const Clock, register: Register) u1 {
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const idx = @intCast(u3, self.i);
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defer self.i += 1;
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// FIXME: What do I do about the unused bits?
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return switch (register) {
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.Control => @truncate(u1, switch (self.count) {
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0 => clock.cnt.raw >> idx,
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else => {
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log.err("RTC: {} is only 1 byte wide", .{register});
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@panic("Out-of-bounds RTC read");
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},
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}),
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.DateTime => @truncate(u1, switch (self.count) {
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// Date
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0 => clock.year >> idx,
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1 => @as(u8, clock.month) >> idx,
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2 => @as(u8, clock.day) >> idx,
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3 => @as(u8, clock.day_of_week) >> idx,
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// Time
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4 => @as(u8, clock.hour) >> idx,
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5 => @as(u8, clock.minute) >> idx,
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6 => @as(u8, clock.second) >> idx,
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else => {
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log.err("RTC: {} is only 7 bytes wide", .{register});
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@panic("Out-of-bounds RTC read");
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},
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}),
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.Time => @truncate(u1, switch (self.count) {
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0 => @as(u8, clock.hour) >> idx,
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1 => @as(u8, clock.minute) >> idx,
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2 => @as(u8, clock.second) >> idx,
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else => {
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log.err("RTC: {} is only 3 bytes wide", .{register});
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@panic("Out-of-bounds RTC read");
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},
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}),
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};
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}
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/// Is true when a Reader has read a u8's worth of bits
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fn finished(self: *const Reader) bool {
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return self.i >= 8;
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}
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/// Resets the index used to shift bits out of RTC registers
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/// and `count`, which is used to keep track of which byte we're reading
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/// is incremeneted
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fn lap(self: *Reader) void {
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self.i = 0;
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self.count += 1;
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}
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/// Resets the state of a `Reader` in preparation for a future
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/// read command
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fn reset(self: *Reader) void {
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self.i = 0;
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self.count = 0;
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}
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};
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const Writer = struct {
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buf: u8,
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i: u4,
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/// The Number of bytes written to since last reset
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/// The Number of bytes written since last reset
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count: u8,
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/// Append a bit to the internal bit buffer (aka an integer)
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fn push(self: *Writer, value: u1) void {
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const idx = @intCast(u3, self.i);
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self.buf = (self.buf & ~(@as(u8, 1) << idx)) | @as(u8, value) << idx;
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self.i += 1;
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}
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/// Takes the contents of the internal buffer and writes it to an RTC register
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/// Where it writes to is dependent on:
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///
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/// 1. The RTC State Machine, whitch tells us which register we're accessing
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/// 2. A `count`, which keeps track of which byte is currently being read
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fn write(self: *const Writer, clock: *Clock, register: Register) void {
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// FIXME: What do do about unused bits?
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switch (register) {
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.Control => switch (self.count) {
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0 => clock.cnt.raw = self.buf,
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else => {
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log.err("RTC :{} is only 1 byte wide", .{register});
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@panic("Out-of-bounds RTC write");
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},
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},
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.DateTime => switch (self.count) {
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// Date
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0 => clock.year = @truncate(@TypeOf(clock.year), self.buf),
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1 => clock.month = @truncate(@TypeOf(clock.month), self.buf),
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2 => clock.day = @truncate(@TypeOf(clock.day), self.buf),
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3 => clock.day_of_week = @truncate(@TypeOf(clock.day_of_week), self.buf),
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// Time
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4 => clock.hour = @truncate(@TypeOf(clock.hour), self.buf),
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5 => clock.minute = @truncate(@TypeOf(clock.minute), self.buf),
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6 => clock.second = @truncate(@TypeOf(clock.second), self.buf),
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else => {
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log.err("RTC :{} is only 1 byte wide", .{register});
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@panic("Out-of-bounds RTC write");
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},
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},
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.Time => switch (self.count) {
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// Time
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0 => clock.hour = @truncate(@TypeOf(clock.hour), self.buf),
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1 => clock.minute = @truncate(@TypeOf(clock.minute), self.buf),
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2 => clock.second = @truncate(@TypeOf(clock.second), self.buf),
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else => {
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log.err("RTC :{} is only 1 byte wide", .{register});
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@panic("Out-of-bounds RTC write");
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},
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},
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}
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}
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/// Is true when 8 bits have been shifted into the internal buffer
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fn finished(self: *const Writer) bool {
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return self.i >= 8;
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}
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/// Resets the internal buffer
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/// resets the index used to shift bits into the internal buffer
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/// increments `count` (which keeps track of byte offsets) by one
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fn lap(self: *Writer) void {
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self.buf = 0;
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self.i = 0;
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self.count += 1;
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}
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/// Resets `Writer` to a clean state in preparation for a future write command
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fn reset(self: *Writer) void {
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self.buf = 0;
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self.i = 0;
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self.count = 0;
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}
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fn isFinished(self: *const Writer) bool {
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return self.i >= 8;
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}
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fn getCount(self: *const Writer) u8 {
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return self.count;
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}
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fn getValue(self: *const Writer) u8 {
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return self.buf;
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}
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};
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const Command = struct {
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buf: u8,
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i: u4,
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fn push(self: *Command, value: u1) void {
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fn write(self: *Command, value: u1) void {
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const idx = @intCast(u3, self.i);
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self.buf = (self.buf & ~(@as(u8, 1) << idx)) | @as(u8, value) << idx;
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self.i += 1;
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@ -413,17 +519,25 @@ const Clock = struct {
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}
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fn getCommand(self: *const Command) u8 {
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// If high Nybble does not contain 0x6, reverse the order of the nybbles.
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// For some reason RTC commands can be LSB or MSB which is funny
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return if (self.buf >> 4 & 0xF == 0x6) self.buf else (self.buf & 0xF) << 4 | (self.buf >> 4 & 0xF);
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// If High Nybble is 0x6, no need to switch the endianness
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if (self.buf >> 4 & 0xF == 0x6) return self.buf;
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// Turns out reversing the order of bits isn't trivial at all
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// https://stackoverflow.com/questions/2602823/in-c-c-whats-the-simplest-way-to-reverse-the-order-of-bits-in-a-byte
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var ret = self.buf;
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ret = (ret & 0xF0) >> 4 | (ret & 0x0F) << 4;
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ret = (ret & 0xCC) >> 2 | (ret & 0x33) << 2;
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ret = (ret & 0xAA) >> 1 | (ret & 0x55) << 1;
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return ret;
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}
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fn handleCommand(self: *const Command, rtc: *Clock) State {
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const command = self.getCommand();
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log.info("RTC: Failed to handle Command 0b{b:0>8} aka 0x{X:0>2}", .{ command, command });
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log.debug("RTC: Handling Command 0x{X:0>2} [0b{b:0>8}]", .{ command, command });
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const is_write = command & 1 == 0;
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const rtc_register = @intCast(u3, command >> 1 & 0x7); // TODO: Make Truncate
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const rtc_register = @truncate(u3, command >> 1 & 0x7);
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if (is_write) {
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return switch (rtc_register) {
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@ -478,6 +592,7 @@ const Clock = struct {
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ptr.* = .{
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.cmd = .{ .buf = 0, .i = 0 },
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.writer = .{ .buf = 0, .i = 0, .count = 0 },
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.reader = .{ .i = 0, .count = 0 },
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.state = .Idle,
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.cnt = .{ .raw = 0 },
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.year = 0,
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@ -492,74 +607,103 @@ const Clock = struct {
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};
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}
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fn step(self: *This, value: Data) void {
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fn step(self: *This, value: Data) u4 {
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const cache: Data = .{ .raw = self.gpio.data };
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switch (self.state) {
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.Idle => {
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// If SCK is high and CS rises, then prepare for Command
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return switch (self.state) {
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.Idle => blk: {
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// FIXME: Maybe check incoming value to see if SCK is also high?
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if (cache.sck.read()) {
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if (!cache.cs.read() and value.cs.read()) {
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log.err("RTC: Entering Command Mode", .{});
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log.debug("RTC: Entering Command Mode", .{});
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self.state = .CommandInput;
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self.cmd.reset();
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}
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}
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break :blk @truncate(u4, value.raw);
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},
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.CommandInput => {
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.CommandInput => blk: {
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if (!value.cs.read()) log.err("RTC: Expected CS to be set during {}, however CS was cleared", .{self.state});
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if (!cache.sck.read() and value.sck.read()) {
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// If SCK rises, sample SIO
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log.debug("RTC: Sampled 0b{b:0>1} from SIO", .{@boolToInt(value.sio.read())});
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self.cmd.push(@boolToInt(value.sio.read()));
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if (!cache.sck.read() and value.sck.read()) {
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self.cmd.write(@boolToInt(value.sio.read()));
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if (self.cmd.isFinished()) {
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self.state = self.cmd.handleCommand(self);
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log.debug("RTC: Switching to {}", .{self.state});
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}
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}
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break :blk @truncate(u4, value.raw);
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},
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State{ .Write = .Control } => {
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.Write => |register| blk: {
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if (!value.cs.read()) log.err("RTC: Expected CS to be set during {}, however CS was cleared", .{self.state});
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if (!cache.sck.read() and value.sck.read()) {
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// If SCK rises, sample SIO
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log.debug("RTC: Sampled 0b{b:0>1} from SIO", .{@boolToInt(value.sio.read())});
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if (!cache.sck.read() and value.sck.read()) {
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self.writer.push(@boolToInt(value.sio.read()));
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if (self.writer.isFinished()) {
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self.writer.lap();
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self.cnt.raw = self.writer.getValue();
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const register_width: u32 = switch (register) {
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.Control => 1,
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.DateTime => 7,
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.Time => 3,
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};
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// FIXME: Move this to a constant or something
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if (self.writer.getCount() == 1) {
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if (self.writer.finished()) {
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self.writer.write(self, register); // write inner buffer to RTC register
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self.writer.lap();
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if (self.writer.count == register_width) {
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self.writer.reset();
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self.state = .Idle;
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}
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}
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}
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break :blk @truncate(u4, value.raw);
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},
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else => {
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// TODO: Implement Read/Writes for Date/Time and Time and Control
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log.err("RTC: Ignored request to handle {} command", .{self.state});
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.Read => |register| blk: {
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if (!value.cs.read()) log.err("RTC: Expected CS to be set during {}, however CS was cleared", .{self.state});
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var ret = value;
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// if SCK rises, sample SIO
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if (!cache.sck.read() and value.sck.read()) {
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ret.sio.write(self.reader.read(self, register) == 0b1);
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const register_width: u32 = switch (register) {
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.Control => 1,
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.DateTime => 7,
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.Time => 3,
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};
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if (self.reader.finished()) {
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self.reader.lap();
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if (self.reader.count == register_width) {
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self.reader.reset();
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self.state = .Idle;
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},
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}
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}
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}
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break :blk @truncate(u4, ret.raw);
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},
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};
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}
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fn reset(self: *This) void {
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// mGBA and NBA only zero the control register
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// we'll do the same
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// mGBA and NBA only zero the control register. We will do the same
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log.debug("RTC: Reset (control register was zeroed)", .{});
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self.cnt.raw = 0;
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log.info("RTC: Reset executed (control register was zeroed)", .{});
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}
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fn irq(self: *This) void {
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// TODO: Confirm that this is the right behaviour
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log.debug("RTC: Force GamePak IRQ", .{});
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self.cpu.bus.io.irq.game_pak.set();
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self.cpu.handleInterrupt();
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}
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