chore: set correct values for select banked registers on fast boot
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parent
997dc1314c
commit
0546b1c308
20
src/cpu.zig
20
src/cpu.zig
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@ -65,8 +65,8 @@ pub const Arm7tdmi = struct {
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.Supervisor => 1,
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.Supervisor => 1,
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.Abort => 2,
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.Abort => 2,
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.Undefined => 3,
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.Undefined => 3,
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.IRQ => 4,
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.Irq => 4,
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.FIQ => 5,
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.Fiq => 5,
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};
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};
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}
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}
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@ -75,8 +75,8 @@ pub const Arm7tdmi = struct {
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.Supervisor => 0,
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.Supervisor => 0,
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.Abort => 1,
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.Abort => 1,
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.Undefined => 2,
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.Undefined => 2,
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.IRQ => 3,
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.Irq => 3,
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.FIQ => 4,
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.Fiq => 4,
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else => std.debug.panic("{} does not have a SPSR Register", .{mode}),
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else => std.debug.panic("{} does not have a SPSR Register", .{mode}),
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};
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};
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}
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}
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@ -110,7 +110,7 @@ pub const Arm7tdmi = struct {
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// Bank R8 -> r12
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// Bank R8 -> r12
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var r: usize = 8;
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var r: usize = 8;
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while (r <= 12) : (r += 1) {
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while (r <= 12) : (r += 1) {
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self.banked_fiq[(r - 8) * 2 + if (now == .FIQ) @as(usize, 1) else 0] = self.r[r];
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self.banked_fiq[(r - 8) * 2 + if (now == .Fiq) @as(usize, 1) else 0] = self.r[r];
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}
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}
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// Bank r13, r14, SPSR
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// Bank r13, r14, SPSR
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@ -129,7 +129,7 @@ pub const Arm7tdmi = struct {
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// Grab R8 -> R12
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// Grab R8 -> R12
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r = 8;
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r = 8;
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while (r <= 12) : (r += 1) {
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while (r <= 12) : (r += 1) {
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self.r[r] = self.banked_fiq[(r - 8) * 2 + if (next == .FIQ) @as(usize, 1) else 0];
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self.r[r] = self.banked_fiq[(r - 8) * 2 + if (next == .Fiq) @as(usize, 1) else 0];
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}
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}
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// Grab r13, r14, SPSR
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// Grab r13, r14, SPSR
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@ -157,7 +157,9 @@ pub const Arm7tdmi = struct {
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self.r[14] = 0x0000_0000;
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self.r[14] = 0x0000_0000;
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self.r[15] = 0x0800_0000;
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self.r[15] = 0x0800_0000;
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// TODO: Set sp_irq = 0x0300_7FA0, sp_svc = 0x0300_7FE0
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// Set r13_irq and r14_svc to their respective values
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self.banked_r[bankedIdx(.Irq) * 2 + 0] = 0x0300_7FA0;
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self.banked_r[bankedIdx(.Supervisor) * 2 + 0] = 0x0300_7FE0;
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self.cpsr.raw = 0x6000001F;
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self.cpsr.raw = 0x6000001F;
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}
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}
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@ -374,8 +376,8 @@ pub const PSR = extern union {
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const Mode = enum(u5) {
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const Mode = enum(u5) {
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User = 0b10000,
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User = 0b10000,
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FIQ = 0b10001,
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Fiq = 0b10001,
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IRQ = 0b10010,
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Irq = 0b10010,
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Supervisor = 0b10011,
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Supervisor = 0b10011,
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Abort = 0b10111,
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Abort = 0b10111,
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Undefined = 0b11011,
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Undefined = 0b11011,
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