2022-02-04 08:00:48 +00:00
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const std = @import("std");
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const Bus = @import("../../Bus.zig");
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const Arm7tdmi = @import("../../cpu.zig").Arm7tdmi;
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const InstrFn = @import("../../cpu.zig").ThumbInstrFn;
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2022-03-17 01:28:24 +00:00
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const rotr = @import("../../util.zig").rotr;
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2022-02-04 08:00:48 +00:00
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pub fn format6(comptime rd: u3) InstrFn {
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return struct {
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fn inner(cpu: *Arm7tdmi, bus: *Bus, opcode: u16) void {
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// LDR
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const offset = (opcode & 0xFF) << 2;
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cpu.r[rd] = bus.read32((cpu.r[15] + 2 & 0xFFFF_FFFD) + offset);
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}
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}.inner;
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}
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2022-03-01 00:38:50 +00:00
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const sext = @import("../../util.zig").sext;
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2022-02-04 08:00:48 +00:00
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pub fn format78(comptime op: u2, comptime T: bool) InstrFn {
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return struct {
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fn inner(cpu: *Arm7tdmi, bus: *Bus, opcode: u16) void {
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const ro = opcode >> 6 & 0x7;
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const rb = opcode >> 3 & 0x7;
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const rd = opcode & 0x7;
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const address = cpu.r[rb] + cpu.r[ro];
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if (T) {
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2022-02-05 18:50:34 +00:00
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// Format 8
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2022-02-04 08:00:48 +00:00
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switch (op) {
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0b00 => {
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// STRH
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bus.write16(address & 0xFFFF_FFFE, @truncate(u16, cpu.r[rd]));
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},
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0b01 => {
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2022-02-05 18:50:34 +00:00
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// LDSB
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2022-03-01 00:38:50 +00:00
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cpu.r[rd] = sext(8, bus.read8(address));
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2022-02-05 18:50:34 +00:00
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},
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0b10 => {
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2022-02-04 08:00:48 +00:00
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// LDRH
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const value = bus.read16(address & 0xFFFF_FFFE);
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2022-03-17 01:28:24 +00:00
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cpu.r[rd] = rotr(u32, value, 8 * (address & 1));
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2022-02-04 08:00:48 +00:00
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},
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0b11 => {
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2022-02-05 21:12:25 +00:00
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// LDRSH
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const value = if (address & 1 == 1) blk: {
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2022-03-01 00:38:50 +00:00
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break :blk sext(8, bus.read8(address));
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2022-02-05 21:12:25 +00:00
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} else blk: {
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2022-03-01 00:38:50 +00:00
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break :blk sext(16, bus.read16(address));
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2022-02-05 21:12:25 +00:00
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};
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2022-03-17 01:28:24 +00:00
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cpu.r[rd] = rotr(u32, value, 8 * (address & 1));
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2022-02-04 08:00:48 +00:00
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},
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}
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} else {
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2022-02-05 18:50:34 +00:00
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// Format 7
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2022-02-04 08:00:48 +00:00
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switch (op) {
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0b00 => {
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// STR
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bus.write32(address & 0xFFFF_FFFC, cpu.r[rd]);
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},
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0b01 => {
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// STRB
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bus.write8(address, @truncate(u8, cpu.r[rd]));
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},
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0b10 => {
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// LDR
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const value = bus.read32(address & 0xFFFF_FFFC);
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2022-03-17 01:28:24 +00:00
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cpu.r[rd] = rotr(u32, value, 8 * (address & 0x3));
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2022-02-04 08:00:48 +00:00
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},
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0b11 => {
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// LDRB
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cpu.r[rd] = bus.read8(address);
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},
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}
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}
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}
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}.inner;
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}
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pub fn format9(comptime B: bool, comptime L: bool, comptime offset: u5) InstrFn {
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return struct {
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fn inner(cpu: *Arm7tdmi, bus: *Bus, opcode: u16) void {
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const rb = opcode >> 3 & 0x7;
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const rd = opcode & 0x7;
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if (L) {
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if (B) {
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// LDRB
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const address = cpu.r[rb] + offset;
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cpu.r[rd] = bus.read8(address);
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} else {
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// LDR
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const address = cpu.r[rb] + (@as(u32, offset) << 2);
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const value = bus.read32(address & 0xFFFF_FFFC);
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2022-03-17 01:28:24 +00:00
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cpu.r[rd] = rotr(u32, value, 8 * (address & 0x3));
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2022-02-04 08:00:48 +00:00
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}
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} else {
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if (B) {
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// STRB
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const address = cpu.r[rb] + offset;
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bus.write8(address, @truncate(u8, cpu.r[rd]));
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} else {
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// STR
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const address = cpu.r[rb] + (@as(u32, offset) << 2);
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bus.write32(address & 0xFFFF_FFFC, cpu.r[rd]);
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}
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}
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}
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}.inner;
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}
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pub fn format10(comptime L: bool, comptime offset: u5) InstrFn {
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return struct {
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fn inner(cpu: *Arm7tdmi, bus: *Bus, opcode: u16) void {
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const rb = opcode >> 3 & 0x7;
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const rd = opcode & 0x7;
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2022-02-13 04:34:47 +00:00
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const address = cpu.r[rb] + (@as(u6, offset) << 1);
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2022-02-04 08:00:48 +00:00
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if (L) {
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// LDRH
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const value = bus.read16(address & 0xFFFF_FFFE);
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2022-03-17 01:28:24 +00:00
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cpu.r[rd] = rotr(u32, value, 8 * (address & 1));
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2022-02-04 08:00:48 +00:00
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} else {
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// STRH
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bus.write16(address & 0xFFFF_FFFE, @truncate(u16, cpu.r[rd]));
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}
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}
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}.inner;
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}
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pub fn format11(comptime L: bool, comptime rd: u3) InstrFn {
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return struct {
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fn inner(cpu: *Arm7tdmi, bus: *Bus, opcode: u16) void {
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const offset = (opcode & 0xFF) << 2;
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const address = cpu.r[13] + offset;
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if (L) {
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// LDR
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const value = bus.read32(address & 0xFFFF_FFFC);
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2022-03-17 01:28:24 +00:00
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cpu.r[rd] = rotr(u32, value, 8 * (address & 0x3));
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2022-02-04 08:00:48 +00:00
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} else {
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// STR
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bus.write32(address & 0xFFFF_FFFC, cpu.r[rd]);
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}
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}
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}.inner;
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}
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