56 lines
2.1 KiB
Zig
56 lines
2.1 KiB
Zig
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const std = @import("std");
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const Bus = @import("../Bus.zig");
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const Arm7tdmi = @import("../cpu.zig").Arm7tdmi;
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const InstrFn = @import("../cpu.zig").InstrFn;
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pub fn blockDataTransfer(comptime P: bool, comptime U: bool, comptime S: bool, comptime W: bool, comptime L: bool) InstrFn {
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return struct {
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fn inner(cpu: *Arm7tdmi, bus: *Bus, opcode: u32) void {
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const rn = opcode >> 16 & 0xF;
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var base = cpu.r[rn];
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// TODO: For Performance (?) if U we got from 0 -> 0xF, if !U, 0xF -> 0
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// we can do this and have it be fast because of comptime, baby!
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if (!U) {
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var count: u32 = 0;
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var i: u5 = 0;
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while (i < 0x10) : (i += 1) {
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count += opcode >> i & 1;
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}
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base -= count * 4;
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}
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var address = if (@boolToInt(P) ^ @boolToInt(U) == 0) base + 4 else base;
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if (S and opcode >> 15 & 1 == 0) std.debug.panic("[CPU] TODO: STM/LDM with S set but R15 not in transfer list", .{});
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var i: u5 = 0;
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while (i < 0x10) : (i += 1) {
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if (opcode >> i & 1 == 1) {
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if (L) {
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cpu.r[i] = bus.read32(address);
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if (S and i == 0xF) std.debug.panic("[CPU] TODO: SPSR_<mode> is transferred to CPSR", .{});
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} else {
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if (i == 0xF) {
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if (!S) {
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// TODO: Assure that this is Address of STM instruction + 12
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bus.write32(address, cpu.r[i] + (12 - 4));
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} else {
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std.debug.panic("[CPU] TODO: STM with S set and R15 in transfer list", .{});
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}
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} else {
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bus.write32(address, cpu.r[i]);
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}
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}
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address += 4;
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}
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}
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if (W and P or !P) cpu.r[rn] = if (U) address - 4 else base;
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}
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}.inner;
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}
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