57 lines
1.8 KiB
Zig
57 lines
1.8 KiB
Zig
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const std = @import("std");
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const cpu_mod = @import("../cpu.zig");
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const Bus = @import("../bus.zig").Bus;
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const ARM7TDMI = cpu_mod.ARM7TDMI;
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const InstrFn = cpu_mod.InstrFn;
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pub fn comptimeDataProcessing(comptime I: bool, comptime S: bool, comptime instrKind: u4) InstrFn {
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return struct {
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fn dataProcessing(cpu: *ARM7TDMI, _: *Bus, opcode: u32) void {
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const rd = opcode >> 12 & 0xF;
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const op1 = opcode >> 16 & 0xF;
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var op2: u32 = undefined;
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if (I) {
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op2 = std.math.rotr(u32, opcode & 0xFF, (opcode >> 8 & 0xF) << 1);
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} else {
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op2 = reg_op2(cpu, opcode);
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}
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switch (instrKind) {
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0x4 => {
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cpu.r[rd] = cpu.r[op1] + op2;
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if (S) std.debug.panic("TODO: implement ADD condition codes", .{});
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},
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0xD => {
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cpu.r[rd] = op2;
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if (S) std.debug.panic("TODO: implement MOV condition codes", .{});
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},
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else => std.debug.panic("TODO: implement data processing type {}", .{instrKind}),
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}
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}
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}.dataProcessing;
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}
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fn reg_op2(cpu: *const ARM7TDMI, opcode: u32) u32 {
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var amount: u32 = undefined;
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if (opcode >> 4 & 0x01 == 0x01) {
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amount = cpu.r[opcode >> 8 & 0xF] & 0xFF;
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} else {
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amount = opcode >> 7 & 0x1F;
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}
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const rm = opcode & 0xF;
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const r_val = cpu.r[rm];
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return switch (opcode >> 5 & 0x03) {
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0b00 => r_val << @truncate(u5, amount),
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0b01 => r_val >> @truncate(u5, amount),
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0b10 => @bitCast(u32, @bitCast(i32, r_val) >> @truncate(u5, amount)),
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0b11 => std.math.rotr(u32, r_val, amount),
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else => unreachable,
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};
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}
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