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94 Commits

Author SHA1 Message Date
Rekai Nyangadzayi Musuka 4516ca8477 chore: run cargo fix
continuous-integration/drone/push Build is passing Details
2021-09-12 04:56:39 -03:00
Rekai Nyangadzayi Musuka 6087e3b20b chore: remove Cycle struct and begin scheduler design 2021-09-12 04:56:34 -03:00
Rekai Nyangadzayi Musuka 6215eccb2f chore(cpu): merge halted and state properties 2021-08-15 23:26:01 -05:00
Rekai Nyangadzayi Musuka 1b78b248a3 chore: minor edits to documentation 2021-08-14 17:51:09 -05:00
Rekai Nyangadzayi Musuka 5d6df46a2d fix(cpu): reimplement instruction handling
continuous-integration/drone/push Build is passing Details
2021-08-14 17:23:45 -05:00
Rekai Nyangadzayi Musuka 8c9567b610 chore(cpu): rename discriminants of ImeState enum 2021-08-14 16:42:15 -05:00
Rekai Nyangadzayi Musuka 8625bec059 feat: clock bus on instruction read-write
continuous-integration/drone/push Build is failing Details 
Commit also includes general work towards passing mem-timings.

Note: while cpu_instrs.gb passes, instr_timing.gb and mem_timing.gb both
are stuck in infinite loops (Currently, it seems like a timing issue).
This is a major regression that hopefully shouldn't last for too long.
 2021-08-14 00:10:51 -05:00
Rekai Nyangadzayi Musuka 0637b771e3 chore(instr): implement copy and clone on instruction enum
continuous-integration/drone/push Build is failing Details
2021-08-05 20:04:39 -05:00
Rekai Nyangadzayi Musuka 4d6fc95130 chore: remove premature optimizations 2021-08-02 21:52:12 -05:00
Rekai Nyangadzayi Musuka 7112cd15e3 chore(cpu): refactor SM83 implementation
continuous-integration/drone/push Build is passing Details 
Instruction::decode no longer requires mutable access to the CPU
 2021-07-31 20:29:13 -05:00
Rekai Nyangadzayi Musuka 903cfacad3 fix(apu): replace mpsc with spsc ringbuffer
continuous-integration/drone/push Build is passing Details
2021-07-28 02:01:04 -05:00
Rekai Nyangadzayi Musuka 9d0e099a97 chore: remove unnecessary derivations from structs 2021-07-28 00:09:07 -05:00
Rekai Nyangadzayi Musuka 9b3a5d49d2 chore: update error messages in expect() calls 2021-07-08 18:50:58 -05:00
Rekai Nyangadzayi Musuka ef4e54aba6 chore: restrict what should be pub or not 2021-06-06 20:47:11 -05:00
Rekai Nyangadzayi Musuka 878edd4082 chore: replace pub with pub(crate) when possible 2021-06-06 19:14:28 -05:00
Rekai Nyangadzayi Musuka 811a9f9cc9 feat(dma): implement non-working dma transfer 2021-06-04 13:47:06 -05:00
Rekai Nyangadzayi Musuka c60bf704ff chore(cpu): Ensure Cycles is the size of an u32 2021-06-02 23:09:45 -05:00
Rekai Nyangadzayi Musuka b1bf6c5868 feat: integrate eui and pixels-rs for debug info 2021-06-02 01:50:35 -05:00
Rekai Nyangadzayi Musuka 834b1bd9fd chore(cpu): remove branching code in instructions 
also, rename a couple of methods
 2021-05-04 00:50:22 -05:00
Rekai Nyangadzayi Musuka 6f4f872765 fix(cpu): pass SLA (HL) and SRA (HL) tests from blargg 2021-04-22 20:38:13 -05:00
Rekai Nyangadzayi Musuka cf3b79f0dc chore(cpu): move RST behaviour to a method 2021-04-07 23:05:22 -05:00
Rekai Nyangadzayi Musuka 0eb40a8109 feat: comply with the fourth individual blargg test rom 2021-04-07 22:37:33 -05:00
Rekai Nyangadzayi Musuka 067ed03de3 feat: comply with test 03 of blargg's cpu_instrs test rom 2021-04-07 20:12:05 -05:00
Rekai Nyangadzayi Musuka 748c32c446 fix(cpu): use enums only of maintaining IME register state 2021-04-05 01:10:03 -05:00
Rekai Nyangadzayi Musuka 77c7c610d0 chore(cpu): rename ImeSet to ImeEnabled 2021-04-05 00:53:46 -05:00
Rekai Nyangadzayi Musuka a15a6a25b6 feat(cpu): properly implement EI instruction 2021-04-05 00:52:12 -05:00
Rekai Nyangadzayi Musuka 4dd7a0d9ce chore: fix several clippy warnings 2021-04-04 01:19:39 -05:00
Rekai Nyangadzayi Musuka cb1bcdb859 feat(cpu): implement DAA instruction 2021-04-04 01:03:44 -05:00
Rekai Nyangadzayi Musuka 2b05571c49 chore: rename Cycles newtype to Cycle 2021-03-27 12:10:18 -05:00
Rekai Nyangadzayi Musuka bce14348f8 feat: enable halt and rework timer registers 2021-03-27 11:56:47 -05:00
Rekai Nyangadzayi Musuka 15781b3d5a fix(instructions): correct the flags being set in ADD HL, r16 2021-03-26 20:19:48 -05:00
Rekai Nyangadzayi Musuka a82e3d3372 feat: implement HALT behaviour 
note: while the logic is there, the instruction currently does not do
anything because we don't halde it in Cpu::step(). The code that does is
currently commented out and there should be some underlying bugs still
present. Nevertheless it is a good start
 2021-03-23 23:05:27 -05:00
Rekai Nyangadzayi Musuka e5fb07c4d1 chore: refactor parts of instruction.rs 2021-03-23 20:22:11 -05:00
Rekai Nyangadzayi Musuka 501d93c37b chore: clean up code in one instruction 2021-03-23 18:21:59 -05:00
Rekai Nyangadzayi Musuka 1b7d778c1d chore: clean up some instruction code 2021-03-23 02:11:40 -05:00
Rekai Nyangadzayi Musuka 342e6616ac chore: improve unreachable! and panic! error messages 2021-03-22 22:33:56 -05:00
Rekai Nyangadzayi Musuka 2813b762dd chore: replace select unreachable! macros with todo! and unreachable! 2021-03-22 21:52:28 -05:00
Rekai Nyangadzayi Musuka 9301a36682 chore: remove all unwraps from the project 2021-03-22 21:48:12 -05:00
Rekai Nyangadzayi Musuka d7d9fd857f fix: squash bugs in cpu intrucion implementation 2021-03-21 21:16:23 -05:00
Rekai Nyangadzayi Musuka dc45688e4f feat: implement timers 2021-03-21 03:03:03 -05:00
Rekai Nyangadzayi Musuka d76b3b6101 chore: make Cycles::new a const fn 2021-03-20 19:55:39 -05:00
Rekai Nyangadzayi Musuka 2401cf7190 chore: implement default for cycles 2021-03-20 19:55:02 -05:00
Rekai Nyangadzayi Musuka 558f9e7c72 feat: implement cpu interrupts 2021-03-18 21:07:19 -05:00
Rekai Nyangadzayi Musuka 8c25e6f976 chore: fix spelling mistake 2021-03-16 02:31:07 -05:00
Rekai Nyangadzayi Musuka 19f642eafe chore: make clippy happy 2021-03-16 01:05:13 -05:00
Rekai Nyangadzayi Musuka 3b5d94adfc fix: reimplement flags register to be a bitfield 2021-03-15 23:35:20 -05:00
Rekai Nyangadzayi Musuka d78a50fefc chore: fix tests and simplify CI build 2021-01-27 22:17:01 -06:00
Rekai Nyangadzayi Musuka 96bfc43312 chore: fix spelling errors 2021-01-19 22:44:48 -06:00
Rekai Nyangadzayi Musuka 842e670807 fix: replace MathTarget::HL and ::SP with already-existing enums 2021-01-19 02:05:04 -06:00
Rekai Nyangadzayi Musuka 9143286e9c feat: implement more operator overrides for Cycles 2021-01-19 00:29:04 -06:00