chore(cpu): merge halted and state properties
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parent
a77d0a0f62
commit
6215eccb2f
36
src/cpu.rs
36
src/cpu.rs
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@ -14,8 +14,6 @@ pub struct Cpu {
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reg: Registers,
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flags: Flags,
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ime: ImeState,
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// TODO: Merge halted and state properties
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halted: Option<HaltKind>,
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state: State,
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}
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@ -45,24 +43,34 @@ impl Cpu {
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})
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}
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pub(crate) fn ime(&self) -> &ImeState {
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&self.ime
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pub(crate) fn ime(&self) -> ImeState {
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self.ime
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}
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pub(crate) fn set_ime(&mut self, state: ImeState) {
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self.ime = state;
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}
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pub(crate) fn halt(&mut self, state: HaltKind) {
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self.halted = Some(state);
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pub(crate) fn halt_cpu(&mut self, kind: HaltKind) {
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self.state = State::Halt(kind);
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}
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fn resume(&mut self) {
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self.halted = None;
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fn resume_execution(&mut self) {
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self.state = State::Execute;
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}
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pub(crate) fn halted(&self) -> Option<HaltKind> {
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self.halted
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pub(crate) fn is_halted(&self) -> bool {
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match self.state {
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State::Halt(_) => true,
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_ => false,
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}
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}
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pub(crate) fn halt_kind(&self) -> Option<HaltKind> {
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match self.state {
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State::Halt(kind) => Some(kind),
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_ => None,
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}
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}
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pub fn load_cartridge(&mut self, path: &str) -> std::io::Result<()> {
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@ -119,7 +127,7 @@ impl Cpu {
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return elapsed;
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}
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if let Some(kind) = self.halted() {
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if let Some(kind) = self.halt_kind() {
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use HaltKind::*;
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self.bus.clock();
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@ -192,7 +200,7 @@ impl Cpu {
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let enable = self.int_enable();
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// TODO: Ensure that this behaviour is correct
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if self.halted.is_some() {
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if self.is_halted() {
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// When we're here either a HALT with IME set or
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// a HALT with IME not set and No pending Interrupts was called
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@ -201,7 +209,7 @@ impl Cpu {
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// nothing actually needs to be added here. This is just documentation
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// since it's a bit weird why nothing is being done
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self.resume();
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self.resume_execution();
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}
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}
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@ -264,7 +272,7 @@ impl Cpu {
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#[derive(Debug, Clone, Copy)]
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enum State {
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Execute,
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// Halt,
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Halt(HaltKind),
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// Stop,
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}
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@ -590,12 +590,12 @@ impl Instruction {
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// HALT | Enter CPU low power consumption mode until interrupt occurs
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use HaltKind::*;
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let kind = match *cpu.ime() {
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let kind = match cpu.ime() {
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ImeState::Enabled => ImeEnabled,
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_ if cpu.int_request() & cpu.int_enable() != 0 => SomePending,
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_ => NonePending,
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};
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cpu.halt(kind);
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cpu.halt_cpu(kind);
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Cycle::new(4)
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}
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Instruction::ADC(source) => match source {
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