chore: clean up some instruction code
This commit is contained in:
parent
6f11640f24
commit
1b7d778c1d
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@ -132,11 +132,10 @@ impl Instruction {
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}
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(LDTarget::RegisterPair(pair), LDTarget::ImmediateWord(nn)) => {
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// LD rp[p], nn | Put value nn into register pair
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use RegisterPair::*;
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match pair {
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RegisterPair::BC
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| RegisterPair::DE
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| RegisterPair::HL
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| RegisterPair::SP => cpu.set_register_pair(pair, nn),
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BC | DE | HL | SP => cpu.set_register_pair(pair, nn),
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_ => unreachable!("There is no \"LD {:?}, nn\" instruction", pair),
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}
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Cycles::new(12)
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@ -231,38 +230,40 @@ impl Instruction {
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}
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(LDTarget::Register(lhs), LDTarget::Register(rhs)) => {
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// LD r[y], r[z] | Store value of RHS Register in LHS Register
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use InstrRegister::*;
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let rhs_value = {
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match rhs {
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InstrRegister::B
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| InstrRegister::C
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| InstrRegister::D
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| InstrRegister::E
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| InstrRegister::H
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| InstrRegister::L
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| InstrRegister::A => cpu.register(rhs.to_register()),
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InstrRegister::IndirectHL => {
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let addr = cpu.register_pair(RegisterPair::HL);
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cpu.read_byte(addr)
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match rhs {
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B | C | D | E | H | L | A => {
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let right = cpu.register(rhs.to_register());
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match lhs {
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B | C | D | E | H | L | A => {
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cpu.set_register(lhs.to_register(), right);
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Cycles::new(4)
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}
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IndirectHL => {
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let addr = cpu.register_pair(RegisterPair::HL);
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cpu.write_byte(addr, right);
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Cycles::new(8)
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}
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}
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}
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};
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match lhs {
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InstrRegister::B
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| InstrRegister::C
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| InstrRegister::D
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| InstrRegister::E
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| InstrRegister::H
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| InstrRegister::L
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| InstrRegister::A => {
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cpu.set_register(lhs.to_register(), rhs_value);
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Cycles::new(4)
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}
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InstrRegister::IndirectHL => {
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IndirectHL => {
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let addr = cpu.register_pair(RegisterPair::HL);
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cpu.write_byte(addr, rhs_value);
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Cycles::new(8)
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let right = cpu.read_byte(addr);
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match lhs {
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B | C | D | E | H | L | A => {
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cpu.set_register(lhs.to_register(), right);
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Cycles::new(8)
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}
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IndirectHL => {
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unreachable!(
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"There is no \"LD ({:?}), ({:?})\" instruction",
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lhs, rhs
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)
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}
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}
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}
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}
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}
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@ -300,43 +301,47 @@ impl Instruction {
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Instruction::JR(cond, offset) => {
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// JR cc[y - 4], d | If condition is true, then add d to current address and jump
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// JR d | Add d to current address and jump
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let prev = cpu.register_pair(RegisterPair::PC);
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let flags: &Flags = cpu.flags();
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let new_addr = Self::add_u16_i8_no_flags(prev, offset);
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let prev = cpu.register_pair(RegisterPair::PC);
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let addr = Self::add_u16_i8_no_flags(prev, offset);
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match cond {
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JumpCondition::Always => {
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cpu.set_register_pair(RegisterPair::PC, new_addr);
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cpu.set_register_pair(RegisterPair::PC, addr);
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Cycles::new(12)
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}
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JumpCondition::NotZero => {
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if !flags.z() {
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cpu.set_register_pair(RegisterPair::PC, new_addr);
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return Cycles::new(12);
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cpu.set_register_pair(RegisterPair::PC, addr);
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Cycles::new(12)
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} else {
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Cycles::new(8)
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}
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Cycles::new(8)
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}
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JumpCondition::Zero => {
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if flags.z() {
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cpu.set_register_pair(RegisterPair::PC, new_addr);
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return Cycles::new(12);
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cpu.set_register_pair(RegisterPair::PC, addr);
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Cycles::new(12)
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} else {
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Cycles::new(8)
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}
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Cycles::new(8)
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}
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JumpCondition::NotCarry => {
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if !flags.c() {
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cpu.set_register_pair(RegisterPair::PC, new_addr);
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return Cycles::new(12);
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cpu.set_register_pair(RegisterPair::PC, addr);
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Cycles::new(12)
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} else {
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Cycles::new(8)
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}
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Cycles::new(8)
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}
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JumpCondition::Carry => {
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if flags.c() {
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cpu.set_register_pair(RegisterPair::PC, new_addr);
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return Cycles::new(12);
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cpu.set_register_pair(RegisterPair::PC, addr);
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Cycles::new(12)
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} else {
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Cycles::new(8)
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}
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Cycles::new(8)
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}
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}
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}
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@ -408,40 +413,36 @@ impl Instruction {
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match registers {
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Registers::Byte(reg) => {
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// INC r[y] | Increment Register
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let mut flags: Flags = *cpu.flags();
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let cycles: Cycles;
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use InstrRegister::*;
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match reg {
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InstrRegister::B
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| InstrRegister::C
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| InstrRegister::D
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| InstrRegister::E
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| InstrRegister::H
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| InstrRegister::L
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| InstrRegister::A => {
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let mut flags: Flags = *cpu.flags();
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let cycles = match reg {
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B | C | D | E | H | L | A => {
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let reg = reg.to_register();
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let value = cpu.register(reg);
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cpu.set_register(reg, Self::inc_register(value, &mut flags));
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cycles = Cycles::new(4)
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Cycles::new(4)
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}
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InstrRegister::IndirectHL => {
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IndirectHL => {
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let addr = cpu.register_pair(RegisterPair::HL);
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let byte = Self::inc_register(cpu.read_byte(addr), &mut flags);
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cpu.write_byte(addr, byte);
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cycles = Cycles::new(12)
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Cycles::new(12)
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}
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}
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};
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cpu.set_flags(flags);
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cycles
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}
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Registers::Word(pair) => {
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// INC rp[p] | Increment Register Pair
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// Note: According to RGBDS, no flags are set here.
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use RegisterPair::*;
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match pair {
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RegisterPair::BC
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| RegisterPair::DE
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| RegisterPair::HL
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| RegisterPair::SP => {
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BC | DE | HL | SP => {
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let value = cpu.register_pair(pair);
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cpu.set_register_pair(pair, value + 1);
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}
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@ -451,45 +452,47 @@ impl Instruction {
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}
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}
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}
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Instruction::DEC(Registers::Word(pair)) => {
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// DEC rp[p] | Decrement Register Pair
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match pair {
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RegisterPair::BC | RegisterPair::DE | RegisterPair::HL | RegisterPair::SP => {
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let value = cpu.register_pair(pair);
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cpu.set_register_pair(pair, value - 1);
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}
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_ => unreachable!("There is no \"DEC {:?}\" instruction", pair),
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}
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Cycles::new(8)
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}
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Instruction::DEC(Registers::Byte(reg)) => {
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// DEC r[y] | Decrement Register
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let mut flags: Flags = *cpu.flags();
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let cycles: Cycles;
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Instruction::DEC(registers) => {
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match registers {
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Registers::Byte(reg) => {
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// DEC r[y] | Decrement Register
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use InstrRegister::*;
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match reg {
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InstrRegister::B
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| InstrRegister::C
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| InstrRegister::D
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| InstrRegister::E
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| InstrRegister::H
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| InstrRegister::L
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| InstrRegister::A => {
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let reg = reg.to_register();
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let mut flags: Flags = *cpu.flags();
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let value = cpu.register(reg);
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cpu.set_register(reg, Self::dec_register(value, &mut flags));
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cycles = Cycles::new(4);
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let cycles = match reg {
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B | C | D | E | H | L | A => {
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let reg = reg.to_register();
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let value = cpu.register(reg);
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cpu.set_register(reg, Self::dec_register(value, &mut flags));
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Cycles::new(4)
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}
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IndirectHL => {
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let addr = cpu.register_pair(RegisterPair::HL);
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let byte = cpu.read_byte(addr);
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cpu.write_byte(addr, Self::dec_register(byte, &mut flags));
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Cycles::new(12)
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}
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};
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cpu.set_flags(flags);
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cycles
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}
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InstrRegister::IndirectHL => {
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let addr = cpu.register_pair(RegisterPair::HL);
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let byte = cpu.read_byte(addr);
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cpu.write_byte(addr, Self::dec_register(byte, &mut flags));
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cycles = Cycles::new(12);
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Registers::Word(pair) => {
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// DEC rp[p] | Decrement Register Pair
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use RegisterPair::*;
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match pair {
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BC | DE | HL | SP => {
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let value = cpu.register_pair(pair);
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cpu.set_register_pair(pair, value - 1);
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}
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_ => unreachable!("There is no \"DEC {:?}\" instruction", pair),
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};
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Cycles::new(8)
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}
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}
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cpu.set_flags(flags);
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cycles
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}
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Instruction::RLCA => {
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// Rotate Register A left
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@ -710,33 +713,25 @@ impl Instruction {
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Instruction::AND(target) => match target {
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MATHTarget::Register(reg) => {
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// AND r[z] | Bitwise AND register r[z] and register A, store in register A
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use InstrRegister::*;
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let mut flags: Flags = *cpu.flags();
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let a_value = cpu.register(Register::A);
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let cycles: Cycles;
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let result;
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match reg {
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InstrRegister::B
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| InstrRegister::C
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| InstrRegister::D
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| InstrRegister::E
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| InstrRegister::H
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| InstrRegister::L
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| InstrRegister::A => {
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let (cycles, result) = match reg {
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B | C | D | E | H | L | A => {
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let value = cpu.register(reg.to_register());
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result = a_value & value;
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cycles = Cycles::new(4);
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(Cycles::new(4), a_value & value)
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}
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InstrRegister::IndirectHL => {
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IndirectHL => {
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let value = cpu.read_byte(cpu.register_pair(RegisterPair::HL));
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result = a_value & value;
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cycles = Cycles::new(8);
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(Cycles::new(8), a_value & value)
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}
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}
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};
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flags.update(result == 0, false, true, false);
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cpu.set_flags(flags);
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cpu.set_register(Register::A, result);
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cpu.set_flags(flags);
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cycles
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}
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MATHTarget::ImmediateByte(n) => {
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@ -745,8 +740,8 @@ impl Instruction {
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let result = cpu.register(Register::A) & n;
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flags.update(result == 0, false, true, false);
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cpu.set_flags(flags);
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cpu.set_register(Register::A, result);
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cpu.set_flags(flags);
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Cycles::new(8)
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}
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_ => unreachable!("There is no \"AND {:?}\" instruction", target),
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@ -842,22 +837,18 @@ impl Instruction {
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Instruction::CP(target) => match target {
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MATHTarget::Register(reg) => {
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// CP r[z] | Same behaviour as SUB, except the result is not stored.
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use InstrRegister::*;
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let mut flags: Flags = *cpu.flags();
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let a_value = cpu.register(Register::A);
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let cycles = match reg {
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InstrRegister::B
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| InstrRegister::C
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| InstrRegister::D
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| InstrRegister::E
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| InstrRegister::H
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| InstrRegister::L
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| InstrRegister::A => {
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B | C | D | E | H | L | A => {
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let value = cpu.register(reg.to_register());
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let _ = Self::sub_u8s(a_value, value, &mut flags);
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Cycles::new(4)
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}
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InstrRegister::IndirectHL => {
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IndirectHL => {
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let value = cpu.read_byte(cpu.register_pair(RegisterPair::HL));
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let _ = Self::sub_u8s(a_value, value, &mut flags);
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Cycles::new(8)
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@ -952,7 +943,9 @@ impl Instruction {
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Instruction::JP(cond, target) => match target {
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JPTarget::RegisterPair(RegisterPair::HL) => {
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// JP HL | Load register pair HL into program counter
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cpu.set_register_pair(RegisterPair::PC, cpu.register_pair(RegisterPair::HL));
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let addr = cpu.register_pair(RegisterPair::HL);
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cpu.set_register_pair(RegisterPair::PC, addr);
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Cycles::new(4)
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}
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JPTarget::ImmediateWord(nn) => {
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@ -964,30 +957,34 @@ impl Instruction {
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JumpCondition::NotZero => {
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if !flags.z() {
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cpu.set_register_pair(RegisterPair::PC, nn);
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return Cycles::new(16);
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Cycles::new(16)
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} else {
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Cycles::new(12)
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}
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Cycles::new(12)
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}
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JumpCondition::Zero => {
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if flags.z() {
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cpu.set_register_pair(RegisterPair::PC, nn);
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return Cycles::new(16);
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Cycles::new(16)
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} else {
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Cycles::new(12)
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}
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Cycles::new(12)
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}
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JumpCondition::NotCarry => {
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if !flags.c() {
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cpu.set_register_pair(RegisterPair::PC, nn);
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return Cycles::new(16);
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Cycles::new(16)
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} else {
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Cycles::new(12)
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}
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Cycles::new(12)
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}
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JumpCondition::Carry => {
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if flags.c() {
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cpu.set_register_pair(RegisterPair::PC, nn);
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return Cycles::new(16);
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Cycles::new(16)
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} else {
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Cycles::new(12)
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}
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Cycles::new(12)
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}
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JumpCondition::Always => {
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cpu.set_register_pair(RegisterPair::PC, nn);
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@ -1056,8 +1053,10 @@ impl Instruction {
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}
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Instruction::PUSH(pair) => {
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// PUSH rp2[p] | Push register pair onto the stack
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use RegisterPair::*;
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match pair {
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RegisterPair::BC | RegisterPair::DE | RegisterPair::HL | RegisterPair::AF => {
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BC | DE | HL | AF => {
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let value = cpu.register_pair(pair);
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Self::push(cpu, value);
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}
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@ -1524,12 +1523,12 @@ impl Instruction {
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(high as u16) << 8 | low as u16
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}
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fn dec_register(reg: u8, flags: &mut Flags) -> u8 {
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Self::sub_u8s_no_carry(reg, 1, flags)
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fn dec_register(byte: u8, flags: &mut Flags) -> u8 {
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Self::sub_u8s_no_carry(byte, 1, flags)
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}
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fn inc_register(reg: u8, flags: &mut Flags) -> u8 {
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Self::add_u8s_no_carry(reg, 1, flags)
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fn inc_register(byte: u8, flags: &mut Flags) -> u8 {
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Self::add_u8s_no_carry(byte, 1, flags)
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}
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fn sub_u8s_no_carry(left: u8, right: u8, flags: &mut Flags) -> u8 {
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