Commit Graph

66 Commits

Author SHA1 Message Date
Rekai Nyangadzayi Musuka 2b05571c49 chore: rename Cycles newtype to Cycle 2021-03-27 12:10:18 -05:00
Rekai Nyangadzayi Musuka bce14348f8 feat: enable halt and rework timer registers 2021-03-27 11:56:47 -05:00
Rekai Nyangadzayi Musuka 15781b3d5a fix(instructions): correct the flags being set in ADD HL, r16 2021-03-26 20:19:48 -05:00
Rekai Nyangadzayi Musuka a82e3d3372 feat: implement HALT behaviour
note: while the logic is there, the instruction currently does not do
anything because we don't halde it in Cpu::step(). The code that does is
currently commented out and there should be some underlying bugs still
present. Nevertheless it is a good start
2021-03-23 23:05:27 -05:00
Rekai Nyangadzayi Musuka e5fb07c4d1 chore: refactor parts of instruction.rs 2021-03-23 20:22:11 -05:00
Rekai Nyangadzayi Musuka 501d93c37b chore: clean up code in one instruction 2021-03-23 18:21:59 -05:00
Rekai Nyangadzayi Musuka 1b7d778c1d chore: clean up some instruction code 2021-03-23 02:11:40 -05:00
Rekai Nyangadzayi Musuka 342e6616ac chore: improve unreachable! and panic! error messages 2021-03-22 22:33:56 -05:00
Rekai Nyangadzayi Musuka 2813b762dd chore: replace select unreachable! macros with todo! and unreachable! 2021-03-22 21:52:28 -05:00
Rekai Nyangadzayi Musuka 9301a36682 chore: remove all unwraps from the project 2021-03-22 21:48:12 -05:00
Rekai Nyangadzayi Musuka d7d9fd857f fix: squash bugs in cpu intrucion implementation 2021-03-21 21:16:23 -05:00
Rekai Nyangadzayi Musuka dc45688e4f feat: implement timers 2021-03-21 03:03:03 -05:00
Rekai Nyangadzayi Musuka d76b3b6101 chore: make Cycles::new a const fn 2021-03-20 19:55:39 -05:00
Rekai Nyangadzayi Musuka 2401cf7190 chore: implement default for cycles 2021-03-20 19:55:02 -05:00
Rekai Nyangadzayi Musuka 558f9e7c72 feat: implement cpu interrupts 2021-03-18 21:07:19 -05:00
Rekai Nyangadzayi Musuka 8c25e6f976 chore: fix spelling mistake 2021-03-16 02:31:07 -05:00
Rekai Nyangadzayi Musuka 19f642eafe chore: make clippy happy 2021-03-16 01:05:13 -05:00
Rekai Nyangadzayi Musuka 3b5d94adfc fix: reimplement flags register to be a bitfield 2021-03-15 23:35:20 -05:00
Rekai Nyangadzayi Musuka d78a50fefc chore: fix tests and simplify CI build 2021-01-27 22:17:01 -06:00
Rekai Nyangadzayi Musuka 96bfc43312 chore: fix spelling errors 2021-01-19 22:44:48 -06:00
Rekai Nyangadzayi Musuka 842e670807 fix: replace MathTarget::HL and ::SP with already-existing enums 2021-01-19 02:05:04 -06:00
Rekai Nyangadzayi Musuka 9143286e9c feat: implement more operator overrides for Cycles 2021-01-19 00:29:04 -06:00
Rekai Nyangadzayi Musuka 9b4c95ce4c feat: reimplement cycles newtype 2021-01-18 22:54:38 -06:00
Rekai Nyangadzayi Musuka 207bcfea30 chore: improve debug logs 2021-01-18 02:47:41 -06:00
Rekai Nyangadzayi Musuka 49a45d48cb fix: improve appearance of debug logs 2021-01-18 02:29:35 -06:00
Rekai Nyangadzayi Musuka 9203b61533 fix: implement 0xff41 and fix CALL instruciton 2021-01-18 02:22:45 -06:00
Rekai Nyangadzayi Musuka 386a780a6f fix: call opcode now pushes correct address onto stack 2021-01-17 22:12:00 -06:00
Rekai Nyangadzayi Musuka c0b8b8bda2 feat: implement more registers 2021-01-17 21:13:59 -06:00
Rekai Nyangadzayi Musuka 072c5f1b70 fix: squash bug in 64 LD instructions 2021-01-17 17:31:45 -06:00
Rekai Nyangadzayi Musuka 911f0f9c86 feat: stub work ram 2021-01-03 00:28:07 -06:00
Rekai Nyangadzayi Musuka 2a234f4d14 feat: implement ability to boot straigt to cartridge 2020-12-23 19:39:37 -06:00
Rekai Nyangadzayi Musuka 4d2e0e33f2 feat: implement fetch, decode, execute loop 2020-12-23 03:25:16 -06:00
Rekai Nyangadzayi Musuka e540c86c7e chore: make InstrRegisterPair public 2020-12-23 01:58:55 -06:00
Rekai Nyangadzayi Musuka bf945c3f44 chore: make InstrRegister public to satisfy rust 2020-12-23 01:27:11 -06:00
Rekai Nyangadzayi Musuka db86d11085 chore: refactor LDTarget and InstrRegister 2020-12-23 01:24:06 -06:00
Rekai Nyangadzayi Musuka 2e1c97e5d7 chore: reorganize instructions.rs 2020-12-23 01:17:13 -06:00
Rekai Nyangadzayi Musuka 9cd4c4ea11 chore: remove duplicate Instruction::INC match 2020-12-23 01:11:03 -06:00
Rekai Nyangadzayi Musuka 5187cbed76 feat: implement remaining gb opcodes
As of now, the initial implementation of all GameBoy opcoes are
complete. There's most likely a lot of bugs in them, however the
foundtain has been placed.
2020-12-23 01:07:30 -06:00
Rekai Nyangadzayi Musuka 9be1d1508e feat: implement all opcodes in rot table 2020-12-23 00:24:29 -06:00
Rekai Nyangadzayi Musuka f9d7fe05df Merge branch 'master' of ssh://ssh.paoda.moe:31059/paoda/gb 2020-12-22 22:23:28 -06:00
Rekai Nyangadzayi Musuka 4bf9ccb98c chore: qol update 2020-12-22 22:23:09 -06:00
Rekai Nyangadzayi Musuka c876778da8 chore: replace 16-bit half carry implementation 2020-11-28 15:42:50 -06:00
Rekai Nyangadzayi Musuka 7edffb166d chore: Implement exec of RLC and RRC 2020-09-07 22:34:09 -05:00
Rekai Nyangadzayi Musuka a4b3da1939 chore: replace unimplemented!() with unreachable!() 2020-09-07 21:51:20 -05:00
Rekai Nyangadzayi Musuka cd6f242f56 feat: Implement exec of all unprefixed opcodes 2020-09-07 21:49:10 -05:00
Rekai Nyangadzayi Musuka eb90ac31e2 chore: Document prefixed opcode decoding 2020-09-07 21:22:26 -05:00
Rekai Nyangadzayi Musuka 7538f946d4 feat: Implement prefixed opcode decoding 2020-09-07 21:18:53 -05:00
Rekai Nyangadzayi Musuka a9510bed54 chore: Document instruction execution implementations 2020-09-07 20:57:31 -05:00
Rekai Nyangadzayi Musuka f193132c5e chore: Implement imm byte versions of alu opcodes 2020-09-07 20:50:33 -05:00
Rekai Nyangadzayi Musuka 70a959fa32 chore: Remove LHS MathTarget from ADC and SBC 2020-09-07 20:28:24 -05:00