160c8ca213
chore: add .drone.yml for CI integration
2021-01-27 21:12:38 -06:00
b5d3a2c675
feat: implement MBC1
2021-01-20 01:39:24 -06:00
96bfc43312
chore: fix spelling errors
2021-01-19 22:44:48 -06:00
842e670807
fix: replace MathTarget::HL and ::SP with already-existing enums
2021-01-19 02:05:04 -06:00
b70c398e14
feat: implement registers 0xFF01 and 0xFF02
2021-01-19 01:40:07 -06:00
68c9557c43
chore: improve code quality
2021-01-19 01:36:44 -06:00
1da01a318d
feat: emulator now sucessfully runs boot rom
2021-01-19 00:30:32 -06:00
9143286e9c
feat: implement more operator overrides for Cycles
2021-01-19 00:29:04 -06:00
9b4c95ce4c
feat: reimplement cycles newtype
2021-01-18 22:54:38 -06:00
2fc7ac3833
feat: add pixels-rs and winit as dependencies
2021-01-18 20:47:09 -06:00
207bcfea30
chore: improve debug logs
2021-01-18 02:47:41 -06:00
49a45d48cb
fix: improve appearance of debug logs
2021-01-18 02:29:35 -06:00
9203b61533
fix: implement 0xff41 and fix CALL instruciton
2021-01-18 02:22:45 -06:00
386a780a6f
fix: call opcode now pushes correct address onto stack
2021-01-17 22:12:00 -06:00
c0b8b8bda2
feat: implement more registers
2021-01-17 21:13:59 -06:00
70de3b9142
feat: stub 0xff40 and 0xff47
2021-01-17 19:25:53 -06:00
92218a227d
feat: implement 0xff24 sound register
2021-01-17 18:58:57 -06:00
251f4e8d6d
feat: implement several sound i/o registers
2021-01-17 17:33:12 -06:00
072c5f1b70
fix: squash bug in 64 LD instructions
2021-01-17 17:31:45 -06:00
834423fe18
feat: stub sound register 0xff26
2021-01-03 02:05:46 -06:00
1b53363095
feat: stub 0xff0f and 0xffff from interrupt
2021-01-03 01:38:31 -06:00
e693ad8a3c
feat: create timer struct and stub 0xff07
2021-01-03 01:21:19 -06:00
911f0f9c86
feat: stub work ram
2021-01-03 00:28:07 -06:00
8048495cbc
chore: move ppu vram from stack to heap
2021-01-02 23:58:49 -06:00
fb0772c671
chore: remove duplicate code
2021-01-02 22:49:25 -06:00
fe74f80ddf
chore: format code
2020-12-24 00:34:48 -06:00
26df683cff
chore: move vram buffer to PPU struct
2020-12-24 00:27:06 -06:00
677a584ba7
chore: stub vram, start work on ppu, fix set_register bug
2020-12-23 21:24:58 -06:00
2a234f4d14
feat: implement ability to boot straigt to cartridge
2020-12-23 19:39:37 -06:00
1502cc3ec2
chore: add debug information to bus.rs
2020-12-23 03:43:49 -06:00
4d2e0e33f2
feat: implement fetch, decode, execute loop
2020-12-23 03:25:16 -06:00
e540c86c7e
chore: make InstrRegisterPair public
2020-12-23 01:58:55 -06:00
bf945c3f44
chore: make InstrRegister public to satisfy rust
2020-12-23 01:27:11 -06:00
db86d11085
chore: refactor LDTarget and InstrRegister
2020-12-23 01:24:06 -06:00
2e1c97e5d7
chore: reorganize instructions.rs
2020-12-23 01:17:13 -06:00
9cd4c4ea11
chore: remove duplicate Instruction::INC match
2020-12-23 01:11:03 -06:00
5187cbed76
feat: implement remaining gb opcodes
...
As of now, the initial implementation of all GameBoy opcoes are
complete. There's most likely a lot of bugs in them, however the
foundtain has been placed.
2020-12-23 01:07:30 -06:00
9be1d1508e
feat: implement all opcodes in rot table
2020-12-23 00:24:29 -06:00
f9d7fe05df
Merge branch 'master' of ssh://ssh.paoda.moe:31059/paoda/gb
2020-12-22 22:23:28 -06:00
4bf9ccb98c
chore: qol update
2020-12-22 22:23:09 -06:00
c876778da8
chore: replace 16-bit half carry implementation
2020-11-28 15:42:50 -06:00
7edffb166d
chore: Implement exec of RLC and RRC
2020-09-07 22:34:09 -05:00
a4b3da1939
chore: replace unimplemented!() with unreachable!()
2020-09-07 21:51:20 -05:00
cd6f242f56
feat: Implement exec of all unprefixed opcodes
2020-09-07 21:49:10 -05:00
eb90ac31e2
chore: Document prefixed opcode decoding
2020-09-07 21:22:26 -05:00
7538f946d4
feat: Implement prefixed opcode decoding
2020-09-07 21:18:53 -05:00
a9510bed54
chore: Document instruction execution implementations
2020-09-07 20:57:31 -05:00
f193132c5e
chore: Implement imm byte versions of alu opcodes
2020-09-07 20:50:33 -05:00
70a959fa32
chore: Remove LHS MathTarget from ADC and SBC
2020-09-07 20:28:24 -05:00
e31d83deae
chore: Implement DI, EI, CALL & PUSH instructions
2020-09-07 20:19:10 -05:00
