Rekai Nyangadzayi Musuka
71ce3f43e0
chore: satisfy clippy
2021-09-20 04:15:05 -03:00
Rekai Nyangadzayi Musuka
5882678bc5
chore: inline some functions
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2021-09-20 01:34:41 -03:00
Rekai Nyangadzayi Musuka
bcd67cb317
chore: begin refactor of public api
2021-09-20 01:34:21 -03:00
Rekai Nyangadzayi Musuka
6087e3b20b
chore: remove Cycle struct and begin scheduler design
2021-09-12 04:56:34 -03:00
Rekai Nyangadzayi Musuka
01064bab69
chore(cpu): comment out blargg-specific code
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2021-08-22 01:49:01 -05:00
Rekai Nyangadzayi Musuka
6215eccb2f
chore(cpu): merge halted and state properties
2021-08-15 23:26:01 -05:00
Rekai Nyangadzayi Musuka
1b78b248a3
chore: minor edits to documentation
2021-08-14 17:51:09 -05:00
Rekai Nyangadzayi Musuka
5d6df46a2d
fix(cpu): reimplement instruction handling
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2021-08-14 17:23:45 -05:00
Rekai Nyangadzayi Musuka
7e65d82fef
chore(cpu): document fetch, decode, execute
2021-08-14 16:42:38 -05:00
Rekai Nyangadzayi Musuka
8c9567b610
chore(cpu): rename discriminants of ImeState enum
2021-08-14 16:42:15 -05:00
Rekai Nyangadzayi Musuka
8625bec059
feat: clock bus on instruction read-write
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Commit also includes general work towards passing mem-timings.
Note: while cpu_instrs.gb passes, instr_timing.gb and mem_timing.gb both
are stuck in infinite loops (Currently, it seems like a timing issue).
This is a major regression that hopefully shouldn't last for too long.
2021-08-14 00:10:51 -05:00
Rekai Nyangadzayi Musuka
7112cd15e3
chore(cpu): refactor SM83 implementation
...
continuous-integration/drone/push Build is passing
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Instruction::decode no longer requires mutable access to the CPU
2021-07-31 20:29:13 -05:00
Rekai Nyangadzayi Musuka
e43cac8041
fix(apu): don't spin if ringbuf is full
2021-07-28 16:23:31 -05:00
Rekai Nyangadzayi Musuka
903cfacad3
fix(apu): replace mpsc with spsc ringbuffer
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2021-07-28 02:01:04 -05:00
Rekai Nyangadzayi Musuka
9d0e099a97
chore: remove unnecessary derivations from structs
2021-07-28 00:09:07 -05:00
Rekai Nyangadzayi Musuka
c1430594cf
chore(apu): change access modifiers of some methods
2021-07-18 20:58:02 -05:00
Rekai Nyangadzayi Musuka
a1eadc0bc4
chore(apu): rename sound/snd to apu
continuous-integration/drone/push Build is passing
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2021-07-14 23:45:01 -05:00
Rekai Nyangadzayi Musuka
ea53f97312
chore(snd): refactor APU implementation
2021-07-14 23:34:00 -05:00
Rekai Nyangadzayi Musuka
08bd33b4d4
fix(snd): replace Audio Sync solution with a faster one
continuous-integration/drone/push Build is passing
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2021-07-14 22:35:37 -05:00
Rekai Nyangadzayi Musuka
2b5926e533
chore(snd): Make AudioReceiver and AudioSender structs generic
2021-07-14 22:34:57 -05:00
Rekai Nyangadzayi Musuka
1e27875dc3
fix(cpu): fix timing issue involving when the bus is clocked
2021-07-14 21:15:52 -05:00
Rekai Nyangadzayi Musuka
ab99e24f64
chore: modify commented out debug statement
2021-07-14 21:10:44 -05:00
Rekai Nyangadzayi Musuka
afdfcfce2c
chore: add _debug_log function to cpu.rs
2021-07-12 21:08:38 -05:00
Rekai Nyangadzayi Musuka
44b605970f
chore(snd): rename some structs
2021-07-12 10:03:45 -05:00
Rekai Nyangadzayi Musuka
b13444c885
feat(snd): simplify audio buffer
...
continuous-integration/drone/push Build is passing
Details
The audio buffer now is held by crossbeam. The developers of said
library could write a batter queue than I could anyday
2021-07-11 23:48:16 -05:00
Rekai Nyangadzayi Musuka
3b772c7c49
feat(snd): synchronize audio with rest of system
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In it's current form I think this is actually rather inefficient. It's
also not very accurate since I throw away a lot of samples for no real
good reason. More improvements to thiss will be coming henceforth
2021-07-11 23:22:17 -05:00
Rekai Nyangadzayi Musuka
ce630baa5d
feat(snd): implement audio playback using rodio
continuous-integration/drone/push Build is failing
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2021-07-09 01:25:52 -05:00
Rekai Nyangadzayi Musuka
fc4a898177
chore: reorganize select parts of codebase
2021-06-27 20:28:29 -05:00
Rekai Nyangadzayi Musuka
50efe12aec
chore: change how bus components are clocked
2021-06-09 19:41:10 -05:00
Rekai Nyangadzayi Musuka
e8e6c41dbe
fix(dma): initial version of dma transfer now works
2021-06-06 23:57:54 -05:00
Rekai Nyangadzayi Musuka
ef4e54aba6
chore: restrict what should be pub or not
2021-06-06 20:47:11 -05:00
Rekai Nyangadzayi Musuka
878edd4082
chore: replace pub with pub(crate) when possible
2021-06-06 19:14:28 -05:00
Rekai Nyangadzayi Musuka
b7b213b6b9
chore(bus): implement read/write blocks when dma is active
2021-06-05 20:53:35 -05:00
Rekai Nyangadzayi Musuka
b1bf6c5868
feat: integrate eui and pixels-rs for debug info
2021-06-02 01:50:35 -05:00
Rekai Nyangadzayi Musuka
4ab59007f9
chore(cpu): disable logging by default
2021-04-23 23:31:16 -05:00
Rekai Nyangadzayi Musuka
b43c8ac7c9
feat(cartridge): grab title from the ROM
2021-04-14 01:21:45 -05:00
Rekai Nyangadzayi Musuka
cf3b79f0dc
chore(cpu): move RST behaviour to a method
2021-04-07 23:05:22 -05:00
Rekai Nyangadzayi Musuka
067ed03de3
feat: comply with test 03 of blargg's cpu_instrs test rom
2021-04-07 20:12:05 -05:00
Rekai Nyangadzayi Musuka
9b77d6c6c3
fix(cpu): ensure that timer, lcd and sound runs regardless of HALT
2021-04-05 01:20:18 -05:00
Rekai Nyangadzayi Musuka
9d2fbd2427
chore: remove unecessary print statements
2021-04-05 01:20:03 -05:00
Rekai Nyangadzayi Musuka
748c32c446
fix(cpu): use enums only of maintaining IME register state
2021-04-05 01:10:03 -05:00
Rekai Nyangadzayi Musuka
77c7c610d0
chore(cpu): rename ImeSet to ImeEnabled
2021-04-05 00:53:46 -05:00
Rekai Nyangadzayi Musuka
a15a6a25b6
feat(cpu): properly implement EI instruction
2021-04-05 00:52:12 -05:00
Rekai Nyangadzayi Musuka
4dd7a0d9ce
chore: fix several clippy warnings
2021-04-04 01:19:39 -05:00
Rekai Nyangadzayi Musuka
25e44f3e49
chore: fix condition when logs are printed
2021-03-27 15:07:17 -05:00
Rekai Nyangadzayi Musuka
2b05571c49
chore: rename Cycles newtype to Cycle
2021-03-27 12:10:18 -05:00
Rekai Nyangadzayi Musuka
bce14348f8
feat: enable halt and rework timer registers
2021-03-27 11:56:47 -05:00
Rekai Nyangadzayi Musuka
2bf877d1ec
fix(cpu): Ensure mask the high bits of the flag register
...
There was a bug where POP AF returned 0x1301. In this example, the A
register would be set to 0x13, and the Flag register woud be set to
0x01, which is an invalid state considering only bits 4 -> 7 of the flag
register are used. This commit masks the flag register with & 0xF0
whenever it is read or written to so that we can ensure that only the
high bits can ever be potentially set
2021-03-26 20:25:30 -05:00
Rekai Nyangadzayi Musuka
a82e3d3372
feat: implement HALT behaviour
...
note: while the logic is there, the instruction currently does not do
anything because we don't halde it in Cpu::step(). The code that does is
currently commented out and there should be some underlying bugs still
present. Nevertheless it is a good start
2021-03-23 23:05:27 -05:00
Rekai Nyangadzayi Musuka
6f11640f24
chore: replace CALL instruction with RST in interrupt handler
2021-03-23 02:11:06 -05:00
