chore(bus): implement read/write blocks when dma is active
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2e42513d71
commit
b7b213b6b9
15
src/bus.rs
15
src/bus.rs
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@ -3,7 +3,7 @@ use super::high_ram::HighRam;
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use super::instruction::Cycle;
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use super::interrupt::{Interrupt, InterruptFlag};
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use super::joypad::Joypad;
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use super::ppu::Ppu;
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use super::ppu::{Ppu, PpuMode};
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use super::serial::Serial;
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use super::sound::Sound;
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use super::timer::Timer;
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@ -133,9 +133,13 @@ impl Bus {
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_ => unreachable!("{:#06X} was incorrectly handled by ECHO RAM", addr),
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}
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}
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0xFE00..=0xFE9F if self.ppu.dma.is_active() => 0xFF,
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0xFE00..=0xFE9F => {
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// Sprite Attribute Table
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self.ppu.oam.read_byte(addr)
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match self.ppu.stat.mode() {
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PpuMode::HBlank | PpuMode::VBlank => self.ppu.oam.read_byte(addr),
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PpuMode::OamScan | PpuMode::Drawing => 0xFF,
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}
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}
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0xFEA0..=0xFEFF => {
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// eprintln!("Read from {:#06X}, which is prohibited", addr);
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@ -240,9 +244,14 @@ impl Bus {
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_ => unreachable!("{:#06X} was incorrectly handled by ECHO RAM", addr),
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}
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}
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0xFE00..=0xFE9F if self.ppu.dma.is_active() => {}
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0xFE00..=0xFE9F => {
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// Sprite Attribute Table
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self.ppu.oam.write_byte(addr, byte);
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match self.ppu.stat.mode() {
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PpuMode::HBlank | PpuMode::VBlank => self.ppu.oam.write_byte(addr, byte),
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PpuMode::Drawing | PpuMode::OamScan => {}
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}
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}
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0xFEA0..=0xFEFF => {
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// eprintln!("Wrote {:#04X} to {:#06X}, which is prohibited", byte, addr);
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@ -96,6 +96,8 @@ impl Cpu {
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// self.log_state(handle).unwrap();
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// }
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self.handle_interrupts();
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let cycles = match self.halted() {
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Some(state) => {
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use HaltState::*;
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@ -119,7 +121,7 @@ impl Cpu {
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};
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self.bus.step(cycles);
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self.handle_interrupts();
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self.bus.step_dma(cycles);
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cycles
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}
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@ -4,10 +4,10 @@ use crate::GB_WIDTH;
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use dma::DmaProcess;
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use std::collections::VecDeque;
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use std::convert::TryInto;
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use self::types::{
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pub use types::PpuMode;
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use types::{
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BackgroundPalette, GrayShade, LCDControl, LCDStatus, ObjectFlags, ObjectPalette,
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ObjectPaletteId, ObjectSize, Pixels, PpuMode, RenderPriority, TileDataAddress,
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ObjectPaletteId, ObjectSize, Pixels, RenderPriority, TileDataAddress,
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};
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pub(crate) mod dma;
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@ -188,7 +188,7 @@ impl Ppu {
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}
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fn scan_oam(&mut self) {
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if self.scan_state.mode() == OamScanMode::Scan {
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if self.scan_state.mode() == OamScanMode::Scan && self.dma.is_active() {
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if !self.window_stat.coincidence() && self.scan_state.count() == 0 {
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// Determine whether we should draw the window next frame
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self.window_stat
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@ -45,6 +45,10 @@ impl DmaProcess {
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}
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}
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pub(crate) fn is_active(&self) -> bool {
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self.state == DmaState::Transferring
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}
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fn reset(&mut self) {
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self.cycle = Cycle::new(0);
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self.state = DmaState::Disabled;
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@ -84,14 +88,6 @@ impl Default for DmaControl {
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}
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impl DmaControl {
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fn src(&self) -> Option<&Range<u16>> {
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self.src.as_ref()
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}
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fn dest(&self) -> &Range<u16> {
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&self.dest
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}
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pub fn update(&mut self, byte: u8, state: &mut DmaState) {
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let left = (byte as u16) << 8 | 0x0000;
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let right = (byte as u16) << 8 | 0x009F;
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@ -116,12 +112,12 @@ mod tests {
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let mut dma_ctrl: DmaControl = Default::default();
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let mut state = DmaState::Disabled;
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assert_eq!(dma_ctrl.src(), None);
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assert_eq!(*dma_ctrl.dest(), 0xFE00..0xFE9F);
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assert_eq!(dma_ctrl.src, None);
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assert_eq!(dma_ctrl.dest, 0xFE00..0xFE9F);
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dma_ctrl.update(0xAB, &mut state);
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assert_eq!(dma_ctrl.src(), Some(0xAB00..0xAB9F).as_ref());
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assert_eq!(*dma_ctrl.dest(), 0xFE00..0xFE9F);
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assert_eq!(dma_ctrl.src, Some(0xAB00..0xAB9F));
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assert_eq!(dma_ctrl.dest, 0xFE00..0xFE9F);
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}
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#[test]
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@ -131,7 +127,7 @@ mod tests {
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bus.dma.ctrl.update(0xAB, &mut bus.dma.state);
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assert_eq!(bus.dma.ctrl.src(), Some(0xAB00..0xAB9F).as_ref());
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assert_eq!(bus.dma.ctrl.src, Some(0xAB00..0xAB9F));
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assert_eq!(bus.dma.state, DmaState::Pending);
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}
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}
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