chore(bus): implement read/write blocks when dma is active

src/cpu.rs

@@ -96,6 +96,8 @@ impl Cpu {
         //     self.log_state(handle).unwrap();
         // }
 
+        self.handle_interrupts();
+
         let cycles = match self.halted() {
             Some(state) => {
                 use HaltState::*;
@@ -119,7 +121,7 @@ impl Cpu {
         };
 
         self.bus.step(cycles);
-        self.handle_interrupts();
+        self.bus.step_dma(cycles);
 
         cycles
     }