From b7b213b6b93ceb5d98db4db285403e65b5f8b1b3 Mon Sep 17 00:00:00 2001
From: Rekai Musuka <rekai@musuka.dev>
Date: Sat, 5 Jun 2021 20:53:35 -0500
Subject: [PATCH] chore(bus): implement read/write blocks when dma is active

---
 src/bus.rs     | 15 ++++++++++++---
 src/cpu.rs     |  4 +++-
 src/ppu.rs     |  8 ++++----
 src/ppu/dma.rs | 22 +++++++++-------------
 4 files changed, 28 insertions(+), 21 deletions(-)

diff --git a/src/bus.rs b/src/bus.rs
index e92995c..5d00f3a 100644
--- a/src/bus.rs
+++ b/src/bus.rs
@@ -3,7 +3,7 @@ use super::high_ram::HighRam;
 use super::instruction::Cycle;
 use super::interrupt::{Interrupt, InterruptFlag};
 use super::joypad::Joypad;
-use super::ppu::Ppu;
+use super::ppu::{Ppu, PpuMode};
 use super::serial::Serial;
 use super::sound::Sound;
 use super::timer::Timer;
@@ -133,9 +133,13 @@ impl Bus {
                     _ => unreachable!("{:#06X} was incorrectly handled by ECHO RAM", addr),
                 }
             }
+            0xFE00..=0xFE9F if self.ppu.dma.is_active() => 0xFF,
             0xFE00..=0xFE9F => {
                 // Sprite Attribute Table
-                self.ppu.oam.read_byte(addr)
+                match self.ppu.stat.mode() {
+                    PpuMode::HBlank | PpuMode::VBlank => self.ppu.oam.read_byte(addr),
+                    PpuMode::OamScan | PpuMode::Drawing => 0xFF,
+                }
             }
             0xFEA0..=0xFEFF => {
                 // eprintln!("Read from {:#06X}, which is prohibited", addr);
@@ -240,9 +244,14 @@ impl Bus {
                     _ => unreachable!("{:#06X} was incorrectly handled by ECHO RAM", addr),
                 }
             }
+
+            0xFE00..=0xFE9F if self.ppu.dma.is_active() => {}
             0xFE00..=0xFE9F => {
                 // Sprite Attribute Table
-                self.ppu.oam.write_byte(addr, byte);
+                match self.ppu.stat.mode() {
+                    PpuMode::HBlank | PpuMode::VBlank => self.ppu.oam.write_byte(addr, byte),
+                    PpuMode::Drawing | PpuMode::OamScan => {}
+                }
             }
             0xFEA0..=0xFEFF => {
                 // eprintln!("Wrote {:#04X} to {:#06X}, which is prohibited", byte, addr);
diff --git a/src/cpu.rs b/src/cpu.rs
index 4a628ff..afce18f 100644
--- a/src/cpu.rs
+++ b/src/cpu.rs
@@ -96,6 +96,8 @@ impl Cpu {
         //     self.log_state(handle).unwrap();
         // }
 
+        self.handle_interrupts();
+
         let cycles = match self.halted() {
             Some(state) => {
                 use HaltState::*;
@@ -119,7 +121,7 @@ impl Cpu {
         };
 
         self.bus.step(cycles);
-        self.handle_interrupts();
+        self.bus.step_dma(cycles);
 
         cycles
     }
diff --git a/src/ppu.rs b/src/ppu.rs
index 22f407c..6e7934a 100644
--- a/src/ppu.rs
+++ b/src/ppu.rs
@@ -4,10 +4,10 @@ use crate::GB_WIDTH;
 use dma::DmaProcess;
 use std::collections::VecDeque;
 use std::convert::TryInto;
-
-use self::types::{
+pub use types::PpuMode;
+use types::{
     BackgroundPalette, GrayShade, LCDControl, LCDStatus, ObjectFlags, ObjectPalette,
-    ObjectPaletteId, ObjectSize, Pixels, PpuMode, RenderPriority, TileDataAddress,
+    ObjectPaletteId, ObjectSize, Pixels, RenderPriority, TileDataAddress,
 };
 
 pub(crate) mod dma;
@@ -188,7 +188,7 @@ impl Ppu {
     }
 
     fn scan_oam(&mut self) {
-        if self.scan_state.mode() == OamScanMode::Scan {
+        if self.scan_state.mode() == OamScanMode::Scan && self.dma.is_active() {
             if !self.window_stat.coincidence() && self.scan_state.count() == 0 {
                 // Determine whether we should draw the window next frame
                 self.window_stat
diff --git a/src/ppu/dma.rs b/src/ppu/dma.rs
index 7b7475f..c119c9c 100644
--- a/src/ppu/dma.rs
+++ b/src/ppu/dma.rs
@@ -45,6 +45,10 @@ impl DmaProcess {
         }
     }
 
+    pub(crate) fn is_active(&self) -> bool {
+        self.state == DmaState::Transferring
+    }
+
     fn reset(&mut self) {
         self.cycle = Cycle::new(0);
         self.state = DmaState::Disabled;
@@ -84,14 +88,6 @@ impl Default for DmaControl {
 }
 
 impl DmaControl {
-    fn src(&self) -> Option<&Range<u16>> {
-        self.src.as_ref()
-    }
-
-    fn dest(&self) -> &Range<u16> {
-        &self.dest
-    }
-
     pub fn update(&mut self, byte: u8, state: &mut DmaState) {
         let left = (byte as u16) << 8 | 0x0000;
         let right = (byte as u16) << 8 | 0x009F;
@@ -116,12 +112,12 @@ mod tests {
         let mut dma_ctrl: DmaControl = Default::default();
         let mut state = DmaState::Disabled;
 
-        assert_eq!(dma_ctrl.src(), None);
-        assert_eq!(*dma_ctrl.dest(), 0xFE00..0xFE9F);
+        assert_eq!(dma_ctrl.src, None);
+        assert_eq!(dma_ctrl.dest, 0xFE00..0xFE9F);
 
         dma_ctrl.update(0xAB, &mut state);
-        assert_eq!(dma_ctrl.src(), Some(0xAB00..0xAB9F).as_ref());
-        assert_eq!(*dma_ctrl.dest(), 0xFE00..0xFE9F);
+        assert_eq!(dma_ctrl.src, Some(0xAB00..0xAB9F));
+        assert_eq!(dma_ctrl.dest, 0xFE00..0xFE9F);
     }
 
     #[test]
@@ -131,7 +127,7 @@ mod tests {
 
         bus.dma.ctrl.update(0xAB, &mut bus.dma.state);
 
-        assert_eq!(bus.dma.ctrl.src(), Some(0xAB00..0xAB9F).as_ref());
+        assert_eq!(bus.dma.ctrl.src, Some(0xAB00..0xAB9F));
         assert_eq!(bus.dma.state, DmaState::Pending);
     }
 }