fix: make Bank.spsrIndex public

- impl behaviour of running v5te instrs on v4t cpu
- impl undefined instruction exception handler
- panic on what I think are still unimplemented v5te opcodes

src/arm.zig

@@ -4,34 +4,38 @@ const Architecture = enum { v4t, v5te };
 const Interpreter = @import("lib.zig").Interpreter;
 const Bus = @import("lib.zig").Bus;
 const Scheduler = @import("lib.zig").Scheduler;
+const Coprocessor = @import("lib.zig").Coprocessor;
 
 const Bitfield = @import("bitfield").Bitfield;
 const Bit = @import("bitfield").Bit;
 
-const condition_lut = [_]u16{
-    0xF0F0, // EQ - Equal
-    0x0F0F, // NE - Not Equal
-    0xCCCC, // CS - Unsigned higher or same
-    0x3333, // CC - Unsigned lower
-    0xFF00, // MI - Negative
-    0x00FF, // PL - Positive or Zero
-    0xAAAA, // VS - Overflow
-    0x5555, // VC - No Overflow
-    0x0C0C, // HI - unsigned hierh
-    0xF3F3, // LS - unsigned lower or same
-    0xAA55, // GE - greater or equal
-    0x55AA, // LT - less than
-    0x0A05, // GT - greater than
-    0xF5FA, // LE - less than or equal
-    0xFFFF, // AL - always
-    0x0000, // NV - never
-};
+fn condition_lut(comptime isa: Architecture) [16]u16 {
+    return [_]u16{
+        0xF0F0, // EQ - Equal
+        0x0F0F, // NE - Not Equal
+        0xCCCC, // CS - Unsigned higher or same
+        0x3333, // CC - Unsigned lower
+        0xFF00, // MI - Negative
+        0x00FF, // PL - Positive or Zero
+        0xAAAA, // VS - Overflow
+        0x5555, // VC - No Overflow
+        0x0C0C, // HI - unsigned hierh
+        0xF3F3, // LS - unsigned lower or same
+        0xAA55, // GE - greater or equal
+        0x55AA, // LT - less than
+        0x0A05, // GT - greater than
+        0xF5FA, // LE - less than or equal
+        0xFFFF, // AL - always
+        if (isa == .v4t) 0x0000 else 0xFFFF, // NV - never
+    };
+}
 
-pub fn Arm32(comptime arch: Architecture) type {
-    const is_v5te = arch == .v5te;
+pub fn Arm32(comptime isa: Architecture) type {
+    const is_v5te = isa == .v5te;
 
     return struct {
         const Self = @This();
+        pub const arch = isa;
 
         r: [16]u32 = [_]u32{0x00} ** 16,
         pipe: Pipeline = Pipeline.init(),
@@ -45,13 +49,14 @@ pub fn Arm32(comptime arch: Architecture) type {
         // The following will be `void` on.v4t but exist on v5te
         itcm: if (is_v5te) Itcm else void,
         dtcm: if (is_v5te) Dtcm else void,
+        cp15: if (is_v5te) Coprocessor else void,
 
-        const arm = switch (arch) {
+        const arm = switch (isa) {
             .v4t => @import("arm/v4t.zig").arm,
             .v5te => @import("arm/v5te.zig").arm,
         };
 
-        const thumb = switch (arch) {
+        const thumb = switch (isa) {
             .v4t => @import("arm/v4t.zig").thumb,
             .v5te => @import("arm/v5te.zig").thumb,
         };
@@ -137,7 +142,7 @@ pub fn Arm32(comptime arch: Architecture) type {
                 return (idx * 2) + if (kind == .R14) @as(usize, 1) else 0;
             }
 
-            inline fn spsrIdx(mode: Mode) usize {
+            pub inline fn spsrIdx(mode: Mode) usize {
                 return switch (mode) {
                     .Supervisor => 0,
                     .Abort => 1,
@@ -153,73 +158,85 @@ pub fn Arm32(comptime arch: Architecture) type {
             }
         };
 
-        pub fn init(scheduler: Scheduler, bus: Bus) Self {
-            return .{
-                .sched = scheduler,
-                .bus = bus,
-                .cpsr = .{ .raw = 0x0000_001F },
-                .spsr = .{ .raw = 0x0000_0000 },
+        // FIXME: Is this a hack or idiomatic?
+        // See https://github.com/ziglang/zig/blob/1a0e6bcdb140c844384d62b78a7f4247753f9ffd/lib/std/atomic/Atomic.zig#L156-L176
+        pub usingnamespace if (is_v5te) struct {
+            // FIXME: this is pretty NDS9 specific lol
+            pub fn init(scheduler: Scheduler, bus: Bus, cp15: Coprocessor) Self {
+                return .{
+                    .sched = scheduler,
+                    .bus = bus,
+                    .cpsr = .{ .raw = 0x0000_001F },
+                    .spsr = .{ .raw = 0x0000_0000 },
 
-                .dtcm = if (is_v5te) .{} else {},
-                .itcm = if (is_v5te) .{} else {},
-            };
-        }
+                    .cp15 = cp15,
+                    .dtcm = .{},
+                    .itcm = .{},
+                };
+            }
+
+            // FIXME: Resetting disables logging (if enabled)
+            pub fn reset(self: *Self) void {
+                self.* = .{
+                    .sched = self.sched,
+                    .bus = self.bus,
+                    .cpsr = .{ .raw = 0x0000_001F },
+                    .spsr = .{ .raw = 0x0000_0000 },
+
+                    .dtcm = .{},
+                    .itcm = .{},
+                    .cp15 = self.cp15,
+                };
+            }
+        } else struct {
+            pub fn init(scheduler: Scheduler, bus: Bus) Self {
+                return .{
+                    .sched = scheduler,
+                    .bus = bus,
+                    .cpsr = .{ .raw = 0x0000_001F },
+                    .spsr = .{ .raw = 0x0000_0000 },
+
+                    .cp15 = {},
+                    .dtcm = {},
+                    .itcm = {},
+                };
+            }
+
+            // FIXME: Resetting disables logging (if enabled)
+            pub fn reset(self: *Self) void {
+                self.* = .{
+                    .sched = self.sched,
+                    .bus = self.bus,
+                    .cpsr = .{ .raw = 0x0000_001F },
+                    .spsr = .{ .raw = 0x0000_0000 },
+
+                    .dtcm = {},
+                    .itcm = {},
+                    .cp15 = {},
+                };
+            }
+        };
 
         // CPU needs it's own read/write fns due to ICTM and DCTM present in v5te
         // I considered implementing Bus.cpu_read and Bus.cpu_write but ended up considering that a bit too leaky
         pub fn read(self: *Self, comptime T: type, address: u32) T {
-            const readInt = std.mem.readIntSliceLittle;
-
             if (is_v5te) {
-                const itcm_base: u32 = self.itcm.base_address;
-                const itcm_size = self.itcm.buf.len;
-                const dtcm_base: u32 = self.dtcm.base_address;
-                const dtcm_size = self.dtcm.buf.len;
-
-                // FIXME: verify correctness + can this be faster?
-                if (itcm_base < address and address < itcm_base + itcm_size)
-                    return readInt(T, self.itcm.buf[address & 0x0000_7FFF ..][0..@sizeOf(T)]);
-
-                if (dtcm_base < address and address < dtcm_base + dtcm_size)
-                    return readInt(T, self.itcm.buf[address & 0x0000_3FFF ..][0..@sizeOf(T)]);
+                if (self.itcm.read(T, address)) |val| return val;
+                if (self.dtcm.read(T, address)) |val| return val;
             }
 
             return self.bus.read(T, address);
         }
 
         pub fn write(self: *Self, comptime T: type, address: u32, value: T) void {
-            const writeInt = std.mem.writeIntSliceLittle;
-
             if (is_v5te) {
-                const itcm_base: u32 = self.itcm.base_address;
-                const itcm_size = self.itcm.buf.len;
-                const dtcm_base: u32 = self.dtcm.base_address;
-                const dtcm_size = self.dtcm.buf.len;
-
-                // FIXME: verify correctness + can this be faster?
-                if (itcm_base < address and address < itcm_base + itcm_size)
-                    return writeInt(T, self.itcm.buf[address & 0x0000_7FFF ..][0..@sizeOf(T)], value);
-
-                if (dtcm_base < address and address < dtcm_base + dtcm_size)
-                    return writeInt(T, self.itcm.buf[address & 0x0000_3FFF ..][0..@sizeOf(T)], value);
+                if (self.itcm.write(T, address, value)) return;
+                if (self.dtcm.write(T, address, value)) return;
             }
 
             return self.bus.write(T, address, value);
         }
 
-        // FIXME: Resetting disables logging (if enabled)
-        pub fn reset(self: *Self) void {
-            self.* = .{
-                .sched = self.sched,
-                .bus = self.bus,
-                .cpsr = .{ .raw = 0x0000_001F },
-                .spsr = .{ .raw = 0x0000_0000 },
-
-                .dtcm = if (is_v5te) .{} else {},
-                .itcm = if (is_v5te) .{} else {},
-            };
-        }
-
         pub inline fn hasSPSR(self: *const Self) bool {
             const mode = Mode.getChecked(self, self.cpsr.mode.read());
             return switch (mode) {
@@ -334,8 +351,13 @@ pub fn Arm32(comptime arch: Architecture) type {
                 thumb.lut[thumb.idx(opcode)](self, opcode);
             } else {
                 const opcode = self.pipe.step(self, u32) orelse return;
+                const cond: u4 = @truncate(opcode >> 28);
+
+                if (self.cpsr.check(Self.arch, cond)) {
+                    if (isa == .v5te and cond == 0b1111) {
+                        std.log.debug("TODO: Unconditional Instruction Extension Space\nopcode: 0x{X:0>8} | idx: 0x{X:} | ptr: {any}", .{ opcode, arm.idx(opcode), arm.lut[arm.idx(opcode)] });
+                    }
 
-                if (self.cpsr.check(@truncate(opcode >> 28))) {
                     arm.lut[arm.idx(opcode)](self, opcode);
                 }
             }
@@ -387,8 +409,31 @@ pub fn Arm32(comptime arch: Architecture) type {
             std.debug.panic(format, args);
         }
 
+        // TODO: Rename
+        pub fn undefinedInstructionTrap(self: *Self) void {
+            // Copy Values from Current Mode
+            const ret_addr = self.r[15] - @as(u32, if (self.cpsr.t.read()) 2 else 4);
+            const cpsr = self.cpsr.raw;
+
+            // Switch Mode
+            self.changeMode(.Undefined);
+            self.cpsr.t.write(false); // Force ARM Mode
+            self.cpsr.i.write(true); // Disable normal interrupts
+
+            self.r[14] = ret_addr; // Resume Execution
+            self.spsr.raw = cpsr; // Previous mode CPSR
+            self.r[15] = switch (Self.arch) {
+                .v4t => 0x0000_0004,
+                .v5te => blk: {
+                    const ctrl = self.cp15.read(0, 1, 0, 0);
+                    break :blk if (ctrl >> 13 & 1 == 1) 0xFFFF_0004 else 0x0000_0004;
+                },
+            };
+            self.pipe.reload(self);
+        }
+
         pub fn interface(self: *Self) Interpreter {
-            return switch (arch) {
+            return switch (isa) {
                 .v4t => .{ .v4t = self },
                 .v5te => .{ .v5te = self },
             };
@@ -402,6 +447,57 @@ fn Tcm(comptime count: usize, comptime default_addr: u32) type {
     return struct {
         buf: [count * KiB]u8 = [_]u8{0x00} ** (count * KiB),
         base_address: u32 = default_addr,
+        virt: struct { size: u32, mask: u32 } = .{ .size = count * KiB, .mask = (count * KiB) - 1 },
+
+        enabled: bool = true,
+        load_mode: bool = false,
+
+        /// Read from TCM
+        ///
+        /// Returns `T` on success, which is the value we have read from TCM.
+        /// Returns `null` on failure for one of the following reasons:
+        /// - TCM is disabled
+        /// - TCM is in load mode (TODO: What about SWP and SWPB)
+        /// - TCM Address is not mapped to TCM
+        ///
+        /// The caller doesn't particularly care about "why" though.
+        pub fn read(self: *const @This(), comptime T: type, address: u32) ?T {
+            const readInt = std.mem.readIntSliceLittle;
+
+            if (!self.enabled) return null;
+            if (self.load_mode) return null;
+
+            const start_addr = self.base_address;
+            const end_addr = self.base_address + self.virt.size;
+
+            if (start_addr <= address and address < end_addr) {
+                return readInt(T, self.buf[address & self.virt.mask ..][0..@sizeOf(T)]);
+            }
+
+            return null;
+        }
+
+        /// Write to TCM
+        ///
+        /// Returns `true` on success. Will return `false` for one of the following reasons:
+        /// - TCM is disabled
+        /// - Address is not mapped to TCM
+        ///
+        /// The caller doesn't particularly care about "why" though.
+        pub fn write(self: *@This(), comptime T: type, address: u32, value: T) bool {
+            const writeInt = std.mem.writeIntSliceLittle;
+            if (!self.enabled) return false;
+
+            const start_addr = self.base_address;
+            const end_addr = self.base_address + self.virt.size;
+
+            if (start_addr <= address and address < end_addr) {
+                writeInt(T, self.buf[address & self.virt.mask ..][0..@sizeOf(T)], value);
+                return true;
+            }
+
+            return false;
+        }
     };
 }
 
@@ -443,6 +539,8 @@ pub const PSR = extern union {
     t: Bit(u32, 5),
     f: Bit(u32, 6),
     i: Bit(u32, 7),
+
+    q: Bit(u32, 27), // ARMv5TE only
     v: Bit(u32, 28),
     c: Bit(u32, 29),
     z: Bit(u32, 30),
@@ -465,9 +563,9 @@ pub const PSR = extern union {
         std.debug.print("]\n", .{});
     }
 
-    pub inline fn check(self: @This(), cond: u4) bool {
+    pub inline fn check(self: @This(), isa: Architecture, cond: u4) bool {
         const flags: u4 = @truncate(self.raw >> 28);
 
-        return condition_lut[cond] & (@as(u16, 1) << flags) != 0;
+        return condition_lut(isa)[cond] & (@as(u16, 1) << flags) != 0;
     }
 };

src/arm/cpu/arm/block_data_transfer.zig

@@ -1,109 +1,153 @@
 pub fn blockDataTransfer(comptime InstrFn: type, comptime P: bool, comptime U: bool, comptime S: bool, comptime W: bool, comptime L: bool) InstrFn {
-    const Arm32 = @typeInfo(@typeInfo(InstrFn).Pointer.child).Fn.params[0].type.?;
+    const Arm32 = @typeInfo(@typeInfo(@typeInfo(InstrFn).Pointer.child).Fn.params[0].type.?).Pointer.child;
 
     return struct {
-        fn inner(cpu: Arm32, opcode: u32) void {
+        fn inner(cpu: *Arm32, opcode: u32) void {
             const rn: u4 = @truncate(opcode >> 16 & 0xF);
-            const rlist = opcode & 0xFFFF;
-            const r15 = rlist >> 15 & 1 == 1;
+            const rlist: u16 = @intCast(opcode & 0xFFFF);
 
-            var count: u32 = 0;
-            var i: u5 = 0;
-            var first: u4 = 0;
-            var write_to_base = true;
+            const reg_count: u32 = @popCount(rlist);
+            const first_in_list: u4 = @truncate(@ctz(rlist)); // note that @ctz(0x0000) and @ctz(0x0001) collide
 
-            while (i < 16) : (i += 1) {
-                const r: u4 = @truncate(15 - i);
-                if (rlist >> r & 1 == 1) {
-                    first = r;
-                    count += 1;
-                }
-            }
+            // U determines whether the LDM/STM transfer is made upwards (U == 1)
+            // or downwards (U == 0).
 
-            var start = cpu.r[rn];
-            if (U) {
-                start += if (P) 4 else 0;
-            } else {
-                start = start - (4 * count) + if (!P) 4 else 0;
-            }
+            const base_addr = cpu.r[rn];
 
-            var end = cpu.r[rn];
-            if (U) {
-                end = end + (4 * count) - if (!P) 4 else 0;
-            } else {
-                end -= if (P) 4 else 0;
-            }
+            const start_addr: u32 = if (U) blk: {
+                break :blk base_addr + if (P) 4 else 0;
+            } else blk: {
+                break :blk base_addr - (4 * reg_count) + if (!P) 4 else 0;
+            };
 
-            var new_base = cpu.r[rn];
-            if (U) {
-                new_base += 4 * count;
-            } else {
-                new_base -= 4 * count;
-            }
+            const new_base_addr: u32 = if (U) blk: {
+                break :blk base_addr + 4 * reg_count;
+            } else blk: {
+                break :blk base_addr - 4 * reg_count;
+            };
 
-            var address = start;
+            var address = start_addr;
+
+            // On Empty List:
+            //
+            // ARMv4 Only: R15 is Loaded/Stored
+            // ARMv4/Armv5: Rn = Rn +/- 0x40
 
             if (rlist == 0) {
-                var und_addr = cpu.r[rn];
-                if (U) {
-                    und_addr += if (P) 4 else 0;
-                } else {
-                    und_addr -= 0x40 - if (!P) 4 else 0;
+                if (Arm32.arch == .v4t) {
+                    const undefined_addr: u32 = if (U) blk: {
+                        break :blk base_addr + if (P) 4 else 0;
+                    } else blk: {
+                        break :blk base_addr - (0x40 - if (!P) 4 else 0);
+                    };
+
+                    if (L) {
+                        cpu.r[15] = cpu.read(u32, undefined_addr);
+                        cpu.pipe.reload(cpu);
+                    } else {
+                        cpu.write(u32, undefined_addr, cpu.r[15] + 4);
+                    }
                 }
 
-                if (L) {
-                    cpu.r[15] = cpu.read(u32, und_addr);
-                    cpu.pipe.reload(cpu);
-                } else {
-                    cpu.write(u32, und_addr, cpu.r[15] + 4);
-                }
-
-                cpu.r[rn] = if (U) cpu.r[rn] + 0x40 else cpu.r[rn] - 0x40;
+                cpu.r[rn] = if (U) base_addr + 0x40 else base_addr - 0x40;
                 return;
             }
 
-            i = first;
-            while (i < 16) : (i += 1) {
-                if (rlist >> i & 1 == 1) {
-                    transfer(cpu, r15, i, address);
-                    address += 4;
+            for (first_in_list..16) |idx| {
+                const i: u4 = @intCast(idx);
 
-                    if (W and !L and write_to_base) {
-                        cpu.r[rn] = new_base;
-                        write_to_base = false;
+                if (rlist >> i & 1 == 1) {
+                    if (L) {
+                        load(cpu, i, rlist, address);
+                    } else {
+                        store(cpu, rn, i, rlist, address, .{ .old_addr = base_addr, .new_addr = new_base_addr });
                     }
+
+                    address += 4;
                 }
             }
 
-            if (W and L and rlist >> rn & 1 == 0) cpu.r[rn] = new_base;
+            if (W and !L)
+                cpu.r[rn] = new_base_addr;
+
+            if (W and L) {
+                // What happens when W is set and Rn is in the rlist? (LDM)
+                //
+                // ARMv4: No writeback
+                // ARMv5: writeback if Rn is "the ONLY register" or NOT the LAST register
+
+                if (rlist >> rn & 1 == 0) { // rn is not in rlist
+                    cpu.r[rn] = new_base_addr;
+                    return;
+                }
+
+                switch (Arm32.arch) {
+                    .v4t => {}, // No Writeback
+                    .v5te => {
+                        const rn_is_last = (15 - @clz(rlist)) <= rn;
+
+                        if (reg_count == 1 or !rn_is_last) {
+                            cpu.r[rn] = new_base_addr;
+                        }
+                    },
+                }
+            }
         }
 
-        fn transfer(cpu: Arm32, r15_present: bool, i: u5, address: u32) void {
-            if (L) {
-                if (S and !r15_present) {
-                    // Always Transfer User mode Registers
-                    cpu.setUserModeRegister(i, cpu.read(u32, address));
-                } else {
-                    const value = cpu.read(u32, address);
+        fn load(cpu: *Arm32, ri: u4, rlist: u16, address: u32) void {
+            const has_r15 = rlist >> 15 & 1 == 1;
 
-                    cpu.r[i] = value;
-                    if (i == 0xF) {
-                        cpu.r[i] &= ~@as(u32, 3); // Align r15
-                        cpu.pipe.reload(cpu);
-
-                        if (S) cpu.setCpsr(cpu.spsr.raw);
-                    }
-                }
+            if (S and !has_r15) {
+                // Always Transfer User mode Registers
+                cpu.setUserModeRegister(ri, cpu.read(u32, address));
             } else {
-                if (S) {
-                    // Always Transfer User mode Registers
-                    // This happens regardless if r15 is in the list
-                    const value = cpu.getUserModeRegister(i);
-                    cpu.write(u32, address, value + if (i == 0xF) 4 else @as(u32, 0)); // PC is already 8 ahead to make 12
-                } else {
-                    cpu.write(u32, address, cpu.r[i] + if (i == 0xF) 4 else @as(u32, 0));
+                const value = cpu.read(u32, address);
+                cpu.r[ri] = value;
+
+                if (ri == 0xF) {
+                    const mask: u32 = if (Arm32.arch == .v5te) 1 else 3;
+                    cpu.r[ri] &= ~mask;
+
+                    if (Arm32.arch == .v5te) cpu.cpsr.t.write(value & 1 == 1);
+                    if (S) cpu.setCpsr(cpu.spsr.raw); // FIXME: before or after the reload?
+
+                    cpu.pipe.reload(cpu);
                 }
             }
         }
+
+        const BaseAddrs = struct { old_addr: u32, new_addr: u32 };
+
+        fn store(cpu: *Arm32, rn: u4, ri: u4, rlist: u16, address: u32, base: BaseAddrs) void {
+            const value = if (S) blk: {
+                // if S == true:
+                //     Always Transfer User mode Registers
+                //     This happens regardless if r15 is in the list
+
+                break :blk cpu.getUserModeRegister(ri);
+            } else blk: {
+                if (ri == rn) {
+                    // What happens when W is set and Rn is in the rlist? (STM)
+                    //
+                    // Armv4: Store OLD Base if Rb is FIRST entry in Rlist, otherwise store NEW base
+                    // Armv5: Always store OLD Base
+
+                    if (rlist >> rn & 1 == 0)
+                        break :blk base.new_addr;
+
+                    const mask = @as(u16, 1) << rn;
+                    const is_first = @popCount(rlist & (mask - 1)) == 0;
+
+                    break :blk switch (Arm32.arch) {
+                        .v4t => if (is_first) base.old_addr else base.new_addr,
+                        .v5te => base.old_addr,
+                    };
+                }
+
+                break :blk cpu.r[ri];
+            };
+
+            cpu.write(u32, address, value + if (ri == 0xF) 4 else @as(u32, 0));
+        }
     }.inner;
 }

src/arm/cpu/arm/branch.zig

@@ -1,23 +1,38 @@
 const sext = @import("zba-util").sext;
 
 pub fn branch(comptime InstrFn: type, comptime L: bool) InstrFn {
-    const Arm32 = @typeInfo(@typeInfo(InstrFn).Pointer.child).Fn.params[0].type.?;
+    const Arm32 = @typeInfo(@typeInfo(@typeInfo(InstrFn).Pointer.child).Fn.params[0].type.?).Pointer.child;
 
     return struct {
-        fn inner(cpu: Arm32, opcode: u32) void {
-            if (L) cpu.r[14] = cpu.r[15] - 4;
+        fn inner(cpu: *Arm32, opcode: u32) void {
+            const cond: u4 = @truncate(opcode >> 28);
+            switch (cond) {
+                0b1111 => { // BLX
+                    const H = L;
+                    const offset = sext(u32, u24, opcode) << 2 | @as(u32, @intFromBool(H)) << 1;
+
+                    cpu.r[14] = cpu.r[15] - 4;
+                    cpu.cpsr.t.set();
+
+                    cpu.r[15] +%= offset;
+                },
+                else => {
+                    if (L) cpu.r[14] = cpu.r[15] - 4;
+
+                    cpu.r[15] +%= sext(u32, u24, opcode) << 2;
+                },
+            }
 
-            cpu.r[15] +%= sext(u32, u24, opcode) << 2;
             cpu.pipe.reload(cpu);
         }
     }.inner;
 }
 
 pub fn branchAndExchange(comptime InstrFn: type) InstrFn {
-    const Arm32 = @typeInfo(@typeInfo(InstrFn).Pointer.child).Fn.params[0].type.?;
+    const Arm32 = @typeInfo(@typeInfo(@typeInfo(InstrFn).Pointer.child).Fn.params[0].type.?).Pointer.child;
 
     return struct {
-        pub fn inner(cpu: Arm32, opcode: u32) void {
+        pub fn inner(cpu: *Arm32, opcode: u32) void {
             const rn = opcode & 0xF;
 
             const thumb = cpu.r[rn] & 1 == 1;

src/arm/cpu/arm/coprocessor.zig

@@ -1,35 +1,145 @@
 const std = @import("std");
+const Bit = @import("bitfield").Bit;
 
 const log = std.log.scoped(.coprocessor_handler);
 
-pub fn dataTransfer(comptime InstrFn: type, comptime P: bool, comptime U: bool, comptime N: bool, comptime W: bool, comptime L: bool) InstrFn {
-    _ = L;
-    _ = W;
-    _ = N;
-    _ = U;
-    _ = P;
-    const Arm32 = @typeInfo(@typeInfo(InstrFn).Pointer.child).Fn.params[0].type.?;
+pub fn dataTransfer(
+    comptime InstrFn: type,
+    comptime P: bool,
+    comptime U: bool,
+    comptime N: bool,
+    comptime W: bool,
+    comptime L: bool,
+) InstrFn {
+    const Arm32 = @typeInfo(@typeInfo(@typeInfo(InstrFn).Pointer.child).Fn.params[0].type.?).Pointer.child;
 
     return struct {
-        fn inner(cpu: Arm32, opcode: u32) void {
-            _ = cpu;
+        fn inner(cpu: *Arm32, opcode: u32) void {
+            if (!P and !W and !U) return copExt(cpu, opcode); // Coprocessor Extension Space
 
-            log.err("TODO: handle 0x{X:0>8} which is a coprocessor data transfer instr", .{opcode});
+            const rn = opcode >> 16 & 0xF;
+            const crd = opcode >> 12 & 0xF;
+            const cp_num = opcode >> 8 & 0xF;
+            const offset = (opcode & 0xFF) << 2;
+
+            // TODO: Make sure this is comptime
+            const addr_mode: u2 = comptime @as(u2, @intFromBool(P)) << 1 | @intFromBool(W);
+
+            const start_address: u32 = switch (addr_mode) {
+                0b00 => blk: {
+                    // Unindexed Addressing
+                    std.debug.assert(U == true);
+
+                    break :blk cpu.r[rn];
+                },
+                0b01 => blk: {
+                    // Immediate Post-Indexed Addressing
+                    const addr = cpu.r[rn];
+                    cpu.r[rn] = if (U) cpu.r[rn] + offset else cpu.r[rn] - offset;
+
+                    break :blk addr;
+                },
+                0b10 => if (U) cpu.r[rn] + offset else cpu.r[rn] - offset, // Immediate Offset Addressing
+                0b11 => blk: {
+                    // Immediate Pre-Indexed Addressing
+                    cpu.r[rn] = if (U) cpu.r[rn] + offset else cpu.r[rn] - offset;
+
+                    break :blk cpu.r[rn];
+                },
+            };
+
+            // TODO: Increment address + 4 (and perform op) until coprocessor says stop
+
+            if (L) {
+                cpu.panic("TODO: ldc{s} p{}, c{}, 0x{X:0>8}", .{ [_]u8{if (N) 'l' else ' '}, cp_num, crd, start_address });
+            } else {
+                cpu.panic("TODO: stc{s} p{}, c{}, 0x{X:0>8}", .{ [_]u8{if (N) 'l' else ' '}, cp_num, crd, start_address });
+            }
+        }
+
+        fn copExt(cpu: *Arm32, opcode: u32) void {
+            const cp_num = opcode >> 8 & 0xF;
+            const rd = opcode >> 12 & 0xF;
+            const rn = opcode >> 16 & 0xF;
+            const crm = opcode & 0xF;
+
+            const cp_opcode = opcode >> 4 & 0xF; // FIXME: We could get this value at comptime
+
+            std.debug.assert(rd != 15); // UNPREDICTABLE
+            std.debug.assert(rn != 15); // UNPREDICTABLE
+
+            if (L) {
+                // MRRC
+                cpu.panic("TODO: mrrc p{}, {}, r{}, r{}, c{}", .{ cp_num, cp_opcode, rd, rn, crm });
+            } else {
+                // MCRR
+                cpu.panic("TODO: mcrr p{}, {}, r{}, r{}, c{}", .{ cp_num, cp_opcode, rd, rn, crm });
+            }
         }
     }.inner;
 }
 
 pub fn registerTransfer(comptime InstrFn: type, comptime opcode1: u3, comptime L: bool, comptime opcode2: u3) InstrFn {
-    _ = opcode2;
-    _ = L;
-    _ = opcode1;
-    const Arm32 = @typeInfo(@typeInfo(InstrFn).Pointer.child).Fn.params[0].type.?;
+    const Arm32 = @typeInfo(@typeInfo(@typeInfo(InstrFn).Pointer.child).Fn.params[0].type.?).Pointer.child;
 
     return struct {
-        fn inner(cpu: Arm32, opcode: u32) void {
-            _ = cpu;
+        fn inner(cpu: *Arm32, opcode: u32) void {
+            const crn: u4 = @intCast(opcode >> 16 & 0xF);
+            const rd = opcode >> 12 & 0xF;
+            const cp_num = opcode >> 8 & 0xF;
+            const crm: u4 = @intCast(opcode & 0xF);
 
-            log.err("TODO: handle 0x{X:0>8} which is a coprocessor register transfer instr", .{opcode});
+            switch (cp_num) {
+                14 => return,
+                15 => if (Arm32.arch == .v4t) return cpu.undefinedInstructionTrap(),
+                else => cpu.panic("MRC: unexpected coprocessor #: {}", .{cp_num}),
+            }
+
+            if (L) {
+                // MRC
+                const value = cpu.cp15.read(opcode1, crn, crm, opcode2);
+
+                if (rd != 0xF) {
+                    cpu.r[rd] = value;
+                    return;
+                }
+
+                // TODO: I can probably do this with a mask and the like
+                cpu.cpsr.n.write(value >> 31 & 1 == 1);
+                cpu.cpsr.z.write(value >> 30 & 1 == 1);
+                cpu.cpsr.c.write(value >> 29 & 1 == 1);
+                cpu.cpsr.v.write(value >> 28 & 1 == 1);
+            } else {
+                // MCR
+                std.debug.assert(rd != 0xF); // UNPREDICTABLE
+
+                cpu.cp15.write(opcode1, crn, crm, opcode2, cpu.r[rd]);
+
+                {
+                    // OK so the idea is that I don't want to pass the coprocessor a reference to the CPU,
+                    // so there's some side effects that we need to deal with. Right now I think I'll just process
+                    // all side affects on every MCR write and hope this isn't too awful
+                    // TODO: there has to be a better way.....
+
+                    // ICTM / DTCM Stuff
+                    const ctrl: cp15.Control = @bitCast(cpu.cp15.read(0, 1, 0, 0));
+                    cpu.dtcm.enabled = ctrl.dtcm_enable.read();
+                    cpu.dtcm.load_mode = ctrl.dtcm_load_mode.read();
+
+                    cpu.itcm.enabled = ctrl.itcm_enable.read();
+                    cpu.itcm.load_mode = ctrl.itcm_load_mode.read();
+
+                    const dtcm_size_base = cpu.cp15.read(0, 9, 1, 0); // mrc 0, c9, c1, 0
+                    const itcm_size_base = cpu.cp15.read(0, 9, 1, 1); // mrc 0, c9, c1, 1
+
+                    cpu.dtcm.base_address = dtcm_size_base & 0xFFFF_F000;
+                    cpu.dtcm.virt.size = @as(u32, 0x200) << @truncate(std.math.clamp(dtcm_size_base >> 1 & 0x1F, 3, 23));
+                    cpu.dtcm.virt.mask = std.math.clamp(cpu.dtcm.virt.size, 0, @as(u32, @intCast(cpu.dtcm.buf.len))) - 1;
+
+                    cpu.itcm.virt.size = @as(u32, 0x200) << @truncate(std.math.clamp(itcm_size_base >> 1 & 0x1F, 3, 23));
+                    cpu.itcm.virt.mask = std.math.clamp(cpu.itcm.virt.size, 0, @as(u32, @intCast(cpu.itcm.buf.len))) - 1;
+                }
+            }
         }
     }.inner;
 }
@@ -37,13 +147,30 @@ pub fn registerTransfer(comptime InstrFn: type, comptime opcode1: u3, comptime L
 pub fn dataProcessing(comptime InstrFn: type, comptime opcode1: u4, comptime opcode2: u3) InstrFn {
     _ = opcode2;
     _ = opcode1;
-    const Arm32 = @typeInfo(@typeInfo(InstrFn).Pointer.child).Fn.params[0].type.?;
+    const Arm32 = @typeInfo(@typeInfo(@typeInfo(InstrFn).Pointer.child).Fn.params[0].type.?).Pointer.child;
 
     return struct {
-        fn inner(cpu: Arm32, opcode: u32) void {
-            _ = cpu;
-
-            log.err("TODO: handle 0x{X:0>8} which is a coprocessor data processing instr", .{opcode});
+        fn inner(cpu: *Arm32, opcode: u32) void {
+            cpu.panic("TODO: handle 0x{X:0>8} which is a coprocessor data processing instr", .{opcode});
         }
     }.inner;
 }
+
+const cp15 = struct {
+    // Only the bits that are R/W on the NDS (for now)
+    const Control = extern union {
+        pu_enable: Bit(u32, 0),
+        unified_cache: Bit(u32, 2),
+        endian: Bit(u32, 7),
+        instruction_cache: Bit(u32, 12),
+        exception_vectors: Bit(u32, 13),
+        cache_replacement: Bit(u32, 14),
+        pre_armv5_mode: Bit(u32, 15),
+        dtcm_enable: Bit(u32, 16),
+        dtcm_load_mode: Bit(u32, 17),
+        itcm_enable: Bit(u32, 18),
+        itcm_load_mode: Bit(u32, 19),
+
+        raw: u32,
+    };
+};

src/arm/cpu/arm/data_processing.zig

@@ -2,10 +2,10 @@ const exec = @import("../barrel_shifter.zig").exec;
 const ror = @import("../barrel_shifter.zig").ror;
 
 pub fn dataProcessing(comptime InstrFn: type, comptime I: bool, comptime S: bool, comptime kind: u4) InstrFn {
-    const Arm32 = @typeInfo(@typeInfo(InstrFn).Pointer.child).Fn.params[0].type.?;
+    const Arm32 = @typeInfo(@typeInfo(@typeInfo(InstrFn).Pointer.child).Fn.params[0].type.?).Pointer.child;
 
     return struct {
-        fn inner(cpu: Arm32, opcode: u32) void {
+        fn inner(cpu: *Arm32, opcode: u32) void {
             const rd: u4 = @truncate(opcode >> 12 & 0xF);
             const rn = opcode >> 16 & 0xF;
             const old_carry = @intFromBool(cpu.cpsr.c.read());
@@ -152,7 +152,7 @@ pub fn dataProcessing(comptime InstrFn: type, comptime I: bool, comptime S: bool
             }
         }
 
-        fn undefinedTestBehaviour(cpu: Arm32) void {
+        fn undefinedTestBehaviour(cpu: *Arm32) void {
             @setCold(true);
             cpu.setCpsr(cpu.spsr.raw);
         }

src/arm/cpu/arm/half_signed_data_transfer.zig

@@ -1,11 +1,14 @@
+const std = @import("std");
 const sext = @import("zba-util").sext;
 const rotr = @import("zba-util").rotr;
 
+const log = std.log.scoped(.half_and_signed_data_transfer);
+
 pub fn halfAndSignedDataTransfer(comptime InstrFn: type, comptime P: bool, comptime U: bool, comptime I: bool, comptime W: bool, comptime L: bool) InstrFn {
-    const Arm32 = @typeInfo(@typeInfo(InstrFn).Pointer.child).Fn.params[0].type.?;
+    const Arm32 = @typeInfo(@typeInfo(@typeInfo(InstrFn).Pointer.child).Fn.params[0].type.?).Pointer.child;
 
     return struct {
-        fn inner(cpu: Arm32, opcode: u32) void {
+        fn inner(cpu: *Arm32, opcode: u32) void {
             const rn = opcode >> 16 & 0xF;
             const rd = opcode >> 12 & 0xF;
             const rm = opcode & 0xF;
@@ -17,9 +20,11 @@ pub fn halfAndSignedDataTransfer(comptime InstrFn: type, comptime P: bool, compt
             const modified_base = if (U) base +% offset else base -% offset;
             var address = if (P) modified_base else base;
 
+            const op: u2 = @truncate(opcode >> 5);
             var result: u32 = undefined;
+
             if (L) {
-                switch (@as(u2, @truncate(opcode >> 5))) {
+                switch (op) {
                     0b01 => {
                         // LDRH
                         const value = cpu.read(u16, address);
@@ -36,15 +41,63 @@ pub fn halfAndSignedDataTransfer(comptime InstrFn: type, comptime P: bool, compt
                         // FIXME: I shouldn't have to use @as(u8, ...) here
                         result = if (address & 1 == 1) sext(u32, u8, @as(u8, @truncate(value >> 8))) else sext(u32, u16, value);
                     },
-                    0b00 => unreachable, // SWP
+                    0b00 => unreachable,
                 }
             } else {
-                if (opcode >> 5 & 0x01 == 0x01) {
-                    // STRH
+                switch (op) {
+                    0b00 => {
+                        const B = I;
+                        const swap_addr = cpu.r[rn];
 
-                    // FIXME: I shouldn't have to use @as(u8, ...) here
-                    cpu.write(u16, address, @as(u16, @truncate(cpu.r[rd])));
-                } else unreachable; // SWP
+                        if (B) {
+                            // SWPB
+                            const value = cpu.read(u8, swap_addr);
+                            cpu.write(u8, swap_addr, @as(u8, @truncate(cpu.r[rm])));
+
+                            cpu.r[rd] = value;
+                        } else {
+                            // SWP
+                            const value = rotr(u32, cpu.read(u32, swap_addr), 8 * (swap_addr & 0x3));
+                            cpu.write(u32, swap_addr, cpu.r[rm]);
+
+                            cpu.r[rd] = value;
+                        }
+                    },
+                    0b01 => {
+                        // STRH
+
+                        // FIXME: I shouldn't have to use @as(u16, ...) here
+                        cpu.write(u16, address, @as(u16, @truncate(cpu.r[rd])));
+                    },
+                    0b10 => blk: {
+                        // LDRD
+                        if (Arm32.arch == .v4t) break :blk;
+                        if (rd & 0 != 0) cpu.panic("LDRD: UNDEFINED behaviour when Rd is not even", .{});
+                        if (rd == 0xE) cpu.panic("LDRD: UNPREDICTABLE behaviour when rd == 14", .{});
+                        if (address & 0x7 != 0b000) cpu.panic("LDRD: UNPREDICTABLE when address (0x{X:0>8} is not double (64-bit) aligned", .{address});
+
+                        // Why do we not make use of result here?
+                        //
+                        // It's because L is not set so there's no chance of writing an undefined
+                        // value to the register
+                        //
+                        // despite this reason, this is bad design imo
+                        // TODO: Refactor this handler
+
+                        cpu.r[rd] = cpu.read(u32, address);
+                        cpu.r[rd + 1] = cpu.read(u32, address + 4);
+                    },
+                    0b11 => {
+                        // STRD
+                        if (Arm32.arch != .v5te) cpu.panic("STRD: unsupported on arm{s}", .{@tagName(Arm32.arch)});
+                        if (rd & 0 != 0) cpu.panic("STRD: UNDEFINED behaviour when Rd is not even", .{});
+                        if (rd == 0xE) cpu.panic("STRD: UNPREDICTABLE behaviour when rd == 14", .{});
+                        if (address & 0x7 != 0b000) cpu.panic("STRD: UNPREDICTABLE when address (0x{X:0>8} is not double (64-bit) aligned", .{address});
+
+                        cpu.write(u32, address, cpu.r[rd]);
+                        cpu.write(u32, address + 4, cpu.r[rd + 1]);
+                    },
+                }
             }
 
             address = modified_base;

src/arm/cpu/arm/multiply.zig

@@ -1,56 +1,48 @@
-pub fn multiply(comptime InstrFn: type, comptime A: bool, comptime S: bool) InstrFn {
-    const Arm32 = @typeInfo(@typeInfo(InstrFn).Pointer.child).Fn.params[0].type.?;
+pub fn multiply(comptime InstrFn: type, comptime L: bool, comptime U: bool, comptime A: bool, comptime S: bool) InstrFn {
+    const Arm32 = @typeInfo(@typeInfo(@typeInfo(InstrFn).Pointer.child).Fn.params[0].type.?).Pointer.child;
 
     return struct {
-        fn inner(cpu: Arm32, opcode: u32) void {
+        fn inner(cpu: *Arm32, opcode: u32) void {
             const rd = opcode >> 16 & 0xF;
             const rn = opcode >> 12 & 0xF;
             const rs = opcode >> 8 & 0xF;
             const rm = opcode & 0xF;
 
-            const temp: u64 = @as(u64, cpu.r[rm]) * @as(u64, cpu.r[rs]) + if (A) cpu.r[rn] else 0;
-            const result: u32 = @truncate(temp);
-            cpu.r[rd] = result;
+            if (L) {
+                const rd_hi = rd;
+                const rd_lo = rn;
 
-            if (S) {
-                cpu.cpsr.n.write(result >> 31 & 1 == 1);
-                cpu.cpsr.z.write(result == 0);
-                // V is unaffected, C is *actually* undefined in ARMv4
-            }
-        }
-    }.inner;
-}
+                if (U) {
+                    // Signed (WHY IS IT U THEN?)
+                    var result: i64 = @as(i64, @as(i32, @bitCast(cpu.r[rm]))) * @as(i64, @as(i32, @bitCast(cpu.r[rs])));
+                    if (A) result +%= @bitCast(@as(u64, cpu.r[rd_hi]) << 32 | @as(u64, cpu.r[rd_lo]));
 
-pub fn multiplyLong(comptime InstrFn: type, comptime U: bool, comptime A: bool, comptime S: bool) InstrFn {
-    const Arm32 = @typeInfo(@typeInfo(InstrFn).Pointer.child).Fn.params[0].type.?;
+                    cpu.r[rd_hi] = @bitCast(@as(i32, @truncate(result >> 32)));
+                    cpu.r[rd_lo] = @bitCast(@as(i32, @truncate(result)));
+                } else {
+                    // Unsigned
+                    var result: u64 = @as(u64, cpu.r[rm]) * @as(u64, cpu.r[rs]);
+                    if (A) result +%= @as(u64, cpu.r[rd_hi]) << 32 | @as(u64, cpu.r[rd_lo]);
 
-    return struct {
-        fn inner(cpu: Arm32, opcode: u32) void {
-            const rd_hi = opcode >> 16 & 0xF;
-            const rd_lo = opcode >> 12 & 0xF;
-            const rs = opcode >> 8 & 0xF;
-            const rm = opcode & 0xF;
+                    cpu.r[rd_hi] = @truncate(result >> 32);
+                    cpu.r[rd_lo] = @truncate(result);
+                }
 
-            if (U) {
-                // Signed (WHY IS IT U THEN?)
-                var result: i64 = @as(i64, @as(i32, @bitCast(cpu.r[rm]))) * @as(i64, @as(i32, @bitCast(cpu.r[rs])));
-                if (A) result +%= @bitCast(@as(u64, cpu.r[rd_hi]) << 32 | @as(u64, cpu.r[rd_lo]));
-
-                cpu.r[rd_hi] = @bitCast(@as(i32, @truncate(result >> 32)));
-                cpu.r[rd_lo] = @bitCast(@as(i32, @truncate(result)));
+                if (S) {
+                    cpu.cpsr.z.write(cpu.r[rd_hi] == 0 and cpu.r[rd_lo] == 0);
+                    cpu.cpsr.n.write(cpu.r[rd_hi] >> 31 & 1 == 1);
+                    // C and V are set to meaningless values
+                }
             } else {
-                // Unsigned
-                var result: u64 = @as(u64, cpu.r[rm]) * @as(u64, cpu.r[rs]);
-                if (A) result +%= @as(u64, cpu.r[rd_hi]) << 32 | @as(u64, cpu.r[rd_lo]);
+                const temp: u64 = @as(u64, cpu.r[rm]) * @as(u64, cpu.r[rs]) + if (A) cpu.r[rn] else 0;
+                const result: u32 = @truncate(temp);
+                cpu.r[rd] = result;
 
-                cpu.r[rd_hi] = @truncate(result >> 32);
-                cpu.r[rd_lo] = @truncate(result);
-            }
-
-            if (S) {
-                cpu.cpsr.z.write(cpu.r[rd_hi] == 0 and cpu.r[rd_lo] == 0);
-                cpu.cpsr.n.write(cpu.r[rd_hi] >> 31 & 1 == 1);
-                // C and V are set to meaningless values
+                if (S) {
+                    cpu.cpsr.n.write(result >> 31 & 1 == 1);
+                    cpu.cpsr.z.write(result == 0);
+                    // V is unaffected, C is *actually* undefined in ARMv4
+                }
             }
         }
     }.inner;

src/arm/cpu/arm/psr_transfer.zig

@@ -1,58 +1,207 @@
 const std = @import("std");
 
 const PSR = @import("../../../arm.zig").PSR;
-
-const log = std.log.scoped(.PsrTransfer);
-
 const rotr = @import("zba-util").rotr;
 
-pub fn psrTransfer(comptime InstrFn: type, comptime I: bool, comptime R: bool, comptime kind: u2) InstrFn {
-    const Arm32 = @typeInfo(@typeInfo(InstrFn).Pointer.child).Fn.params[0].type.?;
+const log = std.log.scoped(.ctrl_ext_space);
+
+pub fn control(comptime InstrFn: type, comptime I: bool, comptime op: u6) InstrFn {
+    const Arm32 = @typeInfo(@typeInfo(@typeInfo(InstrFn).Pointer.child).Fn.params[0].type.?).Pointer.child;
 
     return struct {
-        fn inner(cpu: Arm32, opcode: u32) void {
-            switch (kind) {
-                0b00 => {
-                    // MRS
+        fn inner(cpu: *Arm32, opcode: u32) void {
+            if (I) {
+                // MSR Immediate
+                const R = op >> 5 & 1 == 1;
+                return msr(R, I, cpu, opcode);
+            }
+
+            switch (op) {
+                0b00_0000, 0b10_0000 => { // MRS
+                    const R = op >> 5 & 1 == 1;
                     const rd = opcode >> 12 & 0xF;
 
                     if (R and !cpu.hasSPSR()) log.err("Tried to read SPSR from User/System Mode", .{});
                     cpu.r[rd] = if (R) cpu.spsr.raw else cpu.cpsr.raw;
                 },
-                0b10 => {
-                    // MSR
-                    const field_mask: u4 = @truncate(opcode >> 16 & 0xF);
-                    const rm_idx = opcode & 0xF;
-                    const right = if (I) rotr(u32, opcode & 0xFF, (opcode >> 8 & 0xF) * 2) else cpu.r[rm_idx];
-
-                    if (R and !cpu.hasSPSR()) log.err("Tried to write to SPSR in User/System Mode", .{});
-
-                    if (R) {
-                        // arm.gba seems to expect the SPSR to do somethign in SYS mode,
-                        // so we just assume that despite writing to the SPSR in USR or SYS mode
-                        // being UNPREDICTABLE, it just magically has a working SPSR somehow
-                        cpu.spsr.raw = fieldMask(&cpu.spsr, field_mask, right);
-                    } else {
-                        if (cpu.isPrivileged()) cpu.setCpsr(fieldMask(&cpu.cpsr, field_mask, right));
-                    }
+                0b01_0000, 0b11_0000 => { // MSR (register)
+                    const R = op >> 5 & 1 == 1;
+                    msr(R, false, cpu, opcode);
                 },
-                else => cpu.panic("[CPU/PSR Transfer] Bits 21:220 of {X:0>8} are undefined", .{opcode}),
+                0b01_0001 => cpu.panic("TODO: implement v5TE BX", .{}),
+                0b11_0001 => { // CLZ
+                    if (Arm32.arch == .v4t) return cpu.undefinedInstructionTrap();
+                    const rd = opcode >> 12 & 0xF;
+                    const rm = opcode & 0xF;
+
+                    if (rd == 0xF) cpu.panic("CLZ: UNPREDICTABLE behaviour when rd == 15", .{});
+                    if (rm == 0xF) cpu.panic("CLZ: UNPREDICTABLE behaviour when rm == 15", .{});
+
+                    cpu.r[rd] = @clz(cpu.r[rm]);
+                },
+                0b01_0011 => { // BLX
+                    const rm = opcode & 0xF;
+
+                    const thumb = cpu.r[rm] & 1 == 1;
+                    cpu.r[14] = cpu.r[15] - 4; // TODO: Why - 4?
+
+                    cpu.r[15] = cpu.r[rm] & ~@as(u32, 1);
+                    cpu.cpsr.t.write(thumb);
+
+                    cpu.pipe.reload(cpu);
+                },
+                0b00_0101, 0b01_0101, 0b10_0101, 0b11_0101 => { // QADD / QDADD / QSUB / QDSUB
+                    if (Arm32.arch == .v4t) return cpu.undefinedInstructionTrap();
+                    const U = op >> 4 & 1 == 1;
+                    const D = op >> 5 & 1 == 1;
+
+                    const rm = opcode & 0xF;
+                    const rd = opcode >> 12 & 0xF;
+                    const rn = opcode >> 16 & 0xF;
+
+                    const left: i32 = @bitCast(cpu.r[rm]);
+                    const right: i32 = blk: {
+                        if (!D) break :blk @bitCast(cpu.r[rn]);
+
+                        const ret = @mulWithOverflow(@as(i32, @bitCast(cpu.r[rn])), 2);
+                        var product: i32 = ret[0];
+
+                        if (ret[1] == 0b1) {
+                            product = if (product < 0) std.math.maxInt(i32) else std.math.minInt(i32);
+                            cpu.cpsr.q.set();
+                        }
+
+                        break :blk product;
+                    };
+
+                    const ret = if (U) @subWithOverflow(left, right) else @addWithOverflow(left, right);
+                    var result: i32 = ret[0];
+
+                    if (ret[1] == 0b1) {
+                        result = if (result < 0) std.math.maxInt(i32) else std.math.minInt(i32);
+                        cpu.cpsr.q.set();
+                    }
+
+                    cpu.r[rd] = @bitCast(result);
+                },
+                0b01_0111 => cpu.panic("TODO: handle BKPT", .{}),
+                0b00_1000, 0b00_1010, 0b00_1100, 0b00_1110 => { // SMLA<x><y>
+                    if (Arm32.arch == .v4t) return; // no-op
+                    const X = op >> 1 & 1;
+                    const Y = op >> 2 & 1;
+
+                    const rm = opcode & 0xF;
+                    const rs = opcode >> 8 & 0xF;
+                    const rn = opcode >> 12 & 0xF;
+                    const rd = opcode >> 16 & 0xF;
+
+                    const left: i32 = @as(i16, @bitCast(@as(u16, @truncate(cpu.r[rm] >> 16 * X))));
+                    const right: i32 = @as(i16, @bitCast(@as(u16, @truncate(cpu.r[rs] >> 16 * Y))));
+                    const accumulate: i32 = @bitCast(cpu.r[rn]);
+
+                    const result = @addWithOverflow(left * right, accumulate);
+                    cpu.r[rd] = @bitCast(result[0]);
+
+                    if (result[1] == 0b1) cpu.cpsr.q.set();
+                },
+
+                0b10_1000, 0b10_1010, 0b10_1100, 0b10_1110 => { // SMLAL<x><y>
+                    const X = op >> 1 & 1;
+                    const Y = op >> 2 & 1;
+
+                    const rm = opcode & 0xF;
+                    const rs = opcode >> 8 & 0xF;
+                    const rdlo = opcode >> 12 & 0xF;
+                    const rdhi = opcode >> 16 & 0xF;
+
+                    const left: i64 = @as(i16, @bitCast(@as(u16, @truncate(cpu.r[rm] >> 16 * X))));
+                    const right: i64 = @as(i16, @bitCast(@as(u16, @truncate(cpu.r[rs] >> 16 * Y))));
+                    const product = left * right;
+
+                    const rdhi_val: i32 = @bitCast(cpu.r[rdhi]);
+                    const rdlo_val: i32 = @bitCast(cpu.r[rdlo]);
+
+                    const accumulate = @as(i64, rdhi_val) << 32 | rdlo_val;
+                    const sum = product +% accumulate;
+
+                    cpu.r[rdhi] = @bitCast(@as(i32, @truncate(sum >> 32)));
+                    cpu.r[rdlo] = @bitCast(@as(i32, @truncate(sum)));
+                },
+                0b01_1000, 0b01_1100 => { // SMLAW<y>
+                    const Y = op >> 2 & 1;
+
+                    // TODO: deduplicate all this
+                    const rm = opcode & 0xF;
+                    const rs = opcode >> 8 & 0xF;
+                    const rn = opcode >> 12 & 0xF;
+                    const rd = opcode >> 16 & 0xF;
+
+                    const right: i16 = @as(i16, @bitCast(@as(u16, @truncate(cpu.r[rs] >> 16 * Y))));
+                    const left: i48 = @as(i32, @bitCast(cpu.r[rm]));
+                    const accumulate: i32 = @bitCast(cpu.r[rn]);
+
+                    const ret = @addWithOverflow(@as(i32, @truncate((left * right) >> 16)), accumulate);
+
+                    cpu.r[rd] = @bitCast(ret[0]);
+                    if (ret[1] == 0b1) cpu.cpsr.q.set();
+                },
+
+                0b01_1010, 0b01_1110 => { // SMULW<y>
+                    const Y = op >> 2 & 1;
+
+                    const rm = opcode & 0xF;
+                    const rs = opcode >> 8 & 0xF;
+                    const rd = opcode >> 16 & 0xF;
+
+                    const right: i64 = @as(i16, @bitCast(@as(u16, @truncate(cpu.r[rs] >> 16 * Y))));
+                    const left: i64 = @as(i32, @bitCast(cpu.r[rm]));
+
+                    const product: i32 = @truncate((left * right) >> 16);
+                    cpu.r[rd] = @bitCast(product);
+                },
+                0b11_1000, 0b11_1010, 0b11_1100, 0b11_1110 => { // SMUL<x><y>
+                    const X = op >> 1 & 1;
+                    const Y = op >> 2 & 1;
+
+                    const rm = opcode & 0xF;
+                    const rs = opcode >> 8 & 0xF;
+                    const rd = opcode >> 16 & 0xF;
+
+                    const left: i32 = @as(i16, @bitCast(@as(u16, @truncate(cpu.r[rm] >> 16 * X))));
+                    const right: i32 = @as(i16, @bitCast(@as(u16, @truncate(cpu.r[rs] >> 16 * Y))));
+
+                    cpu.r[rd] = @bitCast(left *% right);
+                },
+                else => cpu.panic("0x{X:0>8} was improperly handled by the control instruction extension space", .{opcode}),
+            }
+        }
+
+        inline fn msr(comptime R: bool, comptime imm: bool, cpu: *Arm32, opcode: u32) void {
+            const field_mask: u4 = @truncate(opcode >> 16 & 0xF);
+            const rm_idx = opcode & 0xF;
+            const right = if (imm) rotr(u32, opcode & 0xFF, (opcode >> 8 & 0xF) * 2) else cpu.r[rm_idx];
+
+            if (R and !cpu.hasSPSR()) log.err("Tried to write to SPSR in User/System Mode", .{});
+
+            if (R) {
+                // arm.gba seems to expect the SPSR to do somethign in SYS mode,
+                // so we just assume that despite writing to the SPSR in USR or SYS mode
+                // being UNPREDICTABLE, it just magically has a working SPSR somehow
+                cpu.spsr.raw = fieldMask(&cpu.spsr, field_mask, right);
+            } else {
+                if (cpu.isPrivileged()) cpu.setCpsr(fieldMask(&cpu.cpsr, field_mask, right));
             }
         }
     }.inner;
 }
 
 fn fieldMask(psr: *const PSR, field_mask: u4, right: u32) u32 {
-    // This bitwise ORs bits 3 and 0 of the field mask into a u2
-    // We do this because we only care about bits 7:0 and 31:28 of the CPSR
-    const bits: u2 = @truncate((field_mask >> 2 & 0x2) | (field_mask & 1));
+    var mask: u32 = 0;
 
-    const mask: u32 = switch (bits) {
-        0b00 => 0x0000_0000,
-        0b01 => 0x0000_00FF,
-        0b10 => 0xF000_0000,
-        0b11 => 0xF000_00FF,
-    };
+    inline for (0..4) |i| {
+        if (field_mask & @as(u4, 1) << i != 0)
+            mask |= @as(u32, 0xFF) << 8 * i;
+    }
 
     return (psr.raw & ~mask) | (right & mask);
 }

src/arm/cpu/arm/single_data_swap.zig

@@ -1,29 +0,0 @@
-const rotr = @import("zba-util").rotr;
-
-pub fn singleDataSwap(comptime InstrFn: type, comptime B: bool) InstrFn {
-    const Arm32 = @typeInfo(@typeInfo(InstrFn).Pointer.child).Fn.params[0].type.?;
-
-    return struct {
-        fn inner(cpu: Arm32, opcode: u32) void {
-            const rn = opcode >> 16 & 0xF;
-            const rd = opcode >> 12 & 0xF;
-            const rm = opcode & 0xF;
-
-            const address = cpu.r[rn];
-
-            if (B) {
-                // SWPB
-                const value = cpu.read(u8, address);
-
-                // FIXME: I shouldn't have to use @as(u8, ...) here
-                cpu.write(u8, address, @as(u8, @truncate(cpu.r[rm])));
-                cpu.r[rd] = value;
-            } else {
-                // SWP
-                const value = rotr(u32, cpu.read(u32, address), 8 * (address & 0x3));
-                cpu.write(u32, address, cpu.r[rm]);
-                cpu.r[rd] = value;
-            }
-        }
-    }.inner;
-}

src/arm/cpu/arm/single_data_transfer.zig

@@ -3,10 +3,10 @@ const shifter = @import("../barrel_shifter.zig");
 const rotr = @import("zba-util").rotr;
 
 pub fn singleDataTransfer(comptime InstrFn: type, comptime I: bool, comptime P: bool, comptime U: bool, comptime B: bool, comptime W: bool, comptime L: bool) InstrFn {
-    const Arm32 = @typeInfo(@typeInfo(InstrFn).Pointer.child).Fn.params[0].type.?;
+    const Arm32 = @typeInfo(@typeInfo(@typeInfo(InstrFn).Pointer.child).Fn.params[0].type.?).Pointer.child;
 
     return struct {
-        fn inner(cpu: Arm32, opcode: u32) void {
+        fn inner(cpu: *Arm32, opcode: u32) void {
             const rn = opcode >> 16 & 0xF;
             const rd = opcode >> 12 & 0xF;
 
@@ -49,7 +49,15 @@ pub fn singleDataTransfer(comptime InstrFn: type, comptime I: bool, comptime P:
             if (L) {
                 // This emulates the LDR rd == rn behaviour
                 cpu.r[rd] = result;
-                if (rd == 0xF) cpu.pipe.reload(cpu);
+
+                if (rd == 0xF) {
+                    if (Arm32.arch == .v5te) {
+                        cpu.r[rd] &= ~@as(u32, 1);
+                        cpu.cpsr.t.write(result & 1 == 1);
+                    }
+
+                    cpu.pipe.reload(cpu);
+                }
             }
         }
     }.inner;

src/arm/cpu/arm/software_interrupt.zig

@@ -1,8 +1,8 @@
 pub fn armSoftwareInterrupt(comptime InstrFn: type) InstrFn {
-    const Arm32 = @typeInfo(@typeInfo(InstrFn).Pointer.child).Fn.params[0].type.?;
+    const Arm32 = @typeInfo(@typeInfo(@typeInfo(InstrFn).Pointer.child).Fn.params[0].type.?).Pointer.child;
 
     return struct {
-        fn inner(cpu: Arm32, _: u32) void {
+        fn inner(cpu: *Arm32, _: u32) void {
             // Copy Values from Current Mode
             const ret_addr = cpu.r[15] - 4;
             const cpsr = cpu.cpsr.raw;
@@ -14,7 +14,13 @@ pub fn armSoftwareInterrupt(comptime InstrFn: type) InstrFn {
 
             cpu.r[14] = ret_addr; // Resume Execution
             cpu.spsr.raw = cpsr; // Previous mode CPSR
-            cpu.r[15] = 0x0000_0008;
+            cpu.r[15] = switch (Arm32.arch) {
+                .v4t => 0x0000_0008,
+                .v5te => blk: {
+                    const ctrl = cpu.cp15.read(0, 1, 0, 0);
+                    break :blk if (ctrl >> 13 & 1 == 1) 0xFFFF_0008 else 0x0000_0008;
+                },
+            };
             cpu.pipe.reload(cpu);
         }
     }.inner;

src/arm/cpu/thumb/alu.zig

@@ -7,10 +7,10 @@ const asr = @import("../barrel_shifter.zig").asr;
 const ror = @import("../barrel_shifter.zig").ror;
 
 pub fn fmt4(comptime InstrFn: type, comptime op: u4) InstrFn {
-    const Arm32 = @typeInfo(@typeInfo(InstrFn).Pointer.child).Fn.params[0].type.?;
+    const Arm32 = @typeInfo(@typeInfo(@typeInfo(InstrFn).Pointer.child).Fn.params[0].type.?).Pointer.child;
 
     return struct {
-        fn inner(cpu: Arm32, opcode: u16) void {
+        fn inner(cpu: *Arm32, opcode: u16) void {
             const rs = opcode >> 3 & 0x7;
             const rd = opcode & 0x7;
             const carry = @intFromBool(cpu.cpsr.c.read());

src/arm/cpu/thumb/block_data_transfer.zig

@@ -1,8 +1,8 @@
 pub fn fmt14(comptime InstrFn: type, comptime L: bool, comptime R: bool) InstrFn {
-    const Arm32 = @typeInfo(@typeInfo(InstrFn).Pointer.child).Fn.params[0].type.?;
+    const Arm32 = @typeInfo(@typeInfo(@typeInfo(InstrFn).Pointer.child).Fn.params[0].type.?).Pointer.child;
 
     return struct {
-        fn inner(cpu: Arm32, opcode: u16) void {
+        fn inner(cpu: *Arm32, opcode: u16) void {
             const count = @intFromBool(R) + countRlist(opcode);
             const start = cpu.r[13] - if (!L) count * 4 else 0;
 
@@ -32,6 +32,8 @@ pub fn fmt14(comptime InstrFn: type, comptime L: bool, comptime R: bool) InstrFn
                 if (L) {
                     const value = cpu.read(u32, address);
                     cpu.r[15] = value & ~@as(u32, 1);
+
+                    if (Arm32.arch == .v5te) cpu.cpsr.t.write(value & 1 == 1);
                     cpu.pipe.reload(cpu);
                 } else {
                     cpu.write(u32, address, cpu.r[14]);
@@ -45,10 +47,10 @@ pub fn fmt14(comptime InstrFn: type, comptime L: bool, comptime R: bool) InstrFn
 }
 
 pub fn fmt15(comptime InstrFn: type, comptime L: bool, comptime rb: u3) InstrFn {
-    const Arm32 = @typeInfo(@typeInfo(InstrFn).Pointer.child).Fn.params[0].type.?;
+    const Arm32 = @typeInfo(@typeInfo(@typeInfo(InstrFn).Pointer.child).Fn.params[0].type.?).Pointer.child;
 
     return struct {
-        fn inner(cpu: Arm32, opcode: u16) void {
+        fn inner(cpu: *Arm32, opcode: u16) void {
             var address = cpu.r[rb];
             const end_address = cpu.r[rb] + 4 * countRlist(opcode);
 

src/arm/cpu/thumb/branch.zig

@@ -1,15 +1,15 @@
 const sext = @import("zba-util").sext;
 
 pub fn fmt16(comptime InstrFn: type, comptime cond: u4) InstrFn {
-    const Arm32 = @typeInfo(@typeInfo(InstrFn).Pointer.child).Fn.params[0].type.?;
+    const Arm32 = @typeInfo(@typeInfo(@typeInfo(InstrFn).Pointer.child).Fn.params[0].type.?).Pointer.child;
 
     return struct {
-        fn inner(cpu: Arm32, opcode: u16) void {
+        fn inner(cpu: *Arm32, opcode: u16) void {
             // B
             if (cond == 0xE or cond == 0xF)
                 cpu.panic("[CPU/THUMB.16] Undefined conditional branch with condition {}", .{cond});
 
-            if (!cpu.cpsr.check(cond)) return;
+            if (!cpu.cpsr.check(Arm32.arch, cond)) return;
 
             cpu.r[15] +%= sext(u32, u8, opcode & 0xFF) << 1;
             cpu.pipe.reload(cpu);
@@ -17,38 +17,37 @@ pub fn fmt16(comptime InstrFn: type, comptime cond: u4) InstrFn {
     }.inner;
 }
 
-pub fn fmt18(comptime InstrFn: type) InstrFn {
-    const Arm32 = @typeInfo(@typeInfo(InstrFn).Pointer.child).Fn.params[0].type.?;
+pub fn linkExchange(comptime InstrFn: type, comptime H: u2) InstrFn {
+    const Arm32 = @typeInfo(@typeInfo(@typeInfo(InstrFn).Pointer.child).Fn.params[0].type.?).Pointer.child;
 
     return struct {
-        // B but conditional
-        fn inner(cpu: Arm32, opcode: u16) void {
-            cpu.r[15] +%= sext(u32, u11, opcode & 0x7FF) << 1;
-            cpu.pipe.reload(cpu);
-        }
-    }.inner;
-}
-
-pub fn fmt19(comptime InstrFn: type, comptime is_low: bool) InstrFn {
-    const Arm32 = @typeInfo(@typeInfo(InstrFn).Pointer.child).Fn.params[0].type.?;
-
-    return struct {
-        fn inner(cpu: Arm32, opcode: u16) void {
-            // BL
+        fn inner(cpu: *Arm32, opcode: u16) void {
             const offset = opcode & 0x7FF;
 
-            if (is_low) {
-                // Instruction 2
-                const next_opcode = cpu.r[15] - 2;
+            switch (H) {
+                0b00 => { // Unconditional Branch
+                    cpu.r[15] +%= sext(u32, u11, opcode & 0x7FF) << 1;
+                    cpu.pipe.reload(cpu);
+                },
+                0b01 => { // BLX Pt. 2
+                    if (Arm32.arch == .v4t) cpu.panic("attempted to execute THUMB BLX(1), despite ARMv4T CPU", .{});
+                    const next_addr = cpu.r[15] - 2;
 
-                cpu.r[15] = cpu.r[14] +% (offset << 1);
-                cpu.r[14] = next_opcode | 1;
+                    cpu.r[15] = (cpu.r[14] +% (offset << 1)) & ~@as(u32, 0x3);
+                    cpu.r[14] = next_addr | 1;
+                    cpu.cpsr.t.unset();
 
-                cpu.pipe.reload(cpu);
-            } else {
-                // Instruction 1
-                const lr_offset = sext(u32, u11, offset) << 12;
-                cpu.r[14] = (cpu.r[15] +% lr_offset) & ~@as(u32, 1);
+                    cpu.pipe.reload(cpu);
+                },
+                0b10 => cpu.r[14] = cpu.r[15] +% (sext(u32, u11, offset) << 12), // BL / BLX Pt. 1
+                0b11 => { // BL Pt. 2
+                    const next_addr = cpu.r[15] - 2;
+
+                    cpu.r[15] = cpu.r[14] +% (offset << 1);
+                    cpu.r[14] = next_addr | 1;
+
+                    cpu.pipe.reload(cpu);
+                },
             }
         }
     }.inner;

src/arm/cpu/thumb/data_processing.zig

@@ -5,10 +5,10 @@ const lsr = @import("../barrel_shifter.zig").lsr;
 const asr = @import("../barrel_shifter.zig").asr;
 
 pub fn fmt1(comptime InstrFn: type, comptime op: u2, comptime offset: u5) InstrFn {
-    const Arm32 = @typeInfo(@typeInfo(InstrFn).Pointer.child).Fn.params[0].type.?;
+    const Arm32 = @typeInfo(@typeInfo(@typeInfo(InstrFn).Pointer.child).Fn.params[0].type.?).Pointer.child;
 
     return struct {
-        fn inner(cpu: Arm32, opcode: u16) void {
+        fn inner(cpu: *Arm32, opcode: u16) void {
             const rs = opcode >> 3 & 0x7;
             const rd = opcode & 0x7;
 
@@ -53,13 +53,24 @@ pub fn fmt1(comptime InstrFn: type, comptime op: u2, comptime offset: u5) InstrF
 }
 
 pub fn fmt5(comptime InstrFn: type, comptime op: u2, comptime h1: u1, comptime h2: u1) InstrFn {
-    const Arm32 = @typeInfo(@typeInfo(InstrFn).Pointer.child).Fn.params[0].type.?;
+    const Arm32 = @typeInfo(@typeInfo(@typeInfo(InstrFn).Pointer.child).Fn.params[0].type.?).Pointer.child;
 
     return struct {
-        fn inner(cpu: Arm32, opcode: u16) void {
+        fn inner(cpu: *Arm32, opcode: u16) void {
             const rs = @as(u4, h2) << 3 | (opcode >> 3 & 0x7);
             const rd = @as(u4, h1) << 3 | (opcode & 0x7);
 
+            if (Arm32.arch == .v5te and op == 0b11 and h1 == 0b1) {
+                // BLX
+                const rm = rs;
+
+                cpu.r[14] = (cpu.r[15] - 2) | 1;
+                cpu.cpsr.t.write(cpu.r[rm] & 1 == 1);
+
+                cpu.r[15] = cpu.r[rm] & ~@as(u32, 1);
+                cpu.pipe.reload(cpu);
+            }
+
             const op1 = cpu.r[rd];
             const op2 = cpu.r[rs];
 
@@ -108,10 +119,10 @@ pub fn fmt5(comptime InstrFn: type, comptime op: u2, comptime h1: u1, comptime h
 }
 
 pub fn fmt2(comptime InstrFn: type, comptime I: bool, is_sub: bool, rn: u3) InstrFn {
-    const Arm32 = @typeInfo(@typeInfo(InstrFn).Pointer.child).Fn.params[0].type.?;
+    const Arm32 = @typeInfo(@typeInfo(@typeInfo(InstrFn).Pointer.child).Fn.params[0].type.?).Pointer.child;
 
     return struct {
-        fn inner(cpu: Arm32, opcode: u16) void {
+        fn inner(cpu: *Arm32, opcode: u16) void {
             const rs = opcode >> 3 & 0x7;
             const rd: u3 = @truncate(opcode);
             const op1 = cpu.r[rs];
@@ -142,10 +153,10 @@ pub fn fmt2(comptime InstrFn: type, comptime I: bool, is_sub: bool, rn: u3) Inst
 }
 
 pub fn fmt3(comptime InstrFn: type, comptime op: u2, comptime rd: u3) InstrFn {
-    const Arm32 = @typeInfo(@typeInfo(InstrFn).Pointer.child).Fn.params[0].type.?;
+    const Arm32 = @typeInfo(@typeInfo(@typeInfo(InstrFn).Pointer.child).Fn.params[0].type.?).Pointer.child;
 
     return struct {
-        fn inner(cpu: Arm32, opcode: u16) void {
+        fn inner(cpu: *Arm32, opcode: u16) void {
             const op1 = cpu.r[rd];
             const op2: u32 = opcode & 0xFF; // Offset
 
@@ -182,10 +193,10 @@ pub fn fmt3(comptime InstrFn: type, comptime op: u2, comptime rd: u3) InstrFn {
 }
 
 pub fn fmt12(comptime InstrFn: type, comptime isSP: bool, comptime rd: u3) InstrFn {
-    const Arm32 = @typeInfo(@typeInfo(InstrFn).Pointer.child).Fn.params[0].type.?;
+    const Arm32 = @typeInfo(@typeInfo(@typeInfo(InstrFn).Pointer.child).Fn.params[0].type.?).Pointer.child;
 
     return struct {
-        fn inner(cpu: Arm32, opcode: u16) void {
+        fn inner(cpu: *Arm32, opcode: u16) void {
             // ADD
             const left = if (isSP) cpu.r[13] else cpu.r[15] & ~@as(u32, 2);
             const right = (opcode & 0xFF) << 2;
@@ -195,13 +206,23 @@ pub fn fmt12(comptime InstrFn: type, comptime isSP: bool, comptime rd: u3) Instr
 }
 
 pub fn fmt13(comptime InstrFn: type, comptime S: bool) InstrFn {
-    const Arm32 = @typeInfo(@typeInfo(InstrFn).Pointer.child).Fn.params[0].type.?;
+    const Arm32 = @typeInfo(@typeInfo(@typeInfo(InstrFn).Pointer.child).Fn.params[0].type.?).Pointer.child;
 
     return struct {
-        fn inner(cpu: Arm32, opcode: u16) void {
+        fn inner(cpu: *Arm32, opcode: u16) void {
             // ADD
             const offset = (opcode & 0x7F) << 2;
             cpu.r[13] = if (S) cpu.r[13] - offset else cpu.r[13] + offset;
         }
     }.inner;
 }
+
+pub fn bkpt(comptime InstrFn: type) InstrFn {
+    const Arm32 = @typeInfo(@typeInfo(@typeInfo(InstrFn).Pointer.child).Fn.params[0].type.?).Pointer.child;
+
+    return struct {
+        fn inner(cpu: *Arm32, _: u16) void {
+            cpu.panic("TODO: handle THUMB BKPT", .{});
+        }
+    }.inner;
+}

src/arm/cpu/thumb/data_transfer.zig

@@ -2,10 +2,10 @@ const rotr = @import("zba-util").rotr;
 const sext = @import("zba-util").sext;
 
 pub fn fmt6(comptime InstrFn: type, comptime rd: u3) InstrFn {
-    const Arm32 = @typeInfo(@typeInfo(InstrFn).Pointer.child).Fn.params[0].type.?;
+    const Arm32 = @typeInfo(@typeInfo(@typeInfo(InstrFn).Pointer.child).Fn.params[0].type.?).Pointer.child;
 
     return struct {
-        fn inner(cpu: Arm32, opcode: u16) void {
+        fn inner(cpu: *Arm32, opcode: u16) void {
             // LDR
             const offset = (opcode & 0xFF) << 2;
 
@@ -16,10 +16,10 @@ pub fn fmt6(comptime InstrFn: type, comptime rd: u3) InstrFn {
 }
 
 pub fn fmt78(comptime InstrFn: type, comptime op: u2, comptime T: bool) InstrFn {
-    const Arm32 = @typeInfo(@typeInfo(InstrFn).Pointer.child).Fn.params[0].type.?;
+    const Arm32 = @typeInfo(@typeInfo(@typeInfo(InstrFn).Pointer.child).Fn.params[0].type.?).Pointer.child;
 
     return struct {
-        fn inner(cpu: Arm32, opcode: u16) void {
+        fn inner(cpu: *Arm32, opcode: u16) void {
             const ro = opcode >> 6 & 0x7;
             const rb = opcode >> 3 & 0x7;
             const rd = opcode & 0x7;
@@ -81,10 +81,10 @@ pub fn fmt78(comptime InstrFn: type, comptime op: u2, comptime T: bool) InstrFn
 }
 
 pub fn fmt9(comptime InstrFn: type, comptime B: bool, comptime L: bool, comptime offset: u5) InstrFn {
-    const Arm32 = @typeInfo(@typeInfo(InstrFn).Pointer.child).Fn.params[0].type.?;
+    const Arm32 = @typeInfo(@typeInfo(@typeInfo(InstrFn).Pointer.child).Fn.params[0].type.?).Pointer.child;
 
     return struct {
-        fn inner(cpu: Arm32, opcode: u16) void {
+        fn inner(cpu: *Arm32, opcode: u16) void {
             const rb = opcode >> 3 & 0x7;
             const rd = opcode & 0x7;
 
@@ -117,10 +117,10 @@ pub fn fmt9(comptime InstrFn: type, comptime B: bool, comptime L: bool, comptime
 }
 
 pub fn fmt10(comptime InstrFn: type, comptime L: bool, comptime offset: u5) InstrFn {
-    const Arm32 = @typeInfo(@typeInfo(InstrFn).Pointer.child).Fn.params[0].type.?;
+    const Arm32 = @typeInfo(@typeInfo(@typeInfo(InstrFn).Pointer.child).Fn.params[0].type.?).Pointer.child;
 
     return struct {
-        fn inner(cpu: Arm32, opcode: u16) void {
+        fn inner(cpu: *Arm32, opcode: u16) void {
             const rb = opcode >> 3 & 0x7;
             const rd = opcode & 0x7;
 
@@ -141,10 +141,10 @@ pub fn fmt10(comptime InstrFn: type, comptime L: bool, comptime offset: u5) Inst
 }
 
 pub fn fmt11(comptime InstrFn: type, comptime L: bool, comptime rd: u3) InstrFn {
-    const Arm32 = @typeInfo(@typeInfo(InstrFn).Pointer.child).Fn.params[0].type.?;
+    const Arm32 = @typeInfo(@typeInfo(@typeInfo(InstrFn).Pointer.child).Fn.params[0].type.?).Pointer.child;
 
     return struct {
-        fn inner(cpu: Arm32, opcode: u16) void {
+        fn inner(cpu: *Arm32, opcode: u16) void {
             const offset = (opcode & 0xFF) << 2;
             const address = cpu.r[13] + offset;
 

src/arm/cpu/thumb/software_interrupt.zig

@@ -1,8 +1,8 @@
 pub fn fmt17(comptime InstrFn: type) InstrFn {
-    const Arm32 = @typeInfo(@typeInfo(InstrFn).Pointer.child).Fn.params[0].type.?;
+    const Arm32 = @typeInfo(@typeInfo(@typeInfo(InstrFn).Pointer.child).Fn.params[0].type.?).Pointer.child;
 
     return struct {
-        fn inner(cpu: Arm32, _: u16) void {
+        fn inner(cpu: *Arm32, _: u16) void {
             // Copy Values from Current Mode
             const ret_addr = cpu.r[15] - 2;
             const cpsr = cpu.cpsr.raw;
@@ -14,7 +14,13 @@ pub fn fmt17(comptime InstrFn: type) InstrFn {
 
             cpu.r[14] = ret_addr; // Resume Execution
             cpu.spsr.raw = cpsr; // Previous mode CPSR
-            cpu.r[15] = 0x0000_0008;
+            cpu.r[15] = switch (Arm32.arch) {
+                .v4t => 0x0000_0008,
+                .v5te => blk: {
+                    const ctrl = cpu.cp15.read(0, 1, 0, 0);
+                    break :blk if (ctrl >> 13 & 1 == 1) 0xFFFF_0008 else 0x0000_0008;
+                },
+            };
             cpu.pipe.reload(cpu);
         }
     }.inner;

src/arm/v4t.zig

@@ -5,17 +5,22 @@ pub const arm = struct {
     pub const lut: [0x1000]InstrFn = populate();
 
     const processing = @import("cpu/arm/data_processing.zig").dataProcessing;
-    const psrTransfer = @import("cpu/arm/psr_transfer.zig").psrTransfer;
     const transfer = @import("cpu/arm/single_data_transfer.zig").singleDataTransfer;
-    const halfSignedTransfer = @import("cpu/arm/half_signed_data_transfer.zig").halfAndSignedDataTransfer;
     const blockTransfer = @import("cpu/arm/block_data_transfer.zig").blockDataTransfer;
     const branch = @import("cpu/arm/branch.zig").branch;
     const branchExchange = @import("cpu/arm/branch.zig").branchAndExchange;
     const swi = @import("cpu/arm/software_interrupt.zig").armSoftwareInterrupt;
-    const swap = @import("cpu/arm/single_data_swap.zig").singleDataSwap;
 
-    const multiply = @import("cpu/arm/multiply.zig").multiply;
-    const multiplyLong = @import("cpu/arm/multiply.zig").multiplyLong;
+    /// Load Store Instruction Extention Space
+    const loadStoreExt = @import("cpu/arm/half_signed_data_transfer.zig").halfAndSignedDataTransfer;
+
+    /// Control Instruction Extension Space
+    const controlExt = @import("cpu/arm/psr_transfer.zig").control;
+
+    /// Arithmetic Instruction Extension Space
+    const multiplyExt = @import("cpu/arm/multiply.zig").multiply;
+
+    const cop = @import("cpu/arm/coprocessor.zig");
 
     /// Determine index into ARM InstrFn LUT
     pub fn idx(opcode: u32) u12 {
@@ -36,37 +41,30 @@ pub const arm = struct {
 
             for (&table, 0..) |*handler, i| {
                 handler.* = switch (@as(u2, i >> 10)) {
-                    0b00 => if (i == 0x121) blk: {
+                    0b00 => if (i == 0x121) blk: { // 12 bits
                         break :blk branchExchange(InstrFn);
-                    } else if (i & 0xFCF == 0x009) blk: {
-                        const A = i >> 5 & 1 == 1;
-                        const S = i >> 4 & 1 == 1;
-                        break :blk multiply(InstrFn, A, S);
-                    } else if (i & 0xFBF == 0x109) blk: {
-                        const B = i >> 6 & 1 == 1;
-                        break :blk swap(InstrFn, B);
-                    } else if (i & 0xF8F == 0x089) blk: {
+                    } else if (i & 0xF0F == 0x009) blk: { // 8 bits
+                        const L = i >> 7 & 1 == 1;
                         const U = i >> 6 & 1 == 1;
                         const A = i >> 5 & 1 == 1;
                         const S = i >> 4 & 1 == 1;
-                        break :blk multiplyLong(InstrFn, U, A, S);
-                    } else if (i & 0xE49 == 0x009 or i & 0xE49 == 0x049) blk: {
+                        break :blk multiplyExt(InstrFn, L, U, A, S);
+                    } else if (i & 0xE49 == 0x009 or i & 0xE49 == 0x049) blk: { // 6 bits
                         const P = i >> 8 & 1 == 1;
                         const U = i >> 7 & 1 == 1;
                         const I = i >> 6 & 1 == 1;
                         const W = i >> 5 & 1 == 1;
                         const L = i >> 4 & 1 == 1;
-                        break :blk halfSignedTransfer(InstrFn, P, U, I, W, L);
-                    } else if (i & 0xD90 == 0x100) blk: {
+                        break :blk loadStoreExt(InstrFn, P, U, I, W, L);
+                    } else if (i & 0xD90 == 0x100) blk: { // 5 bits
                         const I = i >> 9 & 1 == 1;
-                        const R = i >> 6 & 1 == 1;
-                        const kind = i >> 4 & 0x3;
-                        break :blk psrTransfer(InstrFn, I, R, kind);
+                        const op = ((i >> 5) & 0x3) << 4 | (i & 0xF);
+                        break :blk controlExt(InstrFn, I, op);
                     } else blk: {
                         const I = i >> 9 & 1 == 1;
                         const S = i >> 4 & 1 == 1;
-                        const instrKind = i >> 5 & 0xF;
-                        break :blk processing(InstrFn, I, S, instrKind);
+                        const instr_kind = i >> 5 & 0xF;
+                        break :blk processing(InstrFn, I, S, instr_kind);
                     },
                     0b01 => if (i >> 9 & 1 == 1 and i & 1 == 1) und else blk: {
                         const I = i >> 9 & 1 == 1;
@@ -91,8 +89,29 @@ pub const arm = struct {
                             const L = i >> 8 & 1 == 1;
                             break :blk branch(InstrFn, L);
                         },
-                        0b10 => und, // COP Data Transfer
-                        0b11 => if (i >> 8 & 1 == 1) swi(InstrFn) else und, // COP Data Operation + Register Transfer
+                        0b10 => blk: {
+                            const P = i >> 8 & 1 == 1;
+                            const U = i >> 7 & 1 == 1;
+                            const N = i >> 6 & 1 == 1;
+                            const W = i >> 5 & 1 == 1;
+                            const L = i >> 4 & 1 == 1;
+
+                            break :blk cop.dataTransfer(InstrFn, P, U, N, W, L);
+                        },
+                        0b11 => blk: {
+                            if (i >> 8 & 1 == 1) break :blk swi(InstrFn);
+
+                            const data_opcode1 = i >> 4 & 0xF; // bits 20 -> 23
+                            const reg_opcode1 = i >> 5 & 0x7; // bits 21 -> 23
+                            const opcode2 = i >> 1 & 0x7; // bits 5 -> 7
+                            const L = i >> 4 & 1 == 1; // bit 20
+
+                            // Bit 4 (index pos of 0) distinguishes between these classes of instructions
+                            break :blk switch (i & 1 == 1) {
+                                true => cop.registerTransfer(InstrFn, reg_opcode1, L, opcode2),
+                                false => cop.dataProcessing(InstrFn, data_opcode1, opcode2),
+                            };
+                        },
                     },
                 };
             }
@@ -209,12 +228,9 @@ pub const thumb = struct {
                             const cond = i >> 2 & 0xF;
                             break :blk branch.fmt16(InstrFn, cond);
                         },
-                        0b110 => branch.fmt18(
-                            InstrFn,
-                        ),
-                        0b111 => blk: {
-                            const is_low = i >> 5 & 1 == 1;
-                            break :blk branch.fmt19(InstrFn, is_low);
+                        0b110, 0b111 => blk: {
+                            const H = i >> 5 & 0x3;
+                            break :blk branch.linkExchange(InstrFn, H);
                         },
                     },
                 };

src/arm/v5te.zig

@@ -5,17 +5,20 @@ pub const arm = struct {
     pub const lut: [0x1000]InstrFn = populate();
 
     const processing = @import("cpu/arm/data_processing.zig").dataProcessing;
-    const psrTransfer = @import("cpu/arm/psr_transfer.zig").psrTransfer;
     const transfer = @import("cpu/arm/single_data_transfer.zig").singleDataTransfer;
-    const halfSignedTransfer = @import("cpu/arm/half_signed_data_transfer.zig").halfAndSignedDataTransfer;
     const blockTransfer = @import("cpu/arm/block_data_transfer.zig").blockDataTransfer;
     const branch = @import("cpu/arm/branch.zig").branch;
     const branchExchange = @import("cpu/arm/branch.zig").branchAndExchange;
     const swi = @import("cpu/arm/software_interrupt.zig").armSoftwareInterrupt;
-    const swap = @import("cpu/arm/single_data_swap.zig").singleDataSwap;
 
-    const multiply = @import("cpu/arm/multiply.zig").multiply;
-    const multiplyLong = @import("cpu/arm/multiply.zig").multiplyLong;
+    /// Load Store Instruction Extention Space
+    const loadStoreExt = @import("cpu/arm/half_signed_data_transfer.zig").halfAndSignedDataTransfer;
+
+    /// Control Instruction Extension Space
+    const controlExt = @import("cpu/arm/psr_transfer.zig").control;
+
+    /// Arithmetic Instruction Extension Space
+    const multiplyExt = @import("cpu/arm/multiply.zig").multiply;
 
     const cop = @import("cpu/arm/coprocessor.zig");
 
@@ -35,40 +38,35 @@ pub const arm = struct {
         return comptime comptime_blk: {
             @setEvalBranchQuota(0xE000);
             var table = [_]InstrFn{und} ** 0x1000;
+            // op : 27 26 25 24 23 22 21 20 07 06 05 04
+            // idx: 11 10 09 08 07 06 05 04 03 02 01 00
 
             for (&table, 0..) |*handler, i| {
                 handler.* = switch (@as(u2, i >> 10)) {
-                    0b00 => if (i == 0x121) blk: {
+                    0b00 => if (i == 0x121) blk: { // 12 bits
                         break :blk branchExchange(InstrFn);
-                    } else if (i & 0xFCF == 0x009) blk: {
-                        const A = i >> 5 & 1 == 1;
-                        const S = i >> 4 & 1 == 1;
-                        break :blk multiply(InstrFn, A, S);
-                    } else if (i & 0xFBF == 0x109) blk: {
-                        const B = i >> 6 & 1 == 1;
-                        break :blk swap(InstrFn, B);
-                    } else if (i & 0xF8F == 0x089) blk: {
+                    } else if (i & 0xF0F == 0x009) blk: { // 8 bits
+                        const L = i >> 7 & 1 == 1;
                         const U = i >> 6 & 1 == 1;
                         const A = i >> 5 & 1 == 1;
                         const S = i >> 4 & 1 == 1;
-                        break :blk multiplyLong(InstrFn, U, A, S);
-                    } else if (i & 0xE49 == 0x009 or i & 0xE49 == 0x049) blk: {
+                        break :blk multiplyExt(InstrFn, L, U, A, S);
+                    } else if (i & 0xE49 == 0x009 or i & 0xE49 == 0x049) blk: { // 6 bits
                         const P = i >> 8 & 1 == 1;
                         const U = i >> 7 & 1 == 1;
                         const I = i >> 6 & 1 == 1;
                         const W = i >> 5 & 1 == 1;
                         const L = i >> 4 & 1 == 1;
-                        break :blk halfSignedTransfer(InstrFn, P, U, I, W, L);
-                    } else if (i & 0xD90 == 0x100) blk: {
+                        break :blk loadStoreExt(InstrFn, P, U, I, W, L);
+                    } else if (i & 0xD90 == 0x100) blk: { // 6 bits
                         const I = i >> 9 & 1 == 1;
-                        const R = i >> 6 & 1 == 1;
-                        const kind = i >> 4 & 0x3;
-                        break :blk psrTransfer(InstrFn, I, R, kind);
+                        const op = ((i >> 5) & 0x3) << 4 | (i & 0xF);
+                        break :blk controlExt(InstrFn, I, op);
                     } else blk: {
                         const I = i >> 9 & 1 == 1;
                         const S = i >> 4 & 1 == 1;
-                        const instrKind = i >> 5 & 0xF;
-                        break :blk processing(InstrFn, I, S, instrKind);
+                        const instr_kind = i >> 5 & 0xF;
+                        break :blk processing(InstrFn, I, S, instr_kind);
                     },
                     0b01 => if (i >> 9 & 1 == 1 and i & 1 == 1) und else blk: {
                         const I = i >> 9 & 1 == 1;
@@ -151,6 +149,8 @@ pub const thumb = struct {
         return comptime comptime_blk: {
             @setEvalBranchQuota(5025); // This is exact
             var table = [_]InstrFn{und} ** 0x400;
+            //  9  8  7  6  5  4  3  2  1  0
+            // 15 14 13 12 11 10  9  8  7  6
 
             for (&table, 0..) |*handler, i| {
                 handler.* = switch (@as(u3, i >> 7 & 0x7)) {
@@ -212,13 +212,18 @@ pub const thumb = struct {
                             const rd = i >> 2 & 0x7;
                             break :blk processing.fmt12(InstrFn, isSP, rd);
                         },
-                        0b011 => if (i >> 4 & 1 == 1) blk: {
-                            const L = i >> 5 & 1 == 1;
-                            const R = i >> 2 & 1 == 1;
-                            break :blk block_transfer.fmt14(InstrFn, L, R);
-                        } else blk: {
-                            const S = i >> 1 & 1 == 1;
-                            break :blk processing.fmt13(InstrFn, S);
+                        0b011 => switch (@as(u2, @truncate(i >> 3 & 0x3))) {
+                            0b10 => blk: {
+                                // PUSH / POP
+                                const L = i >> 5 & 1 == 1;
+                                const R = i >> 2 & 1 == 1;
+                                break :blk block_transfer.fmt14(InstrFn, L, R);
+                            },
+                            0b11 => processing.bkpt(InstrFn),
+                            else => blk: {
+                                const S = i >> 1 & 1 == 1;
+                                break :blk processing.fmt13(InstrFn, S);
+                            },
                         },
                         0b100 => blk: {
                             const L = i >> 5 & 1 == 1;
@@ -232,12 +237,9 @@ pub const thumb = struct {
                             const cond = i >> 2 & 0xF;
                             break :blk branch.fmt16(InstrFn, cond);
                         },
-                        0b110 => branch.fmt18(
-                            InstrFn,
-                        ),
-                        0b111 => blk: {
-                            const is_low = i >> 5 & 1 == 1;
-                            break :blk branch.fmt19(InstrFn, is_low);
+                        0b110, 0b111 => blk: {
+                            const H = i >> 5 & 0x3;
+                            break :blk branch.linkExchange(InstrFn, H);
                         },
                     },
                 };

src/lib.zig

@@ -32,6 +32,38 @@ pub const Interpreter = union(enum) {
     }
 };
 
+test "create ARMv4T interface" {
+    var bus_impl = ExampleBus{};
+    var scheduler_impl = ExampleScheduler{};
+
+    const bus_interface = Bus.init(&bus_impl);
+    const scheduler_interface = Scheduler.init(&scheduler_impl);
+
+    var arm7tdmi = Arm7tdmi.init(scheduler_interface, bus_interface);
+    var icpu = arm7tdmi.interface();
+
+    icpu.reset();
+    icpu.step();
+    // TODO: call icpu.panic()
+}
+
+test "create ARMv5TE interface" {
+    var bus_impl = ExampleBus{};
+    var scheduler_impl = ExampleScheduler{};
+    var cop_impl = ExampleCoprocessor{};
+
+    const bus_interface = Bus.init(&bus_impl);
+    const scheduler_interface = Scheduler.init(&scheduler_impl);
+    const coprocessor_interface = Coprocessor.init(&cop_impl);
+
+    var arm946es = Arm946es.init(scheduler_interface, bus_interface, coprocessor_interface);
+    var icpu = arm946es.interface();
+
+    icpu.reset();
+    icpu.step();
+    // TODO: call icpu.panic();
+}
+
 pub const Bus = struct {
     ptr: *anyopaque,
     vtable: *const Vtable,
@@ -196,6 +228,118 @@ pub const Bus = struct {
     }
 };
 
+test "create Bus" {
+    var bus_impl = ExampleBus{};
+    const iface = Bus.init(&bus_impl);
+    _ = iface;
+}
+
+test "call Bus reads" {
+    var bus_impl = ExampleBus{};
+    const iface = Bus.init(&bus_impl);
+
+    _ = iface.read(u32, 0x0000_0000);
+    _ = iface.read(u16, 0x0000_0000);
+    _ = iface.read(u8, 0x0000_0000);
+
+    _ = iface.dbgRead(u32, 0x0000_0000);
+    _ = iface.dbgRead(u16, 0x0000_0000);
+    _ = iface.dbgRead(u8, 0x0000_0000);
+}
+
+test "call Bus writes" {
+    var bus_impl = ExampleBus{};
+    const iface = Bus.init(&bus_impl);
+
+    _ = iface.write(u32, 0x0000_0000, 0x0000_0000);
+    _ = iface.write(u16, 0x0000_0000, 0x0000);
+    _ = iface.write(u8, 0x0000_0000, 0x00);
+
+    _ = iface.dbgWrite(u32, 0x0000_0000, 0x0000_0000);
+    _ = iface.dbgWrite(u16, 0x0000_0000, 0x0000);
+    _ = iface.dbgWrite(u8, 0x0000_0000, 0x00);
+}
+
+pub const Coprocessor = struct {
+    ptr: *anyopaque,
+
+    // VTable
+    readFn: *const fn (ptr: *anyopaque, op1: u3, cn: u4, cm: u4, op2: u3) u32,
+    writeFn: *const fn (ptr: *anyopaque, op1: u3, cn: u4, cm: u4, op2: u3, value: u32) void,
+    resetFn: *const fn (ptr: *anyopaque) void,
+
+    pub fn init(obj: anytype) @This() {
+        const P = @TypeOf(obj);
+        const info = @typeInfo(P);
+
+        std.debug.assert(info == .Pointer); // `anytype` is a Pointer
+        std.debug.assert(info.Pointer.size == .One); // Single-Item Pointer
+        std.debug.assert(@typeInfo(info.Pointer.child) == .Struct); // Pointer Child is a `struct`
+
+        const impl = struct {
+            fn read(ptr: *anyopaque, op1: u3, cn: u4, cm: u4, op2: u3) u32 {
+                const self: P = @ptrCast(@alignCast(ptr));
+                return self.read(op1, cn, cm, op2);
+            }
+
+            fn write(ptr: *anyopaque, op1: u3, cn: u4, cm: u4, op2: u3, value: u32) void {
+                const self: P = @ptrCast(@alignCast(ptr));
+                return self.write(op1, cn, cm, op2, value);
+            }
+
+            fn reset(ptr: *anyopaque) void {
+                const self: P = @ptrCast(@alignCast(ptr));
+                return self.reset();
+            }
+        };
+
+        return .{
+            .ptr = obj,
+            .readFn = impl.read,
+            .writeFn = impl.write,
+            .resetFn = impl.reset,
+        };
+    }
+
+    pub fn read(self: @This(), op1: u3, cn: u4, cm: u4, op2: u3) u32 {
+        return self.readFn(self.ptr, op1, cn, cm, op2);
+    }
+
+    pub fn write(self: @This(), op1: u3, cn: u4, cm: u4, op2: u3, value: u32) void {
+        return self.writeFn(self.ptr, op1, cn, cm, op2, value);
+    }
+
+    pub fn reset(self: @This()) void {
+        return self.resetFn(self.ptr);
+    }
+};
+
+test "create Coprocessor" {
+    var cop_impl = ExampleCoprocessor{};
+    _ = Coprocessor.init(&cop_impl);
+}
+
+test "Coprocessor.read" {
+    var cop_impl = ExampleCoprocessor{};
+    const iface = Coprocessor.init(&cop_impl);
+
+    try testing.expectEqual(@as(u32, 0xDEADBEEF), iface.read(0, 0, 0, 0));
+}
+
+test "Coprocessor.write" {
+    var cop_impl = ExampleCoprocessor{};
+    const iface = Coprocessor.init(&cop_impl);
+
+    iface.write(0, 0, 0, 0, 0xDEADBEEF);
+}
+
+test "Coprocessor.reset" {
+    var cop_impl = ExampleCoprocessor{};
+    const iface = Coprocessor.init(&cop_impl);
+
+    iface.reset();
+}
+
 pub const Scheduler = struct {
     ptr: *anyopaque,
 
@@ -235,6 +379,27 @@ pub const Scheduler = struct {
     }
 };
 
+test "create Scheduler" {
+    var scheduler_impl = ExampleScheduler{};
+    const iface = Scheduler.init(&scheduler_impl);
+    _ = iface;
+}
+
+test "Scheduler.now()" {
+    var scheduler_impl = ExampleScheduler{};
+    const iface = Scheduler.init(&scheduler_impl);
+
+    try testing.expectEqual(@as(u64, 0), iface.now());
+}
+
+test "Scheduler.reset()" {
+    var scheduler_impl = ExampleScheduler{ .tick = std.math.maxInt(u64) };
+    const iface = Scheduler.init(&scheduler_impl);
+    iface.reset();
+
+    try testing.expectEqual(@as(u64, 0), scheduler_impl.tick);
+}
+
 // ---
 // TESTING
 // ---
@@ -282,61 +447,27 @@ const ExampleScheduler = struct {
     }
 };
 
-test "create IBus" {
-    var bus_impl = ExampleBus{};
-    const iface = Bus.init(&bus_impl);
-    _ = iface;
-}
+const ExampleCoprocessor = struct {
+    pub fn read(self: *@This(), op1: u3, cn: u4, cm: u4, op2: u3) u32 {
+        _ = op2;
+        _ = cm;
+        _ = cn;
+        _ = op1;
+        _ = self;
 
-test "call IBus reads" {
-    var bus_impl = ExampleBus{};
-    const iface = Bus.init(&bus_impl);
+        return 0xDEADBEEF;
+    }
 
-    _ = iface.read(u32, 0x0000_0000);
-    _ = iface.read(u16, 0x0000_0000);
-    _ = iface.read(u8, 0x0000_0000);
+    pub fn write(self: *@This(), op1: u3, cn: u4, cm: u4, op2: u3, value: u32) void {
+        _ = value;
+        _ = op2;
+        _ = cm;
+        _ = cn;
+        _ = op1;
+        _ = self;
+    }
 
-    _ = iface.dbgRead(u32, 0x0000_0000);
-    _ = iface.dbgRead(u16, 0x0000_0000);
-    _ = iface.dbgRead(u8, 0x0000_0000);
-}
-
-test "call IBus writes" {
-    var bus_impl = ExampleBus{};
-    const iface = Bus.init(&bus_impl);
-
-    _ = iface.write(u32, 0x0000_0000, 0x0000_0000);
-    _ = iface.write(u16, 0x0000_0000, 0x0000);
-    _ = iface.write(u8, 0x0000_0000, 0x00);
-
-    _ = iface.dbgWrite(u32, 0x0000_0000, 0x0000_0000);
-    _ = iface.dbgWrite(u16, 0x0000_0000, 0x0000);
-    _ = iface.dbgWrite(u8, 0x0000_0000, 0x00);
-}
-
-test "create ARMv4T interface" {
-    var bus_impl = ExampleBus{};
-    var scheduler_impl = ExampleScheduler{};
-
-    const bus_interface = Bus.init(&bus_impl);
-    const scheduler_interface = Scheduler.init(&scheduler_impl);
-
-    var arm7tdmi = Arm7tdmi.init(scheduler_interface, bus_interface);
-    var icpu = arm7tdmi.interface();
-
-    icpu.reset();
-    icpu.step();
-    // TODO: call icpu.panic()
-}
-
-test "create ARMv5TE interface" {
-    var bus_impl = ExampleBus{};
-    var scheduler_impl = ExampleScheduler{};
-
-    const bus_interface = Bus.init(&bus_impl);
-    const scheduler_interface = Scheduler.init(&scheduler_impl);
-
-    var arm946es = Arm946es.init(scheduler_interface, bus_interface);
-
-    _ = arm946es.interface();
-}
+    pub fn reset(self: *@This()) void {
+        self.* = .{};
+    }
+};