diff --git a/src/arm.zig b/src/arm.zig
index e345e69..4b21c4a 100644
--- a/src/arm.zig
+++ b/src/arm.zig
@@ -217,6 +217,24 @@ pub fn Arm32(comptime isa: Architecture) type {
             }
         };
 
+        pub fn dbgRead(self: *const Self, comptime T: type, address: u32) T {
+            if (is_v5te) {
+                if (self.itcm.read(T, address)) |val| return val;
+                if (self.dtcm.read(T, address)) |val| return val;
+            }
+
+            return self.bus.dbgRead(T, address);
+        }
+
+        pub fn dbgWrite(self: *Self, comptime T: type, address: u32, value: T) void {
+            if (is_v5te) {
+                if (self.itcm.write(T, address, value)) return;
+                if (self.dtcm.write(T, address, value)) return;
+            }
+
+            return self.bus.dbgWrite(T, address, value);
+        }
+
         // CPU needs it's own read/write fns due to ICTM and DCTM present in v5te
         // I considered implementing Bus.cpu_read and Bus.cpu_write but ended up considering that a bit too leaky
         pub fn read(self: *Self, comptime T: type, address: u32) T {