fix: pass more test roms

TODO: deduplicate please

src/core/Scheduler.zig

@@ -1,7 +1,6 @@
 const std = @import("std");
 
-const Bus9 = @import("nds9/Bus.zig");
-const Bus7 = @import("nds7/Bus.zig");
+const System = @import("emu.zig").System;
 
 const PriorityQueue = std.PriorityQueue(Event, void, Event.lessThan);
 const Allocator = std.mem.Allocator;
@@ -41,6 +40,10 @@ pub fn reset(self: *@This()) void {
     self.tick = 0;
 }
 
+pub inline fn peekTimestamp(self: *const @This()) u64 {
+    return self.queue.items[0].tick;
+}
+
 pub inline fn check(self: *@This()) ?Event {
     @setRuntimeSafety(false);
     if (self.tick < self.queue.items[0].tick) return null;
@@ -48,25 +51,25 @@ pub inline fn check(self: *@This()) ?Event {
     return self.queue.remove();
 }
 
-pub fn handle(self: *@This(), bus_ptr: ?*anyopaque, event: Event, late: u64) void {
+pub fn handle(self: *@This(), system: System, event: Event, late: u64) void {
     switch (event.kind) {
         .heat_death => unreachable,
         .nds7 => |ev| {
-            const bus: *Bus7 = @ptrCast(@alignCast(bus_ptr));
+            const bus = system.bus7;
             _ = bus;
 
             switch (ev) {}
         },
         .nds9 => |ev| {
-            const bus: *Bus9 = @ptrCast(@alignCast(bus_ptr));
+            const bus = system.bus9;
 
             switch (ev) {
                 .draw => {
                     bus.ppu.drawScanline(bus);
-                    bus.ppu.onHdrawEnd(self, late);
+                    bus.ppu.onHdrawEnd(system, self, late);
                 },
-                .hblank => bus.ppu.onHblankEnd(self, late),
-                .vblank => bus.ppu.onHblankEnd(self, late),
+                .hblank => bus.ppu.onHblankEnd(system, self, late),
+                .vblank => bus.ppu.onVblankEnd(system, self, late),
                 .sqrt => bus.io.sqrt.onSqrtCalc(),
                 .div => bus.io.div.onDivCalc(),
             }

src/core/emu.zig

@@ -5,6 +5,9 @@ const Scheduler = @import("Scheduler.zig");
 
 const Allocator = std.mem.Allocator;
 
+const dma7 = @import("nds7/dma.zig");
+const dma9 = @import("nds9/dma.zig");
+
 /// Load a NDS Cartridge
 ///
 /// intended to be used immediately after Emulator initialization
@@ -107,32 +110,46 @@ pub fn runFrame(scheduler: *Scheduler, system: System) void {
     const frame_end = scheduler.tick + cycles_per_frame;
 
     while (scheduler.tick < frame_end) {
-        system.arm7tdmi.step();
-        system.arm946es.step();
-        system.arm946es.step();
+        switch (isHalted(system)) {
+            .both => scheduler.tick = scheduler.peekTimestamp(),
+            inline else => |halt| {
+                if (!dma9.step(system.arm946es) and comptime halt != .arm9) {
+                    system.arm946es.step();
+                    system.arm946es.step();
+                }
+
+                if (!dma7.step(system.arm7tdmi) and comptime halt != .arm7) {
+                    system.arm7tdmi.step();
+                }
+            },
+        }
 
         if (scheduler.check()) |ev| {
             const late = scheduler.tick - ev.tick;
-
-            // this is kinda really jank lol
-            const bus_ptr: ?*anyopaque = switch (ev.kind) {
-                .heat_death => null,
-                .nds7 => system.bus7,
-                .nds9 => system.bus9,
-            };
-
-            scheduler.handle(bus_ptr, ev, late);
+            scheduler.handle(system, ev, late);
         }
     }
 }
 
+const Halted = enum { arm7, arm9, both, none };
+
+inline fn isHalted(system: System) Halted {
+    const ret = [_]Halted{ .none, .arm7, .arm9, .both };
+    const nds7_bus: *System.Bus7 = @ptrCast(@alignCast(system.arm7tdmi.bus.ptr));
+
+    const nds9_halt: u2 = @intFromBool(system.cp15.wait_for_interrupt);
+    const nds7_halt: u2 = @intFromBool(nds7_bus.io.haltcnt == .halt);
+
+    return ret[(nds9_halt << 1) | nds7_halt];
+}
+
 // FIXME: Perf win to allocating on the stack instead?
 pub const SharedCtx = struct {
     const MiB = 0x100000;
     const KiB = 0x400;
 
     pub const Io = @import("io.zig").Io;
-    const Vram = @import("ppu.zig").Vram;
+    const Vram = @import("ppu/Vram.zig");
 
     io: *Io,
     main: *[4 * MiB]u8,
@@ -248,15 +265,12 @@ pub const Wram = struct {
         }
     }
 
-    // TODO: Rename
-    const Device = enum { nds9, nds7 };
-
-    pub fn read(self: @This(), comptime T: type, comptime dev: Device, address: u32) T {
+    pub fn read(self: @This(), comptime T: type, comptime proc: System.Process, address: u32) T {
         const bits = @typeInfo(IntFittingRange(0, page_size - 1)).Int.bits;
         const masked_addr = address & (addr_space_size - 1);
         const page = masked_addr >> bits;
         const offset = masked_addr & (page_size - 1);
-        const table = if (dev == .nds9) self.nds9_table else self.nds7_table;
+        const table = if (proc == .nds9) self.nds9_table else self.nds7_table;
 
         if (table[page]) |some_ptr| {
             const ptr: [*]const T = @ptrCast(@alignCast(some_ptr));
@@ -264,16 +278,16 @@ pub const Wram = struct {
             return ptr[offset / @sizeOf(T)];
         }
 
-        log.err("{s}: read(T: {}, addr: 0x{X:0>8}) was in un-mapped WRAM space", .{ @tagName(dev), T, 0x0300_0000 + address });
+        log.err("{s}: read(T: {}, addr: 0x{X:0>8}) was in un-mapped WRAM space", .{ @tagName(proc), T, 0x0300_0000 + address });
         return 0x00;
     }
 
-    pub fn write(self: *@This(), comptime T: type, comptime dev: Device, address: u32, value: T) void {
+    pub fn write(self: *@This(), comptime T: type, comptime proc: System.Process, address: u32, value: T) void {
         const bits = @typeInfo(IntFittingRange(0, page_size - 1)).Int.bits;
         const masked_addr = address & (addr_space_size - 1);
         const page = masked_addr >> bits;
         const offset = masked_addr & (page_size - 1);
-        const table = if (dev == .nds9) self.nds9_table else self.nds7_table;
+        const table = if (proc == .nds9) self.nds9_table else self.nds7_table;
 
         if (table[page]) |some_ptr| {
             const ptr: [*]T = @ptrCast(@alignCast(some_ptr));
@@ -282,7 +296,7 @@ pub const Wram = struct {
             return;
         }
 
-        log.err("{s}: write(T: {}, addr: 0x{X:0>8}, value: 0x{X:0>8}) was in un-mapped WRAM space", .{ @tagName(dev), T, 0x0300_0000 + address, value });
+        log.err("{s}: write(T: {}, addr: 0x{X:0>8}, value: 0x{X:0>8}) was in un-mapped WRAM space", .{ @tagName(proc), T, 0x0300_0000 + address, value });
     }
 };
 
@@ -298,6 +312,8 @@ pub const System = struct {
     pub const Arm7tdmi = @import("arm32").Arm7tdmi;
     pub const Arm946es = @import("arm32").Arm946es;
 
+    pub const Process = enum { nds7, nds9 };
+
     arm7tdmi: *Arm7tdmi,
     arm946es: *Arm946es,
 
@@ -310,18 +326,35 @@ pub const System = struct {
         self.bus7.deinit(allocator);
         self.bus9.deinit(allocator);
     }
+
+    fn Cpu(comptime proc: Process) type {
+        return switch (proc) {
+            .nds7 => Arm7tdmi,
+            .nds9 => Arm946es,
+        };
+    }
+
+    fn Bus(comptime proc: Process) type {
+        return switch (proc) {
+            .nds7 => Bus7,
+            .nds9 => Bus9,
+        };
+    }
 };
 
-// FIXME: Using Wram.Device here is jank. System should probably carry an Enum + some Generic Type Fns
-pub fn handleInterrupt(comptime dev: Wram.Device, cpu: if (dev == .nds9) *System.Arm946es else *System.Arm7tdmi) void {
-    const Bus = if (dev == .nds9) System.Bus9 else System.Bus7;
-    const bus_ptr: *Bus = @ptrCast(@alignCast(cpu.bus.ptr));
+pub fn handleInterrupt(comptime proc: System.Process, cpu: *System.Cpu(proc)) void {
+    const bus_ptr: *System.Bus(proc) = @ptrCast(@alignCast(cpu.bus.ptr));
 
     if (!bus_ptr.io.ime or cpu.cpsr.i.read()) return; // ensure irqs are enabled
     if ((bus_ptr.io.ie.raw & bus_ptr.io.irq.raw) == 0) return; // ensure there is an irq to handle
 
-    // TODO: Handle HALT
-    // HALTCNG (NDS7) and CP15 (NDS9)
+    switch (proc) {
+        .nds9 => {
+            const cp15: *System.Cp15 = @ptrCast(@alignCast(cpu.cp15.ptr));
+            cp15.wait_for_interrupt = false;
+        },
+        .nds7 => bus_ptr.io.haltcnt = .execute,
+    }
 
     const ret_addr = cpu.r[15] - if (cpu.cpsr.t.read()) 0 else @as(u32, 4);
     const spsr = cpu.cpsr;
@@ -332,6 +365,41 @@ pub fn handleInterrupt(comptime dev: Wram.Device, cpu: if (dev == .nds9) *System
 
     cpu.r[14] = ret_addr;
     cpu.spsr.raw = spsr.raw;
-    cpu.r[15] = if (dev == .nds9) 0xFFFF_0018 else 0x0000_0018;
+    cpu.r[15] = if (proc == .nds9) 0xFFFF_0018 else 0x0000_0018;
     cpu.pipe.reload(cpu);
 }
+
+pub fn fastBoot(system: System) void {
+    {
+        const Bank = System.Arm946es.Bank;
+
+        const cpu = system.arm946es;
+
+        // from advanDS
+        cpu.spsr = .{ .raw = 0x0000_000DF };
+
+        @memset(cpu.r[0..12], 0x0000_0000); // r0 -> r11 are zeroed
+        // TODO: r12, r14, and r15 are set to the entrypoint?
+        cpu.r[13] = 0x0300_2F7C; // FIXME: Why is there (!) in GBATEK?
+        cpu.bank.r[Bank.regIdx(.Irq, .R13)] = 0x0300_3F80;
+        cpu.bank.r[Bank.regIdx(.Supervisor, .R13)] = 0x0300_3FC0;
+        cpu.bank.spsr[Bank.spsrIdx(.Irq)] = .{ .raw = 0x0000_0000 };
+        cpu.bank.spsr[Bank.spsrIdx(.Supervisor)] = .{ .raw = 0x0000_0000 };
+    }
+    {
+        const Bank = System.Arm7tdmi.Bank;
+
+        const cpu = system.arm7tdmi;
+
+        // from advanDS
+        cpu.spsr = .{ .raw = 0x0000_000D3 };
+
+        @memset(cpu.r[0..12], 0x0000_0000); // r0 -> r11 are zeroed
+        // TODO: r12, r14, and r15 are set to the entrypoint?
+        cpu.r[13] = 0x0380_FD80;
+        cpu.bank.r[Bank.regIdx(.Irq, .R13)] = 0x0380_FF80;
+        cpu.bank.r[Bank.regIdx(.Supervisor, .R13)] = 0x0380_FFC0;
+        cpu.bank.spsr[Bank.spsrIdx(.Irq)] = .{ .raw = 0x0000_0000 };
+        cpu.bank.spsr[Bank.spsrIdx(.Supervisor)] = .{ .raw = 0x0000_0000 };
+    }
+}

src/core/io.zig

@@ -12,6 +12,9 @@ pub const Io = struct {
     ipc: Ipc = .{},
 
     wramcnt: WramCnt = .{ .raw = 0x00 },
+
+    // Read Only
+    keyinput: AtomicKeyInput = .{},
 };
 
 fn warn(comptime format: []const u8, args: anytype) u0 {
@@ -33,8 +36,6 @@ const Ipc = struct {
 
     // TODO: DS Cartridge I/O Ports
 
-    const Source = enum { nds7, nds9 };
-
     const Impl = struct {
         /// IPC Synchronize
         /// Read/Write
@@ -57,8 +58,8 @@ const Ipc = struct {
 
     /// IPCSYNC
     /// Read/Write
-    pub fn setIpcSync(self: *@This(), comptime src: Source, value: anytype) void {
-        switch (src) {
+    pub fn setIpcSync(self: *@This(), comptime proc: System.Process, value: anytype) void {
+        switch (proc) {
             .nds7 => {
                 self._nds7.sync.raw = masks.ipcFifoSync(self._nds7.sync.raw, value);
                 self._nds9.sync.raw = masks.mask(self._nds9.sync.raw, (self._nds7.sync.raw >> 8) & 0xF, 0xF);
@@ -106,8 +107,8 @@ const Ipc = struct {
 
     /// IPCFIFOCNT
     /// Read/Write
-    pub fn setIpcFifoCnt(self: *@This(), comptime src: Source, value: anytype) void {
-        switch (src) {
+    pub fn setIpcFifoCnt(self: *@This(), comptime proc: System.Process, value: anytype) void {
+        switch (proc) {
             .nds7 => self._nds7.cnt.raw = masks.ipcFifoCnt(self._nds7.cnt.raw, value),
             .nds9 => self._nds9.cnt.raw = masks.ipcFifoCnt(self._nds9.cnt.raw, value),
         }
@@ -115,8 +116,8 @@ const Ipc = struct {
 
     /// IPC Send FIFO
     /// Write-Only
-    pub fn send(self: *@This(), comptime src: Source, value: u32) void {
-        switch (src) {
+    pub fn send(self: *@This(), comptime proc: System.Process, value: u32) void {
+        switch (proc) {
             .nds7 => {
                 if (!self._nds7.cnt.enable_fifos.read()) return;
                 self._nds7.fifo.push(value) catch unreachable; // see early return above
@@ -170,8 +171,8 @@ const Ipc = struct {
 
     /// IPC Receive FIFO
     /// Read-Only
-    pub fn recv(self: *@This(), comptime src: Source) u32 {
-        switch (src) {
+    pub fn recv(self: *@This(), comptime proc: System.Process) u32 {
+        switch (proc) {
             .nds7 => {
                 const enabled = self._nds7.cnt.enable_fifos.read();
                 const val_opt = if (enabled) self._nds9.fifo.pop() else self._nds9.fifo.peek();
@@ -320,6 +321,15 @@ pub const masks = struct {
 
 // FIXME: bitfields depends on NDS9 / NDS7
 pub const IntEnable = extern union {
+    vblank: Bit(u32, 0),
+    hblank: Bit(u32, 1),
+    coincidence: Bit(u32, 2),
+
+    dma0: Bit(u32, 8),
+    dma1: Bit(u32, 9),
+    dma2: Bit(u32, 10),
+    dma3: Bit(u32, 11),
+
     ipcsync: Bit(u32, 16),
     ipc_send_empty: Bit(u32, 17),
     ipc_recv_not_empty: Bit(u32, 18),
@@ -386,3 +396,41 @@ const Fifo = struct {
         return idx & _mask;
     }
 };
+
+/// Read Only
+/// 0 = Pressed, 1 = Released
+pub const KeyInput = extern union {
+    a: Bit(u16, 0),
+    b: Bit(u16, 1),
+    select: Bit(u16, 2),
+    start: Bit(u16, 3),
+    right: Bit(u16, 4),
+    left: Bit(u16, 5),
+    up: Bit(u16, 6),
+    down: Bit(u16, 7),
+    shoulder_r: Bit(u16, 8),
+    shoulder_l: Bit(u16, 9),
+    raw: u16,
+};
+
+const AtomicKeyInput = struct {
+    const Self = @This();
+    const Ordering = std.atomic.Ordering;
+
+    inner: KeyInput = .{ .raw = 0x03FF },
+
+    pub inline fn load(self: *const Self, comptime ordering: Ordering) u16 {
+        return switch (ordering) {
+            .AcqRel, .Release => @compileError("not supported for atomic loads"),
+            else => @atomicLoad(u16, &self.inner.raw, ordering),
+        };
+    }
+
+    pub inline fn fetchOr(self: *Self, value: u16, comptime ordering: Ordering) void {
+        _ = @atomicRmw(u16, &self.inner.raw, .Or, value, ordering);
+    }
+
+    pub inline fn fetchAnd(self: *Self, value: u16, comptime ordering: Ordering) void {
+        _ = @atomicRmw(u16, &self.inner.raw, .And, value, ordering);
+    }
+};

src/core/nds7/Bus.zig

@@ -4,10 +4,12 @@ const io = @import("io.zig");
 const Scheduler = @import("../Scheduler.zig");
 const SharedCtx = @import("../emu.zig").SharedCtx;
 const Wram = @import("../emu.zig").Wram;
-const Vram = @import("../ppu.zig").Vram;
+const Vram = @import("../ppu/Vram.zig");
 const Bios = @import("Bios.zig");
 const forceAlign = @import("../emu.zig").forceAlign;
 
+const Controllers = @import("dma.zig").Controllers;
+
 const Allocator = std.mem.Allocator;
 
 const Mode = enum { normal, debug };
@@ -22,6 +24,8 @@ shr_wram: *Wram,
 wram: *[64 * KiB]u8,
 vram: *Vram,
 
+dma: Controllers = .{},
+
 io: io.Io,
 bios: Bios,
 
@@ -78,7 +82,8 @@ fn _read(self: *@This(), comptime T: type, comptime mode: Mode, address: u32) T
         0x0380_0000...0x03FF_FFFF => readInt(T, self.wram[aligned_addr & 0x0000_FFFF ..][0..byte_count]),
         0x0400_0000...0x04FF_FFFF => io.read(self, T, aligned_addr),
         0x0600_0000...0x06FF_FFFF => self.vram.read(T, .nds7, aligned_addr),
-        else => warn("unexpected read: 0x{x:0>8} -> {}", .{ aligned_addr, T }),
+
+        else => warn("unexpected: read(T: {}, addr: 0x{X:0>8}) {} ", .{ T, address, T }),
     };
 }
 
@@ -109,10 +114,10 @@ fn _write(self: *@This(), comptime T: type, comptime mode: Mode, address: u32, v
             0b00 => writeInt(T, self.wram[aligned_addr & 0x0000_FFFF ..][0..byte_count], value),
             else => self.shr_wram.write(T, .nds7, aligned_addr, value),
         },
-        0x0380_0000...0x0380_FFFF => writeInt(T, self.wram[aligned_addr & 0x0000_FFFF ..][0..byte_count], value),
+        0x0380_0000...0x03FF_FFFF => writeInt(T, self.wram[aligned_addr & 0x0000_FFFF ..][0..byte_count], value),
         0x0400_0000...0x04FF_FFFF => io.write(self, T, aligned_addr, value),
         0x0600_0000...0x06FF_FFFF => self.vram.write(T, .nds7, aligned_addr, value),
-        else => log.warn("unexpected write: 0x{X:}{} -> 0x{X:0>8}", .{ value, T, aligned_addr }),
+        else => log.warn("unexpected: write(T: {}, addr: 0x{X:0>8}, value: 0x{X:0>8})", .{ T, address, value }),
     }
 }
 

src/core/nds7/dma.zig

@@ -0,0 +1,374 @@
+const std = @import("std");
+
+const System = @import("../emu.zig").System;
+const DmaCnt = @import("io.zig").DmaCnt;
+
+const rotr = std.math.rotr;
+const shift = @import("../../util.zig").shift;
+const subset = @import("../../util.zig").subset;
+
+const handleInterrupt = @import("../emu.zig").handleInterrupt;
+
+const log = std.log.scoped(.nds7_dma_transfer);
+
+pub const Controllers = struct {
+    Controller(0) = Controller(0){},
+    Controller(1) = Controller(1){},
+    Controller(2) = Controller(2){},
+    Controller(3) = Controller(3){},
+};
+
+pub fn read(comptime T: type, dma: *const Controllers, addr: u32) ?T {
+    const byte_addr: u8 = @truncate(addr);
+
+    return switch (T) {
+        u32 => switch (byte_addr) {
+            0xB0, 0xB4 => null, // DMA0SAD, DMA0DAD,
+            0xB8 => @as(T, dma.*[0].dmacntH()) << 16, // DMA0CNT_L is write-only
+            0xBC, 0xC0 => null, // DMA1SAD, DMA1DAD
+            0xC4 => @as(T, dma.*[1].dmacntH()) << 16, // DMA1CNT_L is write-only
+            0xC8, 0xCC => null, // DMA2SAD, DMA2DAD
+            0xD0 => @as(T, dma.*[2].dmacntH()) << 16, // DMA2CNT_L is write-only
+            0xD4, 0xD8 => null, // DMA3SAD, DMA3DAD
+            0xDC => @as(T, dma.*[3].dmacntH()) << 16, // DMA3CNT_L is write-only
+            else => warn("unaligned {} read from 0x{X:0>8}", .{ T, addr }),
+        },
+        u16 => switch (byte_addr) {
+            0xB0, 0xB2, 0xB4, 0xB6 => null, // DMA0SAD, DMA0DAD
+            0xB8 => 0x0000, // DMA0CNT_L, suite.gba expects 0x0000 instead of 0xDEAD
+            0xBA => dma.*[0].dmacntH(),
+
+            0xBC, 0xBE, 0xC0, 0xC2 => null, // DMA1SAD, DMA1DAD
+            0xC4 => 0x0000, // DMA1CNT_L
+            0xC6 => dma.*[1].dmacntH(),
+
+            0xC8, 0xCA, 0xCC, 0xCE => null, // DMA2SAD, DMA2DAD
+            0xD0 => 0x0000, // DMA2CNT_L
+            0xD2 => dma.*[2].dmacntH(),
+
+            0xD4, 0xD6, 0xD8, 0xDA => null, // DMA3SAD, DMA3DAD
+            0xDC => 0x0000, // DMA3CNT_L
+            0xDE => dma.*[3].dmacntH(),
+            else => warn("unaligned {} read from 0x{X:0>8}", .{ T, addr }),
+        },
+        u8 => switch (byte_addr) {
+            0xB0...0xB7 => null, // DMA0SAD, DMA0DAD
+            0xB8, 0xB9 => 0x00, // DMA0CNT_L
+            0xBA, 0xBB => @truncate(dma.*[0].dmacntH() >> shift(u16, byte_addr)),
+
+            0xBC...0xC3 => null, // DMA1SAD, DMA1DAD
+            0xC4, 0xC5 => 0x00, // DMA1CNT_L
+            0xC6, 0xC7 => @truncate(dma.*[1].dmacntH() >> shift(u16, byte_addr)),
+
+            0xC8...0xCF => null, // DMA2SAD, DMA2DAD
+            0xD0, 0xD1 => 0x00, // DMA2CNT_L
+            0xD2, 0xD3 => @truncate(dma.*[2].dmacntH() >> shift(u16, byte_addr)),
+
+            0xD4...0xDB => null, // DMA3SAD, DMA3DAD
+            0xDC, 0xDD => 0x00, // DMA3CNT_L
+            0xDE, 0xDF => @truncate(dma.*[3].dmacntH() >> shift(u16, byte_addr)),
+            else => warn("unexpected {} read from 0x{X:0>8}", .{ T, addr }),
+        },
+        else => @compileError("DMA: Unsupported read width"),
+    };
+}
+
+pub fn write(comptime T: type, dma: *Controllers, addr: u32, value: T) void {
+    const byte_addr: u8 = @truncate(addr);
+
+    switch (T) {
+        u32 => switch (byte_addr) {
+            0xB0 => dma.*[0].setDmasad(value),
+            0xB4 => dma.*[0].setDmadad(value),
+            0xB8 => dma.*[0].setDmacnt(value),
+
+            0xBC => dma.*[1].setDmasad(value),
+            0xC0 => dma.*[1].setDmadad(value),
+            0xC4 => dma.*[1].setDmacnt(value),
+
+            0xC8 => dma.*[2].setDmasad(value),
+            0xCC => dma.*[2].setDmadad(value),
+            0xD0 => dma.*[2].setDmacnt(value),
+
+            0xD4 => dma.*[3].setDmasad(value),
+            0xD8 => dma.*[3].setDmadad(value),
+            0xDC => dma.*[3].setDmacnt(value),
+            else => log.warn("Tried to write 0x{X:0>8}{} to 0x{X:0>8}", .{ value, T, addr }),
+        },
+        u16 => switch (byte_addr) {
+            0xB0, 0xB2 => dma.*[0].setDmasad(subset(u32, u16, byte_addr, dma.*[0].sad, value)),
+            0xB4, 0xB6 => dma.*[0].setDmadad(subset(u32, u16, byte_addr, dma.*[0].dad, value)),
+            0xB8 => dma.*[0].setDmacntL(value),
+            0xBA => dma.*[0].setDmacntH(value),
+
+            0xBC, 0xBE => dma.*[1].setDmasad(subset(u32, u16, byte_addr, dma.*[1].sad, value)),
+            0xC0, 0xC2 => dma.*[1].setDmadad(subset(u32, u16, byte_addr, dma.*[1].dad, value)),
+            0xC4 => dma.*[1].setDmacntL(value),
+            0xC6 => dma.*[1].setDmacntH(value),
+
+            0xC8, 0xCA => dma.*[2].setDmasad(subset(u32, u16, byte_addr, dma.*[2].sad, value)),
+            0xCC, 0xCE => dma.*[2].setDmadad(subset(u32, u16, byte_addr, dma.*[2].dad, value)),
+            0xD0 => dma.*[2].setDmacntL(value),
+            0xD2 => dma.*[2].setDmacntH(value),
+
+            0xD4, 0xD6 => dma.*[3].setDmasad(subset(u32, u16, byte_addr, dma.*[3].sad, value)),
+            0xD8, 0xDA => dma.*[3].setDmadad(subset(u32, u16, byte_addr, dma.*[3].dad, value)),
+            0xDC => dma.*[3].setDmacntL(value),
+            0xDE => dma.*[3].setDmacntH(value),
+            else => log.warn("Tried to write 0x{X:0>4}{} to 0x{X:0>8}", .{ value, T, addr }),
+        },
+        u8 => switch (byte_addr) {
+            0xB0, 0xB1, 0xB2, 0xB3 => dma.*[0].setDmasad(subset(u32, u8, byte_addr, dma.*[0].sad, value)),
+            0xB4, 0xB5, 0xB6, 0xB7 => dma.*[0].setDmadad(subset(u32, u8, byte_addr, dma.*[0].dad, value)),
+            0xB8, 0xB9 => dma.*[0].setDmacntL(subset(u16, u8, byte_addr, dma.*[0].word_count, value)),
+            0xBA, 0xBB => dma.*[0].setDmacntH(subset(u16, u8, byte_addr, dma.*[0].cnt.raw, value)),
+
+            0xBC, 0xBD, 0xBE, 0xBF => dma.*[1].setDmasad(subset(u32, u8, byte_addr, dma.*[1].sad, value)),
+            0xC0, 0xC1, 0xC2, 0xC3 => dma.*[1].setDmadad(subset(u32, u8, byte_addr, dma.*[1].dad, value)),
+            0xC4, 0xC5 => dma.*[1].setDmacntL(subset(u16, u8, byte_addr, dma.*[1].word_count, value)),
+            0xC6, 0xC7 => dma.*[1].setDmacntH(subset(u16, u8, byte_addr, dma.*[1].cnt.raw, value)),
+
+            0xC8, 0xC9, 0xCA, 0xCB => dma.*[2].setDmasad(subset(u32, u8, byte_addr, dma.*[2].sad, value)),
+            0xCC, 0xCD, 0xCE, 0xCF => dma.*[2].setDmadad(subset(u32, u8, byte_addr, dma.*[2].dad, value)),
+            0xD0, 0xD1 => dma.*[2].setDmacntL(subset(u16, u8, byte_addr, dma.*[2].word_count, value)),
+            0xD2, 0xD3 => dma.*[2].setDmacntH(subset(u16, u8, byte_addr, dma.*[2].cnt.raw, value)),
+
+            0xD4, 0xD5, 0xD6, 0xD7 => dma.*[3].setDmasad(subset(u32, u8, byte_addr, dma.*[3].sad, value)),
+            0xD8, 0xD9, 0xDA, 0xDB => dma.*[3].setDmadad(subset(u32, u8, byte_addr, dma.*[3].dad, value)),
+            0xDC, 0xDD => dma.*[3].setDmacntL(subset(u16, u8, byte_addr, dma.*[3].word_count, value)),
+            0xDE, 0xDF => dma.*[3].setDmacntH(subset(u16, u8, byte_addr, dma.*[3].cnt.raw, value)),
+            else => log.warn("Tried to write 0x{X:0>2}{} to 0x{X:0>8}", .{ value, T, addr }),
+        },
+        else => @compileError("DMA: Unsupported write width"),
+    }
+}
+
+fn warn(comptime format: []const u8, args: anytype) u0 {
+    log.warn(format, args);
+    return 0;
+}
+
+/// Function that creates a DMAController. Determines unique DMA Controller behaiour at compile-time
+fn Controller(comptime id: u2) type {
+    return struct {
+        const Self = @This();
+
+        const sad_mask: u32 = if (id == 0) 0x07FF_FFFF else 0x0FFF_FFFF;
+        const dad_mask: u32 = if (id != 3) 0x07FF_FFFF else 0x0FFF_FFFF;
+        const WordCount = if (id == 3) u16 else u14;
+
+        /// Write-only. The first address in a DMA transfer. (DMASAD)
+        /// Note: use writeSrc instead of manipulating src_addr directly
+        sad: u32 = 0x0000_0000,
+        /// Write-only. The final address in a DMA transffer. (DMADAD)
+        /// Note: Use writeDst instead of manipulatig dst_addr directly
+        dad: u32 = 0x0000_0000,
+        /// Write-only. The Word Count for the DMA Transfer (DMACNT_L)
+        word_count: WordCount = 0,
+        /// Read / Write. DMACNT_H
+        /// Note: Use writeControl instead of manipulating cnt directly.
+        cnt: DmaCnt = .{ .raw = 0x0000 },
+
+        /// Internal. The last successfully read value
+        data_latch: u32 = 0x0000_0000,
+        /// Internal. Currrent Source Address
+        sad_latch: u32 = 0x0000_0000,
+        /// Internal. Current Destination Address
+        dad_latch: u32 = 0x0000_0000,
+        /// Internal. Word Count
+        _word_count: WordCount = 0,
+
+        /// Some DMA Transfers are enabled during Hblank / VBlank and / or
+        /// have delays. Thefore bit 15 of DMACNT isn't actually something
+        /// we can use to control when we do or do not execute a step in a DMA Transfer
+        in_progress: bool = false,
+
+        pub fn reset(self: *Self) void {
+            self.* = Self.init();
+        }
+
+        pub fn setDmasad(self: *Self, addr: u32) void {
+            self.sad = addr & sad_mask;
+        }
+
+        pub fn setDmadad(self: *Self, addr: u32) void {
+            self.dad = addr & dad_mask;
+        }
+
+        pub fn setDmacntL(self: *Self, halfword: u16) void {
+            self.word_count = @truncate(halfword);
+        }
+
+        pub fn dmacntH(self: *const Self) u16 {
+            return self.cnt.raw & if (id == 3) 0xFFE0 else 0xF7E0;
+        }
+
+        pub fn setDmacntH(self: *Self, halfword: u16) void {
+            const new = DmaCnt{ .raw = halfword };
+
+            if (!self.cnt.enabled.read() and new.enabled.read()) {
+                // Reload Internals on Rising Edge.
+                self.sad_latch = self.sad;
+                self.dad_latch = self.dad;
+                self._word_count = if (self.word_count == 0) std.math.maxInt(WordCount) else self.word_count;
+
+                // Only a Start Timing of 00 has a DMA Transfer immediately begin
+                self.in_progress = new.start_timing.read() == 0b00;
+
+                // this is just for debug purposes
+                const start_timing: Kind = @enumFromInt(new.start_timing.read());
+
+                switch (start_timing) {
+                    .immediate, .vblank => {},
+                    else => log.err("TODO: Implement DMA({}) {s} mode", .{ id, @tagName(start_timing) }),
+                }
+
+                log.debug("configured {s} transfer from 0x{X:0>8} -> 0x{X:0>8} ({} words) for DMA{}", .{ @tagName(start_timing), self.sad_latch, self.dad_latch, self._word_count, id });
+            }
+
+            self.cnt.raw = halfword;
+        }
+
+        pub fn setDmacnt(self: *Self, word: u32) void {
+            self.setDmacntL(@truncate(word));
+            self.setDmacntH(@truncate(word >> 16));
+        }
+
+        pub fn step(self: *Self, cpu: *System.Arm7tdmi) void {
+            const bus_ptr: *System.Bus7 = @ptrCast(@alignCast(cpu.bus.ptr));
+
+            const is_fifo = (id == 1 or id == 2) and self.cnt.start_timing.read() == 0b11;
+            const sad_adj: Adjustment = @enumFromInt(self.cnt.sad_adj.read());
+            const dad_adj: Adjustment = if (is_fifo) .Fixed else @enumFromInt(self.cnt.dad_adj.read());
+
+            const transfer_type = is_fifo or self.cnt.transfer_type.read();
+            const offset: u32 = if (transfer_type) @sizeOf(u32) else @sizeOf(u16);
+
+            const mask = if (transfer_type) ~@as(u32, 3) else ~@as(u32, 1);
+            const sad_addr = self.sad_latch & mask;
+            const dad_addr = self.dad_latch & mask;
+
+            if (transfer_type) {
+                if (sad_addr >= 0x0200_0000) self.data_latch = cpu.bus.read(u32, sad_addr);
+                cpu.bus.write(u32, dad_addr, self.data_latch);
+            } else {
+                if (sad_addr >= 0x0200_0000) {
+                    const value: u32 = cpu.bus.read(u16, sad_addr);
+                    self.data_latch = value << 16 | value;
+                }
+
+                cpu.bus.write(u16, dad_addr, @as(u16, @truncate(rotr(u32, self.data_latch, 8 * (dad_addr & 3)))));
+            }
+
+            switch (@as(u8, @truncate(sad_addr >> 24))) {
+                // according to fleroviux, DMAs with a source address in ROM misbehave
+                // the resultant behaviour is that the source address will increment despite what DMAXCNT says
+                0x08...0x0D => self.sad_latch +%= offset, // obscure behaviour
+                else => switch (sad_adj) {
+                    .Increment => self.sad_latch +%= offset,
+                    .Decrement => self.sad_latch -%= offset,
+                    .IncrementReload => log.err("{} is a prohibited adjustment on SAD", .{sad_adj}),
+                    .Fixed => {},
+                },
+            }
+
+            switch (dad_adj) {
+                .Increment, .IncrementReload => self.dad_latch +%= offset,
+                .Decrement => self.dad_latch -%= offset,
+                .Fixed => {},
+            }
+
+            self._word_count -= 1;
+
+            if (self._word_count == 0) {
+                if (self.cnt.irq.read()) {
+                    switch (id) {
+                        0 => bus_ptr.io.irq.dma0.set(),
+                        1 => bus_ptr.io.irq.dma1.set(),
+                        2 => bus_ptr.io.irq.dma2.set(),
+                        3 => bus_ptr.io.irq.dma3.set(),
+                    }
+
+                    handleInterrupt(.nds7, cpu);
+                }
+
+                // If we're not repeating, Fire the IRQs and disable the DMA
+                if (!self.cnt.repeat.read()) self.cnt.enabled.unset();
+
+                // We want to disable our internal enabled flag regardless of repeat
+                // because we only want to step A DMA that repeats during it's specific
+                // timing window
+                self.in_progress = false;
+            }
+        }
+
+        fn poll(self: *Self, comptime kind: Kind) void {
+            if (self.in_progress) return; // If there's an ongoing DMA Transfer, exit early
+
+            // No ongoing DMA Transfer, We want to check if we should repeat an existing one
+            // Determined by the repeat bit and whether the DMA is in the right start_timing
+
+            switch (kind) {
+                .vblank => self.in_progress = self.cnt.enabled.read() and self.cnt.start_timing.read() == 0b01,
+                .cartridge_slot, .immediate, .special => {},
+            }
+
+            // If we determined that the repeat bit is set (and now the Hblank / Vblank DMA is now in progress)
+            // Reload internal word count latch
+            // Reload internal DAD latch if we are in IncrementRelaod
+            if (self.in_progress) {
+                self._word_count = if (self.word_count == 0) std.math.maxInt(@TypeOf(self._word_count)) else self.word_count;
+                if (@as(Adjustment, @enumFromInt(self.cnt.dad_adj.read())) == .IncrementReload) self.dad_latch = self.dad;
+            }
+        }
+
+        pub fn requestAudio(self: *Self, _: u32) void {
+            comptime std.debug.assert(id == 1 or id == 2);
+            if (self.in_progress) return; // APU must wait their turn
+
+            // DMA May not be configured for handling DMAs
+            if (self.cnt.start_timing.read() != 0b11) return;
+
+            // We Assume the Repeat Bit is Set
+            // We Assume that DAD is set to 0x0400_00A0 or 0x0400_00A4 (fifo_addr)
+            // We Assume DMACNT_L is set to 4
+
+            // FIXME: Safe to just assume whatever DAD is set to is the FIFO Address?
+            // self.dad_latch = fifo_addr;
+            self.cnt.repeat.set();
+            self._word_count = 4;
+            self.in_progress = true;
+        }
+    };
+}
+
+pub fn onVblank(bus: *System.Bus7) void {
+    inline for (0..4) |i| bus.dma[i].poll(.vblank);
+}
+
+pub fn step(cpu: *System.Arm7tdmi) bool {
+    const bus: *System.Bus7 = @ptrCast(@alignCast(cpu.bus.ptr));
+
+    inline for (0..4) |i| {
+        if (bus.dma[i].in_progress) {
+            bus.dma[i].step(cpu);
+            return true;
+        }
+    }
+
+    return false;
+}
+
+const Adjustment = enum(u2) {
+    Increment = 0,
+    Decrement = 1,
+    Fixed = 2,
+    IncrementReload = 3,
+};
+
+const Kind = enum(u2) {
+    immediate = 0,
+    vblank,
+    cartridge_slot,
+    special,
+};

src/core/nds7/io.zig

@@ -3,6 +3,8 @@ const std = @import("std");
 const Bitfield = @import("bitfield").Bitfield;
 const Bit = @import("bitfield").Bit;
 
+const Ppu = @import("../ppu.zig").Ppu;
+
 const Bus = @import("Bus.zig");
 const SharedCtx = @import("../emu.zig").SharedCtx;
 const masks = @import("../io.zig").masks;
@@ -10,46 +12,52 @@ const masks = @import("../io.zig").masks;
 const IntEnable = @import("../io.zig").IntEnable;
 const IntRequest = @import("../io.zig").IntEnable;
 
+const dma = @import("dma.zig");
+
 const log = std.log.scoped(.nds7_io);
 
 pub const Io = struct {
     shr: *SharedCtx.Io,
 
-    /// Interrupt Master Enable
+    /// IME - Interrupt Master Enable
     /// Read/Write
     ime: bool = false,
 
-    /// Interrupt Enable
+    /// IE -  Interrupt Enable
     /// Read/Write
-    ///
-    /// Caller must cast the `u32` to either `nds7.IntEnable` or `nds9.IntEnable`
     ie: IntEnable = .{ .raw = 0x0000_0000 },
 
     /// IF - Interrupt Request
     /// Read/Write
-    ///
-    /// Caller must cast the `u32` to either `nds7.IntRequest` or `nds9.IntRequest`
     irq: IntRequest = .{ .raw = 0x0000_0000 },
 
-    /// Post Boot Flag
+    /// POSTFLG - Post Boot Flag
     /// Read/Write
-    ///
-    /// Caller must cast the `u8` to either `nds7.PostFlg` or `nds9.PostFlg`
     postflg: PostFlag = .in_progress,
 
+    /// HALTCNT - Low Power Mode Control
+    /// Read/Write
+    haltcnt: Haltcnt = .execute,
+
+    ppu: ?*Ppu.Io = null,
+
     pub fn init(io: *SharedCtx.Io) @This() {
         return .{ .shr = io };
     }
+
+    pub fn configure(self: *@This(), ppu: *Ppu) void {
+        self.ppu = &ppu.io;
+    }
 };
 
 pub fn read(bus: *const Bus, comptime T: type, address: u32) T {
     return switch (T) {
         u32 => switch (address) {
             // DMA Transfers
-            0x0400_00B0...0x0400_00DC => warn("TODO: Implement DMA", .{}),
+            0x0400_00B0...0x0400_00DC => dma.read(T, &bus.dma, address) orelse 0x000_0000,
 
             // Timers
-            0x0400_0100...0x0400_010C => warn("TODO: Implement Timer", .{}),
+            0x0400_0100...0x0400_010C => warn("TODO: impl timer", .{}),
 
             0x0400_0180 => bus.io.shr.ipc._nds7.sync.raw,
             0x0400_0208 => @intFromBool(bus.io.ime),
@@ -60,22 +68,27 @@ pub fn read(bus: *const Bus, comptime T: type, address: u32) T {
             else => warn("unexpected: read(T: {}, addr: 0x{X:0>8}) {} ", .{ T, address, T }),
         },
         u16 => switch (address) {
+            0x0400_0004 => bus.io.ppu.?.nds7.dispstat.raw,
             // DMA Transfers
-            0x0400_00B0...0x0400_00DE => warn("TODO: Implement DMA", .{}),
+            0x0400_00B0...0x0400_00DE => dma.read(T, &bus.dma, address) orelse 0x0000,
 
             // Timers
-            0x0400_0100...0x0400_010E => warn("TODO: Implement Timer", .{}),
+            0x0400_0100...0x0400_010E => warn("TODO: impl timer", .{}),
 
+            0x0400_0130 => bus.io.shr.keyinput.load(.Monotonic),
             0x0400_0180 => @truncate(bus.io.shr.ipc._nds7.sync.raw),
             0x0400_0184 => @truncate(bus.io.shr.ipc._nds7.cnt.raw),
             else => warn("unexpected: read(T: {}, addr: 0x{X:0>8}) {} ", .{ T, address, T }),
         },
         u8 => switch (address) {
             // DMA Transfers
-            0x0400_00B0...0x0400_00DF => warn("TODO: Implement DMA", .{}),
+            0x0400_00B0...0x0400_00DF => dma.read(T, &bus.dma, address) orelse 0x00,
 
             // Timers
-            0x0400_0100...0x0400_010F => warn("TODO: Implement Timer", .{}),
+            0x0400_0100...0x0400_010F => warn("TODO: impl timer", .{}),
+
+            // RTC
+            0x0400_0138 => warn("TODO: RTC read", .{}),
 
             0x0400_0240 => bus.vram.stat().raw,
             0x0400_0241 => bus.io.shr.wramcnt.raw,
@@ -91,10 +104,10 @@ pub fn write(bus: *Bus, comptime T: type, address: u32, value: T) void {
     switch (T) {
         u32 => switch (address) {
             // DMA Transfers
-            0x0400_00B0...0x0400_00DC => log.warn("TODO: Implement DMA", .{}),
+            0x0400_00B0...0x0400_00DC => dma.write(T, &bus.dma, address, value),
 
             // Timers
-            0x0400_0100...0x0400_010C => log.warn("TODO: Implement Timer", .{}),
+            0x0400_0100...0x0400_010C => log.warn("TODO: impl timer", .{}),
 
             0x0400_0180 => bus.io.shr.ipc.setIpcSync(.nds7, value),
             0x0400_0208 => bus.io.ime = value & 1 == 1,
@@ -105,25 +118,41 @@ pub fn write(bus: *Bus, comptime T: type, address: u32, value: T) void {
             else => log.warn("unexpected: write(T: {}, addr: 0x{X:0>8}, value: 0x{X:0>8})", .{ T, address, value }),
         },
         u16 => switch (address) {
+            0x0400_0004 => bus.io.ppu.?.nds7.dispstat.raw = value,
+
             // DMA Transfers
-            0x0400_00B0...0x0400_00DE => log.warn("TODO: Implement DMA", .{}),
+            0x0400_00B0...0x0400_00DE => dma.write(T, &bus.dma, address, value),
 
             // Timers
-            0x0400_0100...0x0400_010E => log.warn("TODO: Implement Timer", .{}),
+            0x0400_0100...0x0400_010E => log.warn("TODO: impl timer", .{}),
 
             0x0400_0180 => bus.io.shr.ipc.setIpcSync(.nds7, value),
             0x0400_0184 => bus.io.shr.ipc.setIpcFifoCnt(.nds7, value),
-            else => log.warn("unexpected: write(T: {}, addr: 0x{X:0>8}, value: 0x{X:0>8})", .{ T, address, value }),
+
+            0x0400_0208 => bus.io.ime = value & 1 == 1,
+            else => log.warn("unexpected: write(T: {}, addr: 0x{X:0>8}, value: 0x{X:0>4})", .{ T, address, value }),
         },
         u8 => switch (address) {
             // DMA Transfers
-            0x0400_00B0...0x0400_00DF => log.warn("TODO: Implement DMA", .{}),
+            0x0400_00B0...0x0400_00DF => dma.write(T, &bus.dma, address, value),
 
             // Timers
-            0x0400_0100...0x0400_010F => log.warn("TODO: Implement Timer", .{}),
+            0x0400_0100...0x0400_010F => log.warn("TODO: impl timer", .{}),
+
+            // RTC
+            0x0400_0138 => log.warn("TODO: RTC write", .{}),
 
             0x0400_0208 => bus.io.ime = value & 1 == 1,
-            else => log.warn("unexpected: write(T: {}, addr: 0x{X:0>8}, value: 0x{X:0>8})", .{ T, address, value }),
+
+            0x0400_0301 => switch ((value >> 6) & 0b11) {
+                0b00 => bus.io.haltcnt = .execute,
+                0b10 => bus.io.haltcnt = .halt,
+                else => |val| {
+                    const tag: Haltcnt = @enumFromInt(val);
+                    log.err("TODO: Implement {}", .{tag});
+                },
+            },
+            else => log.warn("unexpected: write(T: {}, addr: 0x{X:0>8}, value: 0x{X:0>2})", .{ T, address, value }),
         },
         else => @compileError(T ++ " is an unsupported bus write type"),
     }
@@ -140,4 +169,22 @@ pub const Vramstat = extern union {
     raw: u8,
 };
 
+const Haltcnt = enum(u2) {
+    execute = 0,
+    gba_mode,
+    halt,
+    sleep,
+};
+
 const PostFlag = enum(u8) { in_progress = 0, completed };
+
+pub const DmaCnt = extern union {
+    dad_adj: Bitfield(u16, 5, 2),
+    sad_adj: Bitfield(u16, 7, 2),
+    repeat: Bit(u16, 9),
+    transfer_type: Bit(u16, 10),
+    start_timing: Bitfield(u16, 12, 2),
+    irq: Bit(u16, 14),
+    enabled: Bit(u16, 15),
+    raw: u16,
+};

src/core/nds9/Bus.zig

@@ -8,6 +8,8 @@ const Wram = @import("../emu.zig").Wram;
 const Bios = @import("Bios.zig");
 const forceAlign = @import("../emu.zig").forceAlign;
 
+const Controllers = @import("dma.zig").Controllers;
+
 const Allocator = std.mem.Allocator;
 
 const Mode = enum { normal, debug };
@@ -18,8 +20,11 @@ const log = std.log.scoped(.nds9_bus);
 
 main: *[4 * MiB]u8,
 wram: *Wram,
+makeshift_palram: *[2 * KiB]u8,
 scheduler: *Scheduler,
 
+dma: Controllers = .{},
+
 io: io.Io,
 ppu: Ppu,
 bios: Bios,
@@ -31,6 +36,7 @@ pub fn init(allocator: Allocator, scheduler: *Scheduler, ctx: SharedCtx) !@This(
     return .{
         .main = ctx.main,
         .wram = ctx.wram,
+        .makeshift_palram = try allocator.create([2 * KiB]u8),
         .ppu = try Ppu.init(allocator, ctx.vram),
         .scheduler = scheduler,
         .io = io.Io.init(ctx.io),
@@ -42,6 +48,8 @@ pub fn init(allocator: Allocator, scheduler: *Scheduler, ctx: SharedCtx) !@This(
 pub fn deinit(self: *@This(), allocator: Allocator) void {
     self.ppu.deinit(allocator);
     self.bios.deinit(allocator);
+
+    allocator.destroy(self.makeshift_palram);
 }
 
 pub fn reset(_: *@This()) void {
@@ -69,12 +77,14 @@ fn _read(self: *@This(), comptime T: type, comptime mode: Mode, address: u32) T
     }
 
     return switch (aligned_addr) {
-        0x0200_0000...0x02FF_FFFF => readInt(T, self.main[aligned_addr & 0x003F_FFFF ..][0..byte_count]),
+        0x0200_0000...0x02FF_FFFF => readInt(T, self.main[aligned_addr & (4 * MiB - 1) ..][0..byte_count]),
         0x0300_0000...0x03FF_FFFF => self.wram.read(T, .nds9, aligned_addr),
         0x0400_0000...0x04FF_FFFF => io.read(self, T, aligned_addr),
+        0x0500_0000...0x05FF_FFFF => readInt(T, self.makeshift_palram[aligned_addr & (2 * KiB - 1) ..][0..@sizeOf(T)]),
         0x0600_0000...0x06FF_FFFF => self.ppu.vram.read(T, .nds9, aligned_addr),
+        0x0700_0000...0x07FF_FFFF => readInt(T, self.ppu.oam.buf[aligned_addr & (2 * KiB - 1) ..][0..byte_count]),
         0xFFFF_0000...0xFFFF_FFFF => self.bios.read(T, address),
-        else => warn("unexpected read: 0x{x:0>8} -> {}", .{ aligned_addr, T }),
+        else => warn("unexpected: read(T: {}, addr: 0x{X:0>8}) {} ", .{ T, address, T }),
     };
 }
 
@@ -99,12 +109,14 @@ fn _write(self: *@This(), comptime T: type, comptime mode: Mode, address: u32, v
     }
 
     switch (aligned_addr) {
-        0x0200_0000...0x02FF_FFFF => writeInt(T, self.main[aligned_addr & 0x003F_FFFF ..][0..byte_count], value),
+        0x0200_0000...0x02FF_FFFF => writeInt(T, self.main[aligned_addr & (4 * MiB - 1) ..][0..byte_count], value),
         0x0300_0000...0x03FF_FFFF => self.wram.write(T, .nds9, aligned_addr, value),
         0x0400_0000...0x04FF_FFFF => io.write(self, T, aligned_addr, value),
+        0x0500_0000...0x05FF_FFFF => writeInt(T, self.makeshift_palram[aligned_addr & (2 * KiB - 1) ..][0..@sizeOf(T)], value),
         0x0600_0000...0x06FF_FFFF => self.ppu.vram.write(T, .nds9, aligned_addr, value),
+        0x0700_0000...0x07FF_FFFF => writeInt(T, self.ppu.oam.buf[aligned_addr & (2 * KiB - 1) ..][0..@sizeOf(T)], value),
         0xFFFF_0000...0xFFFF_FFFF => self.bios.write(T, address, value),
-        else => log.warn("unexpected write: 0x{X:}{} -> 0x{X:0>8}", .{ value, T, aligned_addr }),
+        else => log.warn("unexpected: write(T: {}, addr: 0x{X:0>8}, value: 0x{X:0>8})", .{ T, address, value }),
     }
 }
 

src/core/nds9/Cp15.zig

@@ -2,10 +2,14 @@ const std = @import("std");
 
 const log = std.log.scoped(.cp15);
 
-control: u32 = 0x0005_2078,
+const panic_on_unimplemented: bool = false;
+
+control: u32 = 0x0001_2078,
 dtcm_size_base: u32 = 0x0300_000A,
 itcm_size_base: u32 = 0x0000_0020,
 
+wait_for_interrupt: bool = false,
+
 // Protection Unit
 // cache_bits_data_unified: u32 = 0x0000_0000,
 // cache_write_bufability: u32 = 0x0000_0000, // For Data Protection Regions
@@ -41,22 +45,57 @@ pub fn write(self: *@This(), op1: u3, cn: u4, cm: u4, op2: u3, value: u32) void
 
             self.control = (value & ~zeroes) | ones;
         },
+
+        0b000_0010_0000_000 => log.err("TODO: write to PU cachability bits (data/unified region)", .{}),
+        0b000_0010_0000_001 => log.err("TODO: write to PU cachability bits (instruction region)", .{}),
+        0b000_0011_0000_000 => log.err("TODO: write to PU cache write-bufferability bits (data protection region)", .{}),
+
+        0b000_0101_0000_000 => log.err("TODO: write to access permission protection region (data/unified)", .{}),
+        0b000_0101_0000_001 => log.err("TODO: write to access permission protection region (insruction)", .{}),
+        0b000_0101_0000_010 => log.err("TODO: write to extended access permission protection region (data/unified)", .{}),
+        0b000_0101_0000_011 => log.err("TODO: write to extended access permission protection region (insruction)", .{}),
+
+        0b000_0110_0000_000,
+        0b000_0110_0001_000,
+        0b000_0110_0010_000,
+        0b000_0110_0011_000,
+        0b000_0110_0100_000,
+        0b000_0110_0101_000,
+        0b000_0110_0110_000,
+        0b000_0110_0111_000,
+        => log.err("TODO: write to PU data/unified region #{}", .{cm}),
+
+        0b000_0110_0000_001,
+        0b000_0110_0001_001,
+        0b000_0110_0010_001,
+        0b000_0110_0011_001,
+        0b000_0110_0100_001,
+        0b000_0110_0101_001,
+        0b000_0110_0110_001,
+        0b000_0110_0111_001,
+        => log.err("TODO: write to PU instruction region #{}", .{cm}),
+
+        0b000_0111_0000_100 => self.wait_for_interrupt = true, // NDS9 Halt
+        0b000_0111_0101_000 => log.err("TODO: invalidate instruction cache", .{}),
+        0b000_0111_0110_000 => log.err("TODO: invalidate data cache", .{}),
+        0b000_0111_1010_100 => log.err("TODO: drain write buffer", .{}),
+
         0b000_1001_0001_000 => { // Data TCM Size / Base
             const zeroes: u32 = 0b00000000_00000000_00001111_11000001;
 
             self.dtcm_size_base = value & ~zeroes;
 
-            const size_shamt: u5 = blk: {
-                const size = self.dtcm_size_base >> 1 & 0x1F;
+            // const size_shamt: u5 = blk: {
+            //     const size = self.dtcm_size_base >> 1 & 0x1F;
 
-                if (size < 3) break :blk 3;
-                if (size > 23) break :blk 23;
+            //     if (size < 3) break :blk 3;
+            //     if (size > 23) break :blk 23;
 
-                break :blk @intCast(size);
-            };
+            //     break :blk @intCast(size);
+            // };
 
-            log.debug("DTCM Virtual Size: {}B", .{@as(u32, 0x200) << size_shamt});
-            log.debug("DTCM Region Base: 0x{X:0>8}", .{self.dtcm_size_base & 0xFFFF_F000});
+            // log.debug("DTCM Virtual Size: {}B", .{@as(u32, 0x200) << size_shamt});
+            // log.debug("DTCM Region Base: 0x{X:0>8}", .{self.dtcm_size_base & 0xFFFF_F000});
         },
         0b000_1001_0001_001 => { // Instruction TCM Size / Base
             const zeroes: u32 = 0b00000000_00000000_00001111_11000001;
@@ -64,18 +103,19 @@ pub fn write(self: *@This(), op1: u3, cn: u4, cm: u4, op2: u3, value: u32) void
 
             self.itcm_size_base = value & ~(zeroes | itcm_specific);
 
-            const size_shamt: u5 = blk: {
-                const size = self.dtcm_size_base >> 1 & 0x1F;
+            // const size_shamt: u5 = blk: {
+            //     const size = self.dtcm_size_base >> 1 & 0x1F;
 
-                if (size < 3) break :blk 3;
-                if (size > 23) break :blk 23;
+            //     if (size < 3) break :blk 3;
+            //     if (size > 23) break :blk 23;
 
-                break :blk @intCast(size);
-            };
+            //     break :blk @intCast(size);
+            // };
 
-            log.debug("ICTM Virtual Size: {}B", .{@as(u32, 0x200) << size_shamt});
-            log.debug("ICTM Region Base: 0x{X:0>8}", .{0x0000_0000});
+            // log.debug("ICTM Virtual Size: {}B", .{@as(u32, 0x200) << size_shamt});
+            // log.debug("ICTM Region Base: 0x{X:0>8}", .{0x0000_0000});
         },
+
         else => _ = panic("TODO: implement write to register {}, c{}, c{}, {}", .{ op1, cn, cm, op2 }),
     }
 }
@@ -97,6 +137,7 @@ pub fn reset(self: *@This()) void {
 
 fn panic(comptime format: []const u8, args: anytype) u32 {
     log.err(format, args);
-    // @panic("Coprocessor invariant broken");
+    if (panic_on_unimplemented) @panic("cp15 invariant broken");
+
     return 0;
 }

src/core/nds9/dma.zig

@@ -0,0 +1,384 @@
+const std = @import("std");
+
+const System = @import("../emu.zig").System;
+const DmaCnt = @import("io.zig").DmaCnt;
+
+const rotr = std.math.rotr;
+const shift = @import("../../util.zig").shift;
+const subset = @import("../../util.zig").subset;
+
+const handleInterrupt = @import("../emu.zig").handleInterrupt;
+
+const log = std.log.scoped(.nds9_dma_transfer);
+
+pub const Controllers = struct {
+    Controller(0) = Controller(0){},
+    Controller(1) = Controller(1){},
+    Controller(2) = Controller(2){},
+    Controller(3) = Controller(3){},
+};
+
+pub fn read(comptime T: type, dma: *const Controllers, addr: u32) ?T {
+    const byte_addr: u8 = @truncate(addr);
+
+    return switch (T) {
+        u32 => switch (byte_addr) {
+            0xB0, 0xB4 => null, // DMA0SAD, DMA0DAD,
+            0xB8 => @as(T, dma.*[0].dmacntH()) << 16, // DMA0CNT_L is write-only
+            0xBC, 0xC0 => null, // DMA1SAD, DMA1DAD
+            0xC4 => @as(T, dma.*[1].dmacntH()) << 16, // DMA1CNT_L is write-only
+            0xC8, 0xCC => null, // DMA2SAD, DMA2DAD
+            0xD0 => @as(T, dma.*[2].dmacntH()) << 16, // DMA2CNT_L is write-only
+            0xD4, 0xD8 => null, // DMA3SAD, DMA3DAD
+            0xDC => @as(T, dma.*[3].dmacntH()) << 16, // DMA3CNT_L is write-only
+            else => warn("unaligned {} read from 0x{X:0>8}", .{ T, addr }),
+        },
+        u16 => switch (byte_addr) {
+            0xB0, 0xB2, 0xB4, 0xB6 => null, // DMA0SAD, DMA0DAD
+            0xB8 => 0x0000, // DMA0CNT_L, suite.gba expects 0x0000 instead of 0xDEAD
+            0xBA => dma.*[0].dmacntH(),
+
+            0xBC, 0xBE, 0xC0, 0xC2 => null, // DMA1SAD, DMA1DAD
+            0xC4 => 0x0000, // DMA1CNT_L
+            0xC6 => dma.*[1].dmacntH(),
+
+            0xC8, 0xCA, 0xCC, 0xCE => null, // DMA2SAD, DMA2DAD
+            0xD0 => 0x0000, // DMA2CNT_L
+            0xD2 => dma.*[2].dmacntH(),
+
+            0xD4, 0xD6, 0xD8, 0xDA => null, // DMA3SAD, DMA3DAD
+            0xDC => 0x0000, // DMA3CNT_L
+            0xDE => dma.*[3].dmacntH(),
+            else => warn("unaligned {} read from 0x{X:0>8}", .{ T, addr }),
+        },
+        u8 => switch (byte_addr) {
+            0xB0...0xB7 => null, // DMA0SAD, DMA0DAD
+            0xB8, 0xB9 => 0x00, // DMA0CNT_L
+            0xBA, 0xBB => @truncate(dma.*[0].dmacntH() >> shift(u16, byte_addr)),
+
+            0xBC...0xC3 => null, // DMA1SAD, DMA1DAD
+            0xC4, 0xC5 => 0x00, // DMA1CNT_L
+            0xC6, 0xC7 => @truncate(dma.*[1].dmacntH() >> shift(u16, byte_addr)),
+
+            0xC8...0xCF => null, // DMA2SAD, DMA2DAD
+            0xD0, 0xD1 => 0x00, // DMA2CNT_L
+            0xD2, 0xD3 => @truncate(dma.*[2].dmacntH() >> shift(u16, byte_addr)),
+
+            0xD4...0xDB => null, // DMA3SAD, DMA3DAD
+            0xDC, 0xDD => 0x00, // DMA3CNT_L
+            0xDE, 0xDF => @truncate(dma.*[3].dmacntH() >> shift(u16, byte_addr)),
+            else => warn("unexpected {} read from 0x{X:0>8}", .{ T, addr }),
+        },
+        else => @compileError("DMA: Unsupported read width"),
+    };
+}
+
+pub fn write(comptime T: type, dma: *Controllers, addr: u32, value: T) void {
+    const byte_addr: u8 = @truncate(addr);
+
+    switch (T) {
+        u32 => switch (byte_addr) {
+            0xB0 => dma.*[0].setDmasad(value),
+            0xB4 => dma.*[0].setDmadad(value),
+            0xB8 => dma.*[0].setDmacnt(value),
+
+            0xBC => dma.*[1].setDmasad(value),
+            0xC0 => dma.*[1].setDmadad(value),
+            0xC4 => dma.*[1].setDmacnt(value),
+
+            0xC8 => dma.*[2].setDmasad(value),
+            0xCC => dma.*[2].setDmadad(value),
+            0xD0 => dma.*[2].setDmacnt(value),
+
+            0xD4 => dma.*[3].setDmasad(value),
+            0xD8 => dma.*[3].setDmadad(value),
+            0xDC => dma.*[3].setDmacnt(value),
+            else => log.warn("Tried to write 0x{X:0>8}{} to 0x{X:0>8}", .{ value, T, addr }),
+        },
+        u16 => switch (byte_addr) {
+            0xB0, 0xB2 => dma.*[0].setDmasad(subset(u32, u16, byte_addr, dma.*[0].sad, value)),
+            0xB4, 0xB6 => dma.*[0].setDmadad(subset(u32, u16, byte_addr, dma.*[0].dad, value)),
+            0xB8 => dma.*[0].setDmacntL(value),
+            0xBA => dma.*[0].setDmacntH(value),
+
+            0xBC, 0xBE => dma.*[1].setDmasad(subset(u32, u16, byte_addr, dma.*[1].sad, value)),
+            0xC0, 0xC2 => dma.*[1].setDmadad(subset(u32, u16, byte_addr, dma.*[1].dad, value)),
+            0xC4 => dma.*[1].setDmacntL(value),
+            0xC6 => dma.*[1].setDmacntH(value),
+
+            0xC8, 0xCA => dma.*[2].setDmasad(subset(u32, u16, byte_addr, dma.*[2].sad, value)),
+            0xCC, 0xCE => dma.*[2].setDmadad(subset(u32, u16, byte_addr, dma.*[2].dad, value)),
+            0xD0 => dma.*[2].setDmacntL(value),
+            0xD2 => dma.*[2].setDmacntH(value),
+
+            0xD4, 0xD6 => dma.*[3].setDmasad(subset(u32, u16, byte_addr, dma.*[3].sad, value)),
+            0xD8, 0xDA => dma.*[3].setDmadad(subset(u32, u16, byte_addr, dma.*[3].dad, value)),
+            0xDC => dma.*[3].setDmacntL(value),
+            0xDE => dma.*[3].setDmacntH(value),
+            else => log.warn("Tried to write 0x{X:0>4}{} to 0x{X:0>8}", .{ value, T, addr }),
+        },
+        u8 => switch (byte_addr) {
+            0xB0, 0xB1, 0xB2, 0xB3 => dma.*[0].setDmasad(subset(u32, u8, byte_addr, dma.*[0].sad, value)),
+            0xB4, 0xB5, 0xB6, 0xB7 => dma.*[0].setDmadad(subset(u32, u8, byte_addr, dma.*[0].dad, value)),
+            0xB8, 0xB9 => dma.*[0].setDmacntL(subset(u16, u8, byte_addr, @as(u16, @truncate(dma.*[0].word_count)), value)), // FIXME: How wrong is this? lol
+            0xBA, 0xBB => dma.*[0].setDmacntH(subset(u16, u8, byte_addr, dma.*[0].cnt.raw, value)),
+
+            0xBC, 0xBD, 0xBE, 0xBF => dma.*[1].setDmasad(subset(u32, u8, byte_addr, dma.*[1].sad, value)),
+            0xC0, 0xC1, 0xC2, 0xC3 => dma.*[1].setDmadad(subset(u32, u8, byte_addr, dma.*[1].dad, value)),
+            0xC4, 0xC5 => dma.*[1].setDmacntL(subset(u16, u8, byte_addr, @as(u16, @truncate(dma.*[1].word_count)), value)),
+            0xC6, 0xC7 => dma.*[1].setDmacntH(subset(u16, u8, byte_addr, dma.*[1].cnt.raw, value)),
+
+            0xC8, 0xC9, 0xCA, 0xCB => dma.*[2].setDmasad(subset(u32, u8, byte_addr, dma.*[2].sad, value)),
+            0xCC, 0xCD, 0xCE, 0xCF => dma.*[2].setDmadad(subset(u32, u8, byte_addr, dma.*[2].dad, value)),
+            0xD0, 0xD1 => dma.*[2].setDmacntL(subset(u16, u8, byte_addr, @as(u16, @truncate(dma.*[2].word_count)), value)),
+            0xD2, 0xD3 => dma.*[2].setDmacntH(subset(u16, u8, byte_addr, dma.*[2].cnt.raw, value)),
+
+            0xD4, 0xD5, 0xD6, 0xD7 => dma.*[3].setDmasad(subset(u32, u8, byte_addr, dma.*[3].sad, value)),
+            0xD8, 0xD9, 0xDA, 0xDB => dma.*[3].setDmadad(subset(u32, u8, byte_addr, dma.*[3].dad, value)),
+            0xDC, 0xDD => dma.*[3].setDmacntL(subset(u16, u8, byte_addr, @as(u16, @truncate(dma.*[3].word_count)), value)),
+            0xDE, 0xDF => dma.*[3].setDmacntH(subset(u16, u8, byte_addr, dma.*[3].cnt.raw, value)),
+            else => log.warn("Tried to write 0x{X:0>2}{} to 0x{X:0>8}", .{ value, T, addr }),
+        },
+        else => @compileError("DMA: Unsupported write width"),
+    }
+}
+
+fn warn(comptime format: []const u8, args: anytype) u0 {
+    log.warn(format, args);
+    return 0;
+}
+
+/// Function that creates a DMAController. Determines unique DMA Controller behaiour at compile-time
+fn Controller(comptime id: u2) type {
+    return struct {
+        const Self = @This();
+
+        const sad_mask: u32 = 0x0FFF_FFFE;
+        const dad_mask: u32 = 0x0FFF_FFFE;
+        const WordCount = u21;
+
+        /// Write-only. The first address in a DMA transfer. (DMASAD)
+        /// Note: use writeSrc instead of manipulating src_addr directly
+        sad: u32 = 0x0000_0000,
+        /// Write-only. The final address in a DMA transffer. (DMADAD)
+        /// Note: Use writeDst instead of manipulatig dst_addr directly
+        dad: u32 = 0x0000_0000,
+        /// Write-only. The Word Count for the DMA Transfer (DMACNT_L)
+        word_count: WordCount = 0,
+        /// Read / Write. DMACNT_H
+        /// Note: Use writeControl instead of manipulating cnt directly.
+        cnt: DmaCnt = .{ .raw = 0x0000 },
+
+        /// Internal. The last successfully read value
+        data_latch: u32 = 0x0000_0000,
+        /// Internal. Currrent Source Address
+        sad_latch: u32 = 0x0000_0000,
+        /// Internal. Current Destination Address
+        dad_latch: u32 = 0x0000_0000,
+        /// Internal. Word Count
+        _word_count: WordCount = 0,
+
+        /// Some DMA Transfers are enabled during Hblank / VBlank and / or
+        /// have delays. Thefore bit 15 of DMACNT isn't actually something
+        /// we can use to control when we do or do not execute a step in a DMA Transfer
+        in_progress: bool = false,
+
+        pub fn reset(self: *Self) void {
+            self.* = Self.init();
+        }
+
+        pub fn setDmasad(self: *Self, addr: u32) void {
+            self.sad = addr & sad_mask;
+        }
+
+        pub fn setDmadad(self: *Self, addr: u32) void {
+            self.dad = addr & dad_mask;
+        }
+
+        pub fn setDmacntL(self: *Self, halfword: u16) void {
+            self.word_count = halfword;
+        }
+
+        pub fn dmacntH(self: *const Self) u16 {
+            return self.cnt.raw & if (id == 3) 0xFFE0 else 0xF7E0;
+        }
+
+        pub fn setDmacntH(self: *Self, halfword: u16) void {
+            const new = DmaCnt{ .raw = halfword };
+
+            if (!self.cnt.enabled.read() and new.enabled.read()) {
+                // Reload Internals on Rising Edge.
+                self.sad_latch = self.sad;
+                self.dad_latch = self.dad;
+                self._word_count = if (self.word_count == 0) std.math.maxInt(WordCount) else self.word_count;
+
+                // Only a Start Timing of 00 has a DMA Transfer immediately begin
+                self.in_progress = new.start_timing.read() == 0b00;
+
+                // this is just for debug purposes
+                const start_timing: Kind = @enumFromInt(new.start_timing.read());
+
+                switch (start_timing) {
+                    .immediate, .vblank, .hblank => {},
+                    else => log.err("TODO: Implement DMA({}) {s} mode", .{ id, @tagName(start_timing) }),
+                }
+
+                log.debug("configured {s} transfer from 0x{X:0>8} -> 0x{X:0>8} ({} words) for DMA{}", .{ @tagName(start_timing), self.sad_latch, self.dad_latch, self._word_count, id });
+            }
+
+            self.cnt.raw = halfword;
+        }
+
+        pub fn setDmacnt(self: *Self, word: u32) void {
+            self.setDmacntL(@truncate(word));
+            self.setDmacntH(@truncate(word >> 16));
+        }
+
+        pub fn step(self: *Self, cpu: *System.Arm946es) void {
+            const bus_ptr: *System.Bus7 = @ptrCast(@alignCast(cpu.bus.ptr));
+
+            const is_fifo = (id == 1 or id == 2) and self.cnt.start_timing.read() == 0b11;
+            const sad_adj: Adjustment = @enumFromInt(self.cnt.sad_adj.read());
+            const dad_adj: Adjustment = if (is_fifo) .Fixed else @enumFromInt(self.cnt.dad_adj.read());
+
+            const transfer_type = is_fifo or self.cnt.transfer_type.read();
+            const offset: u32 = if (transfer_type) @sizeOf(u32) else @sizeOf(u16);
+
+            const mask = if (transfer_type) ~@as(u32, 3) else ~@as(u32, 1);
+            const sad_addr = self.sad_latch & mask;
+            const dad_addr = self.dad_latch & mask;
+
+            if (transfer_type) {
+                if (sad_addr >= 0x0200_0000) self.data_latch = cpu.bus.read(u32, sad_addr);
+                cpu.bus.write(u32, dad_addr, self.data_latch);
+            } else {
+                if (sad_addr >= 0x0200_0000) {
+                    const value: u32 = cpu.bus.read(u16, sad_addr);
+                    self.data_latch = value << 16 | value;
+                }
+
+                cpu.bus.write(u16, dad_addr, @as(u16, @truncate(rotr(u32, self.data_latch, 8 * (dad_addr & 3)))));
+            }
+
+            switch (@as(u8, @truncate(sad_addr >> 24))) {
+                // according to fleroviux, DMAs with a source address in ROM misbehave
+                // the resultant behaviour is that the source address will increment despite what DMAXCNT says
+                0x08...0x0D => self.sad_latch +%= offset, // obscure behaviour
+                else => switch (sad_adj) {
+                    .Increment => self.sad_latch +%= offset,
+                    .Decrement => self.sad_latch -%= offset,
+                    .IncrementReload => log.err("{} is a prohibited adjustment on SAD", .{sad_adj}),
+                    .Fixed => {},
+                },
+            }
+
+            switch (dad_adj) {
+                .Increment, .IncrementReload => self.dad_latch +%= offset,
+                .Decrement => self.dad_latch -%= offset,
+                .Fixed => {},
+            }
+
+            self._word_count -= 1;
+
+            if (self._word_count == 0) {
+                if (self.cnt.irq.read()) {
+                    switch (id) {
+                        0 => bus_ptr.io.irq.dma0.set(),
+                        1 => bus_ptr.io.irq.dma1.set(),
+                        2 => bus_ptr.io.irq.dma2.set(),
+                        3 => bus_ptr.io.irq.dma3.set(),
+                    }
+
+                    handleInterrupt(.nds9, cpu);
+                }
+
+                // If we're not repeating, Fire the IRQs and disable the DMA
+                if (!self.cnt.repeat.read()) self.cnt.enabled.unset();
+
+                // We want to disable our internal enabled flag regardless of repeat
+                // because we only want to step A DMA that repeats during it's specific
+                // timing window
+                self.in_progress = false;
+            }
+        }
+
+        fn poll(self: *Self, comptime kind: Kind) void {
+            if (self.in_progress) return; // If there's an ongoing DMA Transfer, exit early
+
+            // No ongoing DMA Transfer, We want to check if we should repeat an existing one
+            // Determined by the repeat bit and whether the DMA is in the right start_timing
+
+            switch (kind) {
+                .vblank => self.in_progress = self.cnt.enabled.read() and self.cnt.start_timing.read() == 0b01,
+                .hblank => self.in_progress = self.cnt.enabled.read() and self.cnt.start_timing.read() == 0b10,
+                else => {},
+            }
+
+            // If we determined that the repeat bit is set (and now the Hblank / Vblank DMA is now in progress)
+            // Reload internal word count latch
+            // Reload internal DAD latch if we are in IncrementRelaod
+            if (self.in_progress) {
+                self._word_count = if (self.word_count == 0) std.math.maxInt(@TypeOf(self._word_count)) else self.word_count;
+                if (@as(Adjustment, @enumFromInt(self.cnt.dad_adj.read())) == .IncrementReload) self.dad_latch = self.dad;
+            }
+        }
+
+        pub fn requestAudio(self: *Self, _: u32) void {
+            comptime std.debug.assert(id == 1 or id == 2);
+            if (self.in_progress) return; // APU must wait their turn
+
+            // DMA May not be configured for handling DMAs
+            if (self.cnt.start_timing.read() != 0b11) return;
+
+            // We Assume the Repeat Bit is Set
+            // We Assume that DAD is set to 0x0400_00A0 or 0x0400_00A4 (fifo_addr)
+            // We Assume DMACNT_L is set to 4
+
+            // FIXME: Safe to just assume whatever DAD is set to is the FIFO Address?
+            // self.dad_latch = fifo_addr;
+            self.cnt.repeat.set();
+            self._word_count = 4;
+            self.in_progress = true;
+        }
+    };
+}
+
+pub fn onVblank(bus: *System.Bus9) void {
+    inline for (0..4) |i| bus.dma[i].poll(.vblank);
+}
+
+pub fn onHblank(bus: *System.Bus9) void {
+    inline for (0..4) |i| bus.dma[i].poll(.hblank);
+}
+
+pub fn step(cpu: *System.Arm946es) bool {
+    const bus: *System.Bus9 = @ptrCast(@alignCast(cpu.bus.ptr));
+
+    inline for (0..4) |i| {
+        if (bus.dma[i].in_progress) {
+            bus.dma[i].step(cpu);
+            return true;
+        }
+    }
+
+    return false;
+}
+
+const Adjustment = enum(u2) {
+    Increment = 0,
+    Decrement = 1,
+    Fixed = 2,
+    IncrementReload = 3,
+};
+
+const Kind = enum(u3) {
+    immediate = 0,
+    vblank,
+    hblank,
+
+    display_start_sync,
+    main_mem_display,
+    cartridge_slot,
+    pak_slot,
+    geo_cmd_fifo,
+};

src/core/nds9/io.zig

@@ -10,12 +10,16 @@ const masks = @import("../io.zig").masks;
 const IntEnable = @import("../io.zig").IntEnable;
 const IntRequest = @import("../io.zig").IntEnable;
 
+const dma = @import("dma.zig");
+
 const sext = @import("../../util.zig").sext;
 const shift = @import("../../util.zig").shift;
 
 const log = std.log.scoped(.nds9_io);
 
 pub const Io = struct {
+    const fill_len = 0x10 * @sizeOf(u32);
+
     shr: *SharedCtx.Io,
 
     /// Interrupt Master Enable
@@ -34,17 +38,13 @@ pub const Io = struct {
     /// Caller must cast the `u32` to either `nds7.IntRequest` or `nds9.IntRequest`
     irq: IntRequest = .{ .raw = 0x0000_0000 },
 
-    /// POWCNT1 - Graphics Power Control
-    /// Read / Write
-    powcnt: PowCnt = .{ .raw = 0x0000_0000 },
-
-    // Read Only
-    keyinput: AtomicKeyInput = .{},
-
     /// DS Maths
     div: Divisor = .{},
     sqrt: SquareRootUnit = .{},
 
+    // TODO: move somewhere else?
+    dma_fill: [fill_len]u8 = [_]u8{0} ** fill_len,
+
     pub fn init(io: *SharedCtx.Io) @This() {
         return .{ .shr = io };
     }
@@ -53,23 +53,49 @@ pub const Io = struct {
 pub fn read(bus: *const Bus, comptime T: type, address: u32) T {
     return switch (T) {
         u32 => switch (address) {
+            // DMA Transfers
+            0x0400_00B0...0x0400_00DC => dma.read(T, &bus.dma, address) orelse 0x0000_0000,
+            0x0400_00E0...0x0400_00EC => std.mem.readIntLittle(T, bus.io.dma_fill[address & 0xF ..][0..@sizeOf(T)]),
+
+            // Timers
+            0x0400_0100...0x0400_010C => warn("TODO: impl timer", .{}),
+
             0x0400_0180 => bus.io.shr.ipc._nds9.sync.raw,
             0x0400_0208 => @intFromBool(bus.io.ime),
             0x0400_0210 => bus.io.ie.raw,
             0x0400_0214 => bus.io.irq.raw,
 
+            // zig fmt: off
+            0x0400_0240 => @as(u32, bus.ppu.vram.io.cnt_d.raw) << 24
+                | @as(u32, bus.ppu.vram.io.cnt_c.raw) << 16
+                | @as(u32, bus.ppu.vram.io.cnt_b.raw) << 8
+                | bus.ppu.vram.io.cnt_a.raw << 0,
+            // zig fmt: on
+
+            0x0400_0280 => bus.io.div.cnt.raw,
             0x0400_02A0, 0x0400_02A4 => @truncate(bus.io.div.result >> shift(u64, address)),
             0x0400_02A8, 0x0400_02AC => @truncate(bus.io.div.remainder >> shift(u64, address)),
             0x0400_02B4 => @truncate(bus.io.sqrt.result),
 
-            0x0400_4008 => 0x0000_0000, // Lets software know this is NOT a DSi
+            0x0400_1000 => bus.ppu.engines[1].dispcnt.raw,
 
             0x0410_0000 => bus.io.shr.ipc.recv(.nds9),
+
+            0x0400_4000, 0x0400_4008 => 0x0000_0000, // Lets software know this is NOT a DSi
             else => warn("unexpected: read(T: {}, addr: 0x{X:0>8}) {} ", .{ T, address, T }),
         },
         u16 => switch (address) {
-            0x0400_0004 => bus.ppu.io.dispstat.raw,
-            0x0400_0130 => bus.io.keyinput.load(.Monotonic),
+            0x0400_0006 => bus.ppu.io.nds9.vcount.raw,
+
+            // DMA Transfers
+            0x0400_00B0...0x0400_00DE => dma.read(T, &bus.dma, address) orelse 0x0000,
+            0x0400_00E0...0x0400_00EE => std.mem.readIntLittle(T, bus.io.dma_fill[address & 0xF ..][0..@sizeOf(T)]),
+
+            // Timers
+            0x0400_0100...0x0400_010E => warn("TODO: impl timer", .{}),
+
+            0x0400_0004 => bus.ppu.io.nds9.dispstat.raw,
+            0x0400_0130 => bus.io.shr.keyinput.load(.Monotonic),
 
             0x0400_0180 => @truncate(bus.io.shr.ipc._nds9.sync.raw),
             0x0400_0184 => @truncate(bus.io.shr.ipc._nds9.cnt.raw),
@@ -77,9 +103,32 @@ pub fn read(bus: *const Bus, comptime T: type, address: u32) T {
             0x0400_0280 => @truncate(bus.io.div.cnt.raw),
             0x0400_02B0 => @truncate(bus.io.sqrt.cnt.raw),
 
+            0x0400_1008 => bus.ppu.engines[1].bg[0].cnt.raw,
+            0x0400_100A => bus.ppu.engines[1].bg[1].cnt.raw,
+            0x0400_100C => bus.ppu.engines[1].bg[2].cnt.raw,
+            0x0400_100E => bus.ppu.engines[1].bg[3].cnt.raw,
+
+            0x0400_1010 => bus.ppu.engines[1].bg[0].hofs.raw,
+            0x0400_1012 => bus.ppu.engines[1].bg[0].vofs.raw,
+            0x0400_1014 => bus.ppu.engines[1].bg[1].hofs.raw,
+            0x0400_1016 => bus.ppu.engines[1].bg[1].vofs.raw,
+            0x0400_1018 => bus.ppu.engines[1].bg[2].hofs.raw,
+            0x0400_101A => bus.ppu.engines[1].bg[2].vofs.raw,
+            0x0400_101C => bus.ppu.engines[1].bg[3].hofs.raw,
+            0x0400_101E => bus.ppu.engines[1].bg[3].vofs.raw,
+
             else => warn("unexpected: read(T: {}, addr: 0x{X:0>8}) {} ", .{ T, address, T }),
         },
         u8 => switch (address) {
+            // DMA Transfers
+            0x0400_00B0...0x0400_00DF => dma.read(T, &bus.dma, address) orelse 0x00,
+            0x0400_00E0...0x0400_00EF => std.mem.readIntLittle(T, bus.io.dma_fill[address & 0xF ..][0..@sizeOf(T)]),
+
+            // Timers
+            0x0400_0100...0x0400_010F => warn("TODO: impl timer", .{}),
+
+            0x0400_0208 => @intFromBool(bus.io.ime),
+
             0x0400_4000 => 0x00, // Lets software know this is NOT a DSi
             else => warn("unexpected: read(T: {}, addr: 0x{X:0>8}) {} ", .{ T, address, T }),
         },
@@ -92,21 +141,70 @@ const subset = @import("../../util.zig").subset;
 pub fn write(bus: *Bus, comptime T: type, address: u32, value: T) void {
     switch (T) {
         u32 => switch (address) {
-            0x0400_0000 => bus.ppu.io.dispcnt_a.raw = value,
+            0x0400_0000 => bus.ppu.engines[0].dispcnt.raw = value,
+            0x0400_0004 => bus.ppu.io.nds9.dispstat.raw = @truncate(value),
+            0x0400_0008 => {
+                bus.ppu.engines[0].bg[0].cnt.raw = @truncate(value >> 0); // 0x0400_0008
+                bus.ppu.engines[0].bg[1].cnt.raw = @truncate(value >> 16); // 0x0400_000A
+            },
+            0x0400_000C => {
+                bus.ppu.engines[0].bg[2].cnt.raw = @truncate(value >> 0); // 0x0400_000A
+                bus.ppu.engines[0].bg[3].cnt.raw = @truncate(value >> 16); // 0x0400_000C
+            },
+            0x00400_0010 => {
+                bus.ppu.engines[0].bg[0].hofs.raw = @truncate(value >> 0); // 0x0400_0010
+                bus.ppu.engines[0].bg[0].vofs.raw = @truncate(value >> 16); // 0x0400_0012
+            },
+            0x00400_0014 => {
+                bus.ppu.engines[0].bg[1].hofs.raw = @truncate(value >> 0); // 0x0400_0014
+                bus.ppu.engines[0].bg[1].vofs.raw = @truncate(value >> 16); // 0x0400_0016
+            },
+            0x00400_0018 => {
+                bus.ppu.engines[0].bg[2].hofs.raw = @truncate(value >> 0); // 0x0400_0018
+                bus.ppu.engines[0].bg[2].vofs.raw = @truncate(value >> 16); // 0x0400_001A
+            },
+            0x00400_001C => {
+                bus.ppu.engines[0].bg[3].hofs.raw = @truncate(value >> 0); // 0x0400_001C
+                bus.ppu.engines[0].bg[3].vofs.raw = @truncate(value >> 16); // 0x0400_001E
+            },
+
+            // DMA Transfers
+            0x0400_00B0...0x0400_00DC => dma.write(T, &bus.dma, address, value),
+            0x0400_00E0...0x0400_00EC => std.mem.writeIntLittle(T, bus.io.dma_fill[address & 0xF ..][0..@sizeOf(T)], value),
+
+            // Timers
+            0x0400_0100...0x0400_010C => log.warn("TODO: impl timer", .{}),
+
             0x0400_0180 => bus.io.shr.ipc.setIpcSync(.nds9, value),
             0x0400_0184 => bus.io.shr.ipc.setIpcFifoCnt(.nds9, value),
             0x0400_0188 => bus.io.shr.ipc.send(.nds9, value),
 
+            0x0400_0208 => bus.io.ime = value & 1 == 1,
+            0x0400_0210 => bus.io.ie.raw = value,
+            0x0400_0214 => bus.io.irq.raw &= ~value,
+
             0x0400_0240 => {
                 bus.ppu.vram.io.cnt_a.raw = @truncate(value >> 0); // 0x0400_0240
                 bus.ppu.vram.io.cnt_b.raw = @truncate(value >> 8); // 0x0400_0241
                 bus.ppu.vram.io.cnt_c.raw = @truncate(value >> 16); // 0x0400_0242
                 bus.ppu.vram.io.cnt_d.raw = @truncate(value >> 24); // 0x0400_0243
+
+                bus.ppu.vram.update();
+            },
+            0x0400_0244 => {
+                bus.ppu.vram.io.cnt_e.raw = @truncate(value >> 0); // 0x0400_0244
+                bus.ppu.vram.io.cnt_f.raw = @truncate(value >> 8); // 0x0400_0245
+                bus.ppu.vram.io.cnt_g.raw = @truncate(value >> 16); // 0x0400_0246
+                bus.io.shr.wramcnt.raw = @truncate(value >> 24); // 0x0400_0247
+
+                bus.ppu.vram.update();
+                bus.wram.update(bus.io.shr.wramcnt);
             },
 
-            0x0400_0208 => bus.io.ime = value & 1 == 1,
-            0x0400_0210 => bus.io.ie.raw = value,
-            0x0400_0214 => bus.io.irq.raw &= ~value,
+            0x0400_0280 => {
+                bus.io.div.cnt.raw = value;
+                bus.io.div.schedule(bus.scheduler);
+            },
 
             0x0400_0290, 0x0400_0294 => {
                 bus.io.div.numerator = subset(u64, u32, address, bus.io.div.numerator, value);
@@ -118,16 +216,57 @@ pub fn write(bus: *Bus, comptime T: type, address: u32, value: T) void {
                 bus.io.div.schedule(bus.scheduler);
             },
 
+            0x0400_02B0 => {
+                bus.io.sqrt.cnt.raw = value;
+                bus.io.sqrt.schedule(bus.scheduler);
+            },
+
             0x0400_02B8, 0x0400_02BC => {
                 bus.io.sqrt.param = subset(u64, u32, address, bus.io.sqrt.param, value);
                 bus.io.sqrt.schedule(bus.scheduler);
             },
 
-            0x0400_0304 => bus.io.powcnt.raw = value,
+            // Engine B
+            0x0400_0304 => bus.ppu.io.powcnt.raw = value,
+
+            0x0400_1000 => bus.ppu.engines[1].dispcnt.raw = value,
+            0x0400_1008 => {
+                bus.ppu.engines[1].bg[0].cnt.raw = @truncate(value >> 0); // 0x0400_1008
+                bus.ppu.engines[1].bg[1].cnt.raw = @truncate(value >> 16); // 0x0400_100A
+            },
+            0x0400_100C => {
+                bus.ppu.engines[1].bg[2].cnt.raw = @truncate(value >> 0); // 0x0400_100A
+                bus.ppu.engines[1].bg[3].cnt.raw = @truncate(value >> 16); // 0x0400_100C
+            },
+            0x00400_1010 => {
+                bus.ppu.engines[1].bg[0].hofs.raw = @truncate(value >> 0); // 0x0400_1010
+                bus.ppu.engines[1].bg[0].vofs.raw = @truncate(value >> 16); // 0x0400_1012
+            },
+            0x00400_1014 => {
+                bus.ppu.engines[1].bg[1].hofs.raw = @truncate(value >> 0); // 0x0400_1014
+                bus.ppu.engines[1].bg[1].vofs.raw = @truncate(value >> 16); // 0x0400_1016
+            },
+            0x00400_1018 => {
+                bus.ppu.engines[1].bg[2].hofs.raw = @truncate(value >> 0); // 0x0400_1018
+                bus.ppu.engines[1].bg[2].vofs.raw = @truncate(value >> 16); // 0x0400_101A
+            },
+            0x00400_101C => {
+                bus.ppu.engines[1].bg[3].hofs.raw = @truncate(value >> 0); // 0x0400_101C
+                bus.ppu.engines[1].bg[3].vofs.raw = @truncate(value >> 16); // 0x0400_101E
+            },
 
             else => log.warn("unexpected: write(T: {}, addr: 0x{X:0>8}, value: 0x{X:0>8})", .{ T, address, value }),
         },
         u16 => switch (address) {
+            0x0400_0004 => bus.ppu.io.nds9.dispstat.raw = value,
+
+            // DMA Transfers
+            0x0400_00B0...0x0400_00DE => dma.write(T, &bus.dma, address, value),
+            0x0400_00E0...0x0400_00EE => std.mem.writeIntLittle(T, bus.io.dma_fill[address & 0xF ..][0..@sizeOf(T)], value),
+
+            // Timers
+            0x0400_0100...0x0400_010E => log.warn("TODO: impl timer", .{}),
+
             0x0400_0180 => bus.io.shr.ipc.setIpcSync(.nds9, value),
             0x0400_0184 => bus.io.shr.ipc.setIpcFifoCnt(.nds9, value),
             0x0400_0208 => bus.io.ime = value & 1 == 1,
@@ -142,11 +281,34 @@ pub fn write(bus: *Bus, comptime T: type, address: u32, value: T) void {
                 bus.io.sqrt.schedule(bus.scheduler);
             },
 
-            0x0400_0304 => bus.io.powcnt.raw = value,
+            0x0400_0304 => bus.ppu.io.powcnt.raw = value,
 
-            else => log.warn("unexpected: write(T: {}, addr: 0x{X:0>8}, value: 0x{X:0>8})", .{ T, address, value }),
+            0x0400_1008 => bus.ppu.engines[1].bg[0].cnt.raw = value,
+            0x0400_100A => bus.ppu.engines[1].bg[1].cnt.raw = value,
+            0x0400_100C => bus.ppu.engines[1].bg[2].cnt.raw = value,
+            0x0400_100E => bus.ppu.engines[1].bg[3].cnt.raw = value,
+
+            0x0400_1010 => bus.ppu.engines[1].bg[0].hofs.raw = value,
+            0x0400_1012 => bus.ppu.engines[1].bg[0].vofs.raw = value,
+            0x0400_1014 => bus.ppu.engines[1].bg[1].hofs.raw = value,
+            0x0400_1016 => bus.ppu.engines[1].bg[1].vofs.raw = value,
+            0x0400_1018 => bus.ppu.engines[1].bg[2].hofs.raw = value,
+            0x0400_101A => bus.ppu.engines[1].bg[2].vofs.raw = value,
+            0x0400_101C => bus.ppu.engines[1].bg[3].hofs.raw = value,
+            0x0400_101E => bus.ppu.engines[1].bg[3].vofs.raw = value,
+
+            else => log.warn("unexpected: write(T: {}, addr: 0x{X:0>8}, value: 0x{X:0>4})", .{ T, address, value }),
         },
         u8 => switch (address) {
+            // DMA Transfers
+            0x0400_00B0...0x0400_00DF => dma.write(T, &bus.dma, address, value),
+            0x0400_00E0...0x0400_00EF => std.mem.writeIntLittle(T, bus.io.dma_fill[address & 0xF ..][0..@sizeOf(T)], value),
+
+            // Timers
+            0x0400_0100...0x0400_010F => log.warn("TODO: impl timer", .{}),
+
+            0x0400_0208 => bus.io.ime = value & 1 == 1,
+
             0x0400_0240 => {
                 bus.ppu.vram.io.cnt_a.raw = value;
                 bus.ppu.vram.update();
@@ -188,7 +350,7 @@ pub fn write(bus: *Bus, comptime T: type, address: u32, value: T) void {
                 bus.ppu.vram.update();
             },
 
-            else => log.warn("unexpected: write(T: {}, addr: 0x{X:0>8}, value: 0x{X:0>8})", .{ T, address, value }),
+            else => log.warn("unexpected: write(T: {}, addr: 0x{X:0>8}, value: 0x{X:0>2})", .{ T, address, value }),
         },
         else => @compileError(T ++ " is an unsupported bus write type"),
     }
@@ -199,7 +361,7 @@ fn warn(comptime format: []const u8, args: anytype) u0 {
     return 0;
 }
 
-const PowCnt = extern union {
+pub const PowCnt = extern union {
     // Enable flag for both LCDs
     lcd: Bit(u32, 0),
     engine2d_a: Bit(u32, 1),
@@ -340,8 +502,7 @@ const SquareRootUnit = struct {
 };
 
 pub const DispcntA = extern union {
-    bg_mode: Bitfield(u32, 0, 2),
-
+    bg_mode: Bitfield(u32, 0, 3),
     /// toggle between 2D and 3D for BG0
     bg0_dimension: Bit(u32, 3),
     tile_obj_mapping: Bit(u32, 4),
@@ -357,8 +518,26 @@ pub const DispcntA = extern union {
     tile_obj_1d_boundary: Bitfield(u32, 20, 2),
     bitmap_obj_1d_boundary: Bit(u32, 22),
     obj_during_hblank: Bit(u32, 23),
-    character_base: Bitfield(u32, 24, 3),
-    screen_base: Bitfield(u32, 27, 2),
+    char_base: Bitfield(u32, 24, 3),
+    screen_base: Bitfield(u32, 27, 3),
+    bg_ext_pal_enable: Bit(u32, 30),
+    obj_ext_pal_enable: Bit(u32, 31),
+    raw: u32,
+};
+
+pub const DispcntB = extern union {
+    bg_mode: Bitfield(u32, 0, 3),
+    tile_obj_mapping: Bit(u32, 4),
+    bitmap_obj_2d_dimension: Bit(u32, 5),
+    bitmap_obj_mapping: Bit(u32, 6),
+    forced_blank: Bit(u32, 7),
+    bg_enable: Bitfield(u32, 8, 4),
+    obj_enable: Bit(u32, 12),
+    win_enable: Bitfield(u32, 13, 2),
+    obj_win_enable: Bit(u32, 15),
+    display_mode: Bitfield(u32, 16, 2),
+    tile_obj_1d_boundary: Bitfield(u32, 20, 2),
+    obj_during_hblank: Bit(u32, 23),
     bg_ext_pal_enable: Bit(u32, 30),
     obj_ext_pal_enable: Bit(u32, 31),
     raw: u32,
@@ -416,40 +595,33 @@ pub const Dispstat = extern union {
     raw: u16,
 };
 
-/// Read Only
-/// 0 = Pressed, 1 = Released
-pub const KeyInput = extern union {
-    a: Bit(u16, 0),
-    b: Bit(u16, 1),
-    select: Bit(u16, 2),
-    start: Bit(u16, 3),
-    right: Bit(u16, 4),
-    left: Bit(u16, 5),
-    up: Bit(u16, 6),
-    down: Bit(u16, 7),
-    shoulder_r: Bit(u16, 8),
-    shoulder_l: Bit(u16, 9),
+pub const Bgcnt = extern union {
+    priority: Bitfield(u16, 0, 2),
+    char_base: Bitfield(u16, 2, 4),
+    mosaic_enable: Bit(u16, 6),
+    colour_mode: Bit(u16, 7),
+    screen_base: Bitfield(u16, 8, 5),
+    display_overflow: Bit(u16, 13),
+    size: Bitfield(u16, 14, 2),
     raw: u16,
 };
 
-const AtomicKeyInput = struct {
-    const Self = @This();
-    const Ordering = std.atomic.Ordering;
-
-    inner: KeyInput = .{ .raw = 0x03FF },
-
-    pub inline fn load(self: *const Self, comptime ordering: Ordering) u16 {
-        return switch (ordering) {
-            .AcqRel, .Release => @compileError("not supported for atomic loads"),
-            else => @atomicLoad(u16, &self.inner.raw, ordering),
-        };
-    }
-
-    pub inline fn fetchOr(self: *Self, value: u16, comptime ordering: Ordering) void {
-        _ = @atomicRmw(u16, &self.inner.raw, .Or, value, ordering);
-    }
-
-    pub inline fn fetchAnd(self: *Self, value: u16, comptime ordering: Ordering) void {
-        _ = @atomicRmw(u16, &self.inner.raw, .And, value, ordering);
-    }
+/// Write Only
+const BackgroundOffset = extern union {
+    offset: Bitfield(u16, 0, 9),
+    raw: u16,
+};
+
+pub const Hofs = BackgroundOffset;
+pub const Vofs = BackgroundOffset;
+
+pub const DmaCnt = extern union {
+    dad_adj: Bitfield(u16, 5, 2),
+    sad_adj: Bitfield(u16, 7, 2),
+    repeat: Bit(u16, 9),
+    transfer_type: Bit(u16, 10),
+    start_timing: Bitfield(u16, 11, 3),
+    irq: Bit(u16, 14),
+    enabled: Bit(u16, 15),
+    raw: u16,
 };

src/core/ppu.zig

@@ -4,6 +4,17 @@ const Allocator = std.mem.Allocator;
 const Scheduler = @import("Scheduler.zig");
 const System = @import("emu.zig").System;
 
+const Vram = @import("ppu/Vram.zig");
+const Oam = @import("ppu/Oam.zig");
+
+const EngineA = @import("ppu/engine.zig").EngineA;
+const EngineB = @import("ppu/engine.zig").EngineB;
+
+const dma7 = @import("nds7/dma.zig");
+const dma9 = @import("nds9/dma.zig");
+
+const handleInterrupt = @import("emu.zig").handleInterrupt;
+
 pub const screen_width = 256;
 pub const screen_height = 192;
 const KiB = 0x400;
@@ -15,91 +26,135 @@ pub const Ppu = struct {
 
     vram: *Vram,
 
+    // FIXME: do I need a pointer here?
+    oam: *Oam,
+
+    engines: struct { EngineA, EngineB },
+
     io: Io = .{},
 
-    const Io = struct {
-        const nds9 = @import("nds9/io.zig");
+    pub const Io = struct {
+        const ty = @import("nds9/io.zig");
 
-        /// Read / Write
-        dispcnt_a: nds9.DispcntA = .{ .raw = 0x0000_0000 },
-        /// Read / Write
-        dispstat: nds9.Dispstat = .{ .raw = 0x0000 },
+        nds9: struct {
+            dispstat: ty.Dispstat = .{ .raw = 0x00000 },
+            vcount: ty.Vcount = .{ .raw = 0x0000 },
+        } = .{},
 
-        /// Read-Only
-        vcount: nds9.Vcount = .{ .raw = 0x0000 },
+        nds7: struct {
+            dispstat: ty.Dispstat = .{ .raw = 0x0000 },
+            vcount: ty.Vcount = .{ .raw = 0x00000 },
+        } = .{},
+
+        powcnt: ty.PowCnt = .{ .raw = 0x0000_0000 },
     };
 
     pub fn init(allocator: Allocator, vram: *Vram) !@This() {
         return .{
             .fb = try FrameBuffer.init(allocator),
+            .engines = .{ try EngineA.init(allocator), try EngineB.init(allocator) },
             .vram = vram,
+            .oam = blk: {
+                var oam = try allocator.create(Oam);
+                oam.init();
+
+                break :blk oam;
+            },
         };
     }
 
     pub fn deinit(self: @This(), allocator: Allocator) void {
         self.fb.deinit(allocator);
+        inline for (self.engines) |eng| eng.deinit(allocator);
+        allocator.destroy(self.oam);
     }
 
     pub fn drawScanline(self: *@This(), bus: *System.Bus9) void {
-        const bg_mode = self.io.dispcnt_a.display_mode.read();
-        const scanline = self.io.vcount.scanline.read();
+        if (self.io.powcnt.engine2d_a.read())
+            self.engines[0].drawScanline(bus, &self.fb);
 
-        switch (bg_mode) {
-            0x0 => {},
-            0x1 => {},
-            0x2 => {
-                // Draw Top Screen
-                {
-                    const buf = self.fb.top(.back);
-
-                    const ptr: *[screen_width * screen_height]u32 = @ptrCast(@alignCast(buf.ptr));
-                    const scanline_ptr = ptr[screen_width * @as(u32, scanline) ..][0..screen_width];
-
-                    const base_addr: u32 = 0x0680_0000 + (screen_width * @sizeOf(u16)) * @as(u32, scanline);
-
-                    // FIXME: I don't think it's okay to be accessing the ARM9 Bus instead of just working with
-                    // memory directly. However, I do understand that VRAM-A, VRAM-B might change things
-
-                    for (scanline_ptr, 0..) |*rgba, i| {
-                        const addr = base_addr + @as(u32, @intCast(i)) * @sizeOf(u16);
-                        rgba.* = rgba888(bus.dbgRead(u16, addr));
-                    }
-                }
-            },
-            0x3 => {},
-        }
+        if (self.io.powcnt.engine2d_b.read())
+            self.engines[1].drawScanline(bus, &self.fb);
     }
 
     /// HDraw -> HBlank
-    pub fn onHdrawEnd(self: *@This(), scheduler: *Scheduler, late: u64) void {
+    pub fn onHdrawEnd(self: *@This(), system: System, scheduler: *Scheduler, late: u64) void {
+        if (self.io.nds9.dispstat.hblank_irq.read()) {
+            system.bus9.io.irq.hblank.set();
+            handleInterrupt(.nds9, system.arm946es);
+        }
+
+        if (self.io.nds7.dispstat.hblank_irq.read()) {
+            system.bus7.io.irq.hblank.set();
+            handleInterrupt(.nds7, system.arm7tdmi);
+        }
+
+        if (!self.io.nds9.dispstat.vblank.read()) { // ensure we aren't in VBlank
+            dma9.onHblank(system.bus9);
+        }
+
+        self.io.nds9.dispstat.hblank.set();
+        self.io.nds7.dispstat.hblank.set();
+
         const dots_in_hblank = 99;
-        std.debug.assert(self.io.dispstat.hblank.read() == false);
-        std.debug.assert(self.io.dispstat.vblank.read() == false);
-
-        // TODO: Signal HBlank IRQ
-
-        self.io.dispstat.hblank.set();
         scheduler.push(.{ .nds9 = .hblank }, dots_in_hblank * cycles_per_dot -| late);
     }
 
-    pub fn onHblankEnd(self: *@This(), scheduler: *Scheduler, late: u64) void {
-        const scanline_count = 192 + 71;
+    /// VBlank -> HBlank (Still VBlank)
+    pub fn onVblankEnd(self: *@This(), system: System, scheduler: *Scheduler, late: u64) void {
+        if (self.io.nds9.dispstat.hblank_irq.read()) {
+            system.bus9.io.irq.hblank.set();
+            handleInterrupt(.nds9, system.arm946es);
+        }
 
-        const prev_scanline = self.io.vcount.scanline.read();
-        const scanline = (prev_scanline + 1) % scanline_count;
+        if (self.io.nds7.dispstat.hblank_irq.read()) {
+            system.bus7.io.irq.hblank.set();
+            handleInterrupt(.nds7, system.arm7tdmi);
+        }
 
-        self.io.vcount.scanline.write(scanline);
-        self.io.dispstat.hblank.unset();
+        self.io.nds9.dispstat.hblank.set();
+        self.io.nds7.dispstat.hblank.set();
 
-        const coincidence = scanline == self.io.dispstat.lyc.read();
-        self.io.dispstat.coincidence.write(coincidence);
+        // TODO: Run DMAs on HBlank
 
-        // TODO: LYC == LY IRQ
+        const dots_in_hblank = 99;
+        scheduler.push(.{ .nds9 = .hblank }, dots_in_hblank * cycles_per_dot -| late);
+    }
+
+    /// HBlank -> HDraw / VBlank
+    pub fn onHblankEnd(self: *@This(), system: System, scheduler: *Scheduler, late: u64) void {
+        const scanline_total = 263; // 192 visible, 71 blanking
+
+        const prev_scanline = self.io.nds9.vcount.scanline.read();
+        const scanline = (prev_scanline + 1) % scanline_total;
+
+        self.io.nds9.vcount.scanline.write(scanline);
+        self.io.nds7.vcount.scanline.write(scanline);
+
+        self.io.nds9.dispstat.hblank.unset();
+        self.io.nds7.dispstat.hblank.unset();
+
+        {
+            const coincidence = scanline == self.io.nds9.dispstat.lyc.read();
+            self.io.nds9.dispstat.coincidence.write(coincidence);
+
+            if (coincidence and self.io.nds9.dispstat.vcount_irq.read()) {
+                system.bus9.io.irq.coincidence.set();
+                handleInterrupt(.nds9, system.arm946es);
+            }
+        }
+
+        {
+            const coincidence = scanline == self.io.nds7.dispstat.lyc.read();
+            self.io.nds7.dispstat.coincidence.write(coincidence);
+
+            if (coincidence and self.io.nds7.dispstat.vcount_irq.read()) {
+                system.bus7.io.irq.coincidence.set();
+                handleInterrupt(.nds7, system.arm7tdmi);
+            }
+        }
 
         if (scanline < 192) {
-            std.debug.assert(self.io.dispstat.vblank.read() == false);
-            std.debug.assert(self.io.dispstat.hblank.read() == false);
-
             // Draw Another Scanline
             const dots_in_hdraw = 256;
             return scheduler.push(.{ .nds9 = .draw }, dots_in_hdraw * cycles_per_dot -| late);
@@ -108,16 +163,35 @@ pub const Ppu = struct {
         if (scanline == 192) {
             // Transition from Hblank to Vblank
             self.fb.swap();
-            self.io.dispstat.vblank.set();
 
-            // TODO: Signal VBlank IRQ
+            if (self.io.nds9.dispstat.vblank_irq.read()) {
+                system.bus9.io.irq.vblank.set();
+                handleInterrupt(.nds9, system.arm946es);
+            }
+
+            if (self.io.nds7.dispstat.vblank_irq.read()) {
+                system.bus7.io.irq.vblank.set();
+                handleInterrupt(.nds7, system.arm7tdmi);
+            }
+
+            self.io.nds9.dispstat.vblank.set();
+            self.io.nds7.dispstat.vblank.set();
+
+            // TODO: Affine BG Latches
+
+            dma7.onVblank(system.bus7);
+            dma9.onVblank(system.bus9);
+
+            // TODO: VBlank DMA9 Transfers
         }
 
-        if (scanline == 262) self.io.dispstat.vblank.unset();
-        std.debug.assert(self.io.dispstat.vblank.read() == (scanline != 262));
+        if (scanline == 262) {
+            self.io.nds9.dispstat.vblank.unset();
+            self.io.nds7.dispstat.vblank.unset();
+        }
 
-        const dots_in_scanline = 256 + 99;
-        scheduler.push(.{ .nds9 = .hblank }, dots_in_scanline * cycles_per_dot -| late);
+        const dots_in_vblank = 256;
+        scheduler.push(.{ .nds9 = .vblank }, dots_in_vblank * cycles_per_dot -| late);
     }
 };
 
@@ -126,15 +200,15 @@ pub const FrameBuffer = struct {
 
     current: u1 = 0,
 
-    ptr: *[len * 4]u8,
+    ptr: *align(@sizeOf(u32)) [len * 4]u8,
 
     const Position = enum { top, bottom };
     const Layer = enum { front, back };
 
     pub fn init(allocator: Allocator) !@This() {
-        const ptr = try allocator.create([len * 4]u8);
+        const buf = try allocator.alignedAlloc(u8, @sizeOf(u32), len * 4);
 
-        return .{ .ptr = ptr };
+        return .{ .ptr = buf[0 .. len * 4] };
     }
 
     pub fn deinit(self: @This(), allocator: Allocator) void {
@@ -162,303 +236,3 @@ pub const FrameBuffer = struct {
         return self.get(.bottom, layer);
     }
 };
-
-inline fn rgba888(bgr555: u16) u32 {
-    const b: u32 = bgr555 >> 10 & 0x1F;
-    const g: u32 = bgr555 >> 5 & 0x1F;
-    const r: u32 = bgr555 & 0x1F;
-
-    // zig fmt: off
-    return (r << 3 | r >> 2) << 24
-        |  (g << 3 | g >> 2) << 16
-        |  (b << 3 | b >> 2) << 8
-        |  0xFF;
-    // zig fmt: on
-}
-
-pub const Vram = struct {
-    const page_size = 16 * KiB; // smallest allocation is 16 KiB
-    const addr_space_size = 0x0100_0000; // 0x0600_0000 -> 0x06FF_FFFF (inclusive)
-    const table_len = addr_space_size / page_size;
-    const buf_len = 656 * KiB;
-
-    const IntFittingRange = std.math.IntFittingRange;
-    const log = std.log.scoped(.vram);
-
-    io: Io = .{},
-
-    _buf: *[buf_len]u8,
-    nds9_table: *const [table_len]?[*]u8,
-    nds7_table: *const [table_len]?[*]u8,
-
-    const Io = struct {
-        const nds9 = @import("nds9/io.zig");
-        const nds7 = @import("nds7/io.zig");
-        pub const Vramstat = @import("nds7/io.zig").Vramstat;
-
-        stat: nds7.Vramstat = .{ .raw = 0x00 },
-
-        /// Write-Only (according to melonDS these are readable lol)
-        cnt_a: nds9.Vramcnt.A = .{ .raw = 0x00 },
-        cnt_b: nds9.Vramcnt.A = .{ .raw = 0x00 },
-        cnt_c: nds9.Vramcnt.C = .{ .raw = 0x00 },
-        cnt_d: nds9.Vramcnt.C = .{ .raw = 0x00 },
-        cnt_e: nds9.Vramcnt.E = .{ .raw = 0x00 },
-        cnt_f: nds9.Vramcnt.C = .{ .raw = 0x00 },
-        cnt_g: nds9.Vramcnt.C = .{ .raw = 0x00 },
-        cnt_h: nds9.Vramcnt.H = .{ .raw = 0x00 },
-        cnt_i: nds9.Vramcnt.H = .{ .raw = 0x00 },
-    };
-
-    pub fn init(self: *@This(), allocator: Allocator) !void {
-        const buf = try allocator.create([buf_len]u8);
-        errdefer allocator.destroy(buf);
-        @memset(buf, 0);
-
-        const tables = try allocator.alloc(?[*]u8, 2 * table_len);
-        @memset(tables, null);
-
-        self.* = .{
-            .nds9_table = tables[0..table_len],
-            .nds7_table = tables[table_len .. 2 * table_len],
-            ._buf = buf,
-        };
-
-        // ROMS like redpanda.nds won't write to VRAMCNT before trying to write to VRAM
-        // therefore we assume some default allocation (in this casee VRAMCNT_A -> VRAMCNT_I are 0x00)
-        self.update();
-    }
-
-    pub fn deinit(self: @This(), allocator: Allocator) void {
-        allocator.destroy(self._buf);
-
-        const ptr: [*]?[*]const u8 = @ptrCast(@constCast(self.nds9_table));
-        allocator.free(ptr[0 .. 2 * table_len]);
-    }
-
-    pub fn stat(self: *const @This()) Io.Vramstat {
-        const vram_c: u8 = @intFromBool(self.io.cnt_c.enable.read() and self.io.cnt_c.mst.read() == 2);
-        const vram_d: u8 = @intFromBool(self.io.cnt_d.enable.read() and self.io.cnt_d.mst.read() == 2);
-
-        return .{ .raw = (vram_d << 1) | vram_c };
-    }
-
-    const Kind = enum {
-        a,
-        b,
-        c,
-        d,
-        e,
-        f,
-        g,
-        h,
-        i,
-
-        /// In Bytes
-        inline fn size(self: @This()) u32 {
-            return switch (self) {
-                .a => 128 * KiB,
-                .b => 128 * KiB,
-                .c => 128 * KiB,
-                .d => 128 * KiB,
-                .e => 64 * KiB,
-                .f => 16 * KiB,
-                .g => 16 * KiB,
-                .h => 32 * KiB,
-                .i => 16 * KiB,
-            };
-        }
-    };
-
-    // TODO: Rename
-    fn range(comptime kind: Kind, mst: u3, offset: u2) u32 {
-        const ofs: u32 = offset;
-        // panic messages are from GBATEK
-
-        return switch (kind) {
-            .a => switch (mst) {
-                0 => 0x0680_0000,
-                1 => 0x0600_0000 + (0x0002_0000 * ofs),
-                2 => 0x0640_0000 + (0x0002_0000 * (ofs & 0b01)),
-                3 => @panic("VRAMCNT_A: Slot OFS(0-3)"),
-                else => std.debug.panic("Invalid MST for VRAMCNT_{s}", .{[_]u8{std.ascii.toUpper(@tagName(kind)[0])}}),
-            },
-            .b => switch (mst) {
-                0 => 0x0682_0000,
-                1 => 0x0600_0000 + (0x0002_0000 * ofs),
-                2 => 0x0640_0000 + (0x0002_0000 * (ofs & 0b01)),
-                3 => @panic("VRAMCNT_B: Slot OFS(0-3)"),
-                else => std.debug.panic("Invalid MST for VRAMCNT_{s}", .{[_]u8{std.ascii.toUpper(@tagName(kind)[0])}}),
-            },
-            .c => switch (mst) {
-                0 => 0x0684_0000,
-                1 => 0x0600_0000 + (0x0002_0000 * ofs),
-                2 => 0x0600_0000 + (0x0002_0000 * (ofs & 0b01)),
-                3 => @panic("VRAMCNT_C: Slot OFS(0-3)"),
-                4 => 0x0620_0000,
-                else => std.debug.panic("Invalid MST for VRAMCNT_{s}", .{[_]u8{std.ascii.toUpper(@tagName(kind)[0])}}),
-            },
-            .d => switch (mst) {
-                0 => 0x0686_0000,
-                1 => 0x0600_0000 + (0x0002_0000 * ofs),
-                2 => 0x0600_0000 + (0x0002_0000 * (ofs & 0b01)),
-                3 => @panic("VRAMCNT_D: Slot OFS(0-3)"),
-                4 => 0x0660_0000,
-                else => std.debug.panic("Invalid MST for VRAMCNT_{s}", .{[_]u8{std.ascii.toUpper(@tagName(kind)[0])}}),
-            },
-            .e => switch (mst) {
-                0 => 0x0688_0000,
-                1 => 0x0600_0000,
-                2 => 0x0640_0000,
-                3 => @panic("VRAMCNT_E: Slots 0-3"),
-                else => std.debug.panic("Invalid MST for VRAMCNT_{s}", .{[_]u8{std.ascii.toUpper(@tagName(kind)[0])}}),
-            },
-            .f => switch (mst) {
-                0 => 0x0689_0000,
-                1 => 0x0600_0000 + (0x0000_4000 * (ofs & 0b01)) + (0x0001_0000 * (ofs >> 1)),
-                2 => 0x0640_0000 + (0x0000_4000 * (ofs & 0b01)) + (0x0001_0000 * (ofs >> 1)),
-                3 => @panic("VRAMCNT_F: Slot (OFS.0*1)+(OFS.1*4)"),
-                4 => @panic("VRAMCNT_F: Slot 0-1 (OFS=0), Slot 2-3 (OFS=1)"),
-                5 => @panic("VRAMCNT_F: Slot 0"),
-                else => std.debug.panic("Invalid MST for VRAMCNT_{s}", .{[_]u8{std.ascii.toUpper(@tagName(kind)[0])}}),
-            },
-            .g => switch (mst) {
-                0 => 0x0689_4000,
-                1 => 0x0600_0000 + (0x0000_4000 * (ofs & 0b01)) + (0x0001_0000 * (ofs >> 1)),
-                2 => 0x0640_0000 + (0x0000_4000 * (ofs & 0b01)) + (0x0001_0000 * (ofs >> 1)),
-                3 => @panic("VRAMCNT_G: Slot (OFS.0*1)+(OFS.1*4)"),
-                4 => @panic("VRAMCNT_G: Slot 0-1 (OFS=0), Slot 2-3 (OFS=1)"),
-                5 => @panic("VRAMCNT_G: Slot 0"),
-                else => std.debug.panic("Invalid MST for VRAMCNT_{s}", .{[_]u8{std.ascii.toUpper(@tagName(kind)[0])}}),
-            },
-            .h => switch (mst) {
-                0 => 0x0689_8000,
-                1 => 0x0620_0000,
-                2 => @panic("VRAMCNT_H: Slot 0-3"),
-                else => std.debug.panic("Invalid MST for VRAMCNT_{s}", .{[_]u8{std.ascii.toUpper(@tagName(kind)[0])}}),
-            },
-            .i => switch (mst) {
-                0 => 0x068A_0000,
-                1 => 0x0620_8000,
-                2 => 0x0660_0000,
-                3 => @panic("Slot 0"),
-                else => std.debug.panic("Invalid MST for VRAMCNT_{s}", .{[_]u8{std.ascii.toUpper(@tagName(kind)[0])}}),
-            },
-        };
-    }
-
-    fn buf_offset(comptime kind: Kind) usize {
-        // zig fmt: off
-        return switch (kind) {
-            .a => 0,                                                            // 0x00000
-            .b => (128 * KiB) * 1,                                              // 0x20000 (+ 0x20000)
-            .c => (128 * KiB) * 2,                                              // 0x40000 (+ 0x20000)
-            .d => (128 * KiB) * 3,                                              // 0x60000 (+ 0x20000)
-            .e => (128 * KiB) * 4,                                              // 0x80000 (+ 0x20000)
-            .f => (128 * KiB) * 4 + (64 * KiB),                                 // 0x90000 (+ 0x10000)
-            .g => (128 * KiB) * 4 + (64 * KiB) + (16 * KiB) * 1,                // 0x94000 (+ 0x04000)
-            .h => (128 * KiB) * 4 + (64 * KiB) + (16 * KiB) * 2,                // 0x98000 (+ 0x04000)
-            .i => (128 * KiB) * 4 + (64 * KiB) + (16 * KiB) * 2 + (32 * KiB)    // 0xA0000 (+ 0x08000)
-        };
-        // zig fmt: on
-    }
-
-    fn CntType(comptime kind: Kind) type {
-        const io = @import("nds9/io.zig");
-
-        return switch (kind) {
-            .a => io.Vramcnt.A,
-            .b => io.Vramcnt.A,
-            .c => io.Vramcnt.C,
-            .d => io.Vramcnt.C,
-            .e => io.Vramcnt.E,
-            .f => io.Vramcnt.C,
-            .g => io.Vramcnt.C,
-            .h => io.Vramcnt.H,
-            .i => io.Vramcnt.H,
-        };
-    }
-
-    fn cntValue(self: *const @This(), comptime kind: Kind) CntType(kind) {
-        return switch (kind) {
-            .a => self.io.cnt_a,
-            .b => self.io.cnt_b,
-            .c => self.io.cnt_c,
-            .d => self.io.cnt_d,
-            .e => self.io.cnt_e,
-            .f => self.io.cnt_f,
-            .g => self.io.cnt_g,
-            .h => self.io.cnt_h,
-            .i => self.io.cnt_i,
-        };
-    }
-
-    // TODO: We always update the entirety of VRAM when that argubably isn't necessary
-    pub fn update(self: *@This()) void {
-        const nds9_tbl = @constCast(self.nds9_table);
-        const nds7_tbl = @constCast(self.nds7_table);
-
-        for (nds9_tbl, nds7_tbl, 0..) |*nds9_ptr, *nds7_ptr, i| {
-            const addr = 0x0600_0000 + (i * page_size);
-
-            inline for (std.meta.fields(Kind)) |f| {
-                const kind = @field(Kind, f.name);
-                const cnt = cntValue(self, kind);
-                const ofs = switch (kind) {
-                    .e, .h, .i => 0,
-                    else => cnt.offset.read(),
-                };
-
-                const min = range(kind, cnt.mst.read(), ofs);
-                const max = min + kind.size();
-                const offset = addr & (kind.size() - 1);
-
-                if (min <= addr and addr < max) {
-                    if ((kind == .c or kind == .d) and cnt.mst.read() == 2) {
-                        // Allocate to ARM7
-                        nds7_ptr.* = self._buf[buf_offset(kind) + offset ..].ptr;
-                    } else {
-                        nds9_ptr.* = self._buf[buf_offset(kind) + offset ..].ptr;
-                    }
-                }
-            }
-        }
-    }
-
-    // TODO: Rename
-    const Device = enum { nds9, nds7 };
-
-    pub fn read(self: @This(), comptime T: type, comptime dev: Device, address: u32) T {
-        const bits = @typeInfo(IntFittingRange(0, page_size - 1)).Int.bits;
-        const masked_addr = address & (addr_space_size - 1);
-        const page = masked_addr >> bits;
-        const offset = masked_addr & (page_size - 1);
-        const table = if (dev == .nds9) self.nds9_table else self.nds7_table;
-
-        if (table[page]) |some_ptr| {
-            const ptr: [*]const T = @ptrCast(@alignCast(some_ptr));
-
-            return ptr[offset / @sizeOf(T)];
-        }
-
-        log.err("{s}: read(T: {}, addr: 0x{X:0>8}) was in un-mapped VRAM space", .{ @tagName(dev), T, address });
-        return 0x00;
-    }
-
-    pub fn write(self: *@This(), comptime T: type, comptime dev: Device, address: u32, value: T) void {
-        const bits = @typeInfo(IntFittingRange(0, page_size - 1)).Int.bits;
-        const masked_addr = address & (addr_space_size - 1);
-        const page = masked_addr >> bits;
-        const offset = masked_addr & (page_size - 1);
-        const table = if (dev == .nds9) self.nds9_table else self.nds7_table;
-
-        if (table[page]) |some_ptr| {
-            const ptr: [*]T = @ptrCast(@alignCast(some_ptr));
-            ptr[offset / @sizeOf(T)] = value;
-
-            return;
-        }
-
-        log.err("{s}: write(T: {}, addr: 0x{X:0>8}, value: 0x{X:0>8}) was in un-mapped VRA< space", .{ @tagName(dev), T, address, value });
-    }
-};

src/core/ppu/Oam.zig

@@ -0,0 +1,7 @@
+const KiB = 0x400;
+
+buf: [2 * KiB]u8,
+
+pub fn init(self: *@This()) void {
+    @memset(self.buf[0..], 0);
+}

src/core/ppu/Vram.zig

@@ -0,0 +1,290 @@
+const std = @import("std");
+const KiB = 0x400;
+
+const System = @import("../emu.zig").System;
+
+const Allocator = std.mem.Allocator;
+const IntFittingRange = std.math.IntFittingRange;
+
+const page_size = 16 * KiB; // smallest allocation is 16 KiB
+const addr_space_size = 0x0100_0000; // 0x0600_0000 -> 0x06FF_FFFF (inclusive)
+const table_len = addr_space_size / page_size;
+const buf_len = 656 * KiB;
+
+const log = std.log.scoped(.vram);
+
+io: Io = .{},
+
+_buf: *[buf_len]u8,
+nds9_table: *const [table_len]?[*]u8,
+nds7_table: *const [table_len]?[*]u8,
+
+const Io = struct {
+    pub const Vramstat = nds7.Vramstat;
+
+    const nds9 = @import("../nds9/io.zig");
+    const nds7 = @import("../nds7/io.zig");
+
+    stat: nds7.Vramstat = .{ .raw = 0x00 },
+
+    /// Write-Only (according to melonDS these are readable lol)
+    cnt_a: nds9.Vramcnt.A = .{ .raw = 0x00 },
+    cnt_b: nds9.Vramcnt.A = .{ .raw = 0x00 },
+    cnt_c: nds9.Vramcnt.C = .{ .raw = 0x00 },
+    cnt_d: nds9.Vramcnt.C = .{ .raw = 0x00 },
+    cnt_e: nds9.Vramcnt.E = .{ .raw = 0x00 },
+    cnt_f: nds9.Vramcnt.C = .{ .raw = 0x00 },
+    cnt_g: nds9.Vramcnt.C = .{ .raw = 0x00 },
+    cnt_h: nds9.Vramcnt.H = .{ .raw = 0x00 },
+    cnt_i: nds9.Vramcnt.H = .{ .raw = 0x00 },
+};
+
+pub fn init(self: *@This(), allocator: Allocator) !void {
+    const buf = try allocator.create([buf_len]u8);
+    errdefer allocator.destroy(buf);
+    @memset(buf, 0);
+
+    const tables = try allocator.alloc(?[*]u8, 2 * table_len);
+    @memset(tables, null);
+
+    self.* = .{
+        .nds9_table = tables[0..table_len],
+        .nds7_table = tables[table_len .. 2 * table_len],
+        ._buf = buf,
+    };
+
+    // ROMS like redpanda.nds won't write to VRAMCNT before trying to write to VRAM
+    // therefore we assume some default allocation (in this casee VRAMCNT_A -> VRAMCNT_I are 0x00)
+    self.update();
+}
+
+pub fn deinit(self: @This(), allocator: Allocator) void {
+    allocator.destroy(self._buf);
+
+    const ptr: [*]?[*]const u8 = @ptrCast(@constCast(self.nds9_table));
+    allocator.free(ptr[0 .. 2 * table_len]);
+}
+
+/// NDS7 VRAMSTAT
+pub fn stat(self: *const @This()) Io.Vramstat {
+    const vram_c: u8 = @intFromBool(self.io.cnt_c.enable.read() and self.io.cnt_c.mst.read() == 2);
+    const vram_d: u8 = @intFromBool(self.io.cnt_d.enable.read() and self.io.cnt_d.mst.read() == 2);
+
+    return .{ .raw = (vram_d << 1) | vram_c };
+}
+
+const Kind = enum {
+    a,
+    b,
+    c,
+    d,
+    e,
+    f,
+    g,
+    h,
+    i,
+
+    /// In Bytes
+    inline fn size(self: @This()) u32 {
+        return switch (self) {
+            .a => 128 * KiB,
+            .b => 128 * KiB,
+            .c => 128 * KiB,
+            .d => 128 * KiB,
+            .e => 64 * KiB,
+            .f => 16 * KiB,
+            .g => 16 * KiB,
+            .h => 32 * KiB,
+            .i => 16 * KiB,
+        };
+    }
+};
+
+// TODO: Rename
+fn range(comptime kind: Kind, mst: u3, offset: u2) u32 {
+    const ofs: u32 = offset;
+    // panic messages are from GBATEK
+
+    return switch (kind) {
+        .a => switch (mst) {
+            0 => 0x0680_0000,
+            1 => 0x0600_0000 + (0x0002_0000 * ofs),
+            2 => 0x0640_0000 + (0x0002_0000 * (ofs & 0b01)),
+            3 => @panic("VRAMCNT_A: Slot OFS(0-3)"),
+            else => std.debug.panic("Invalid MST for VRAMCNT_{s}", .{[_]u8{std.ascii.toUpper(@tagName(kind)[0])}}),
+        },
+        .b => switch (mst) {
+            0 => 0x0682_0000,
+            1 => 0x0600_0000 + (0x0002_0000 * ofs),
+            2 => 0x0640_0000 + (0x0002_0000 * (ofs & 0b01)),
+            3 => @panic("VRAMCNT_B: Slot OFS(0-3)"),
+            else => std.debug.panic("Invalid MST for VRAMCNT_{s}", .{[_]u8{std.ascii.toUpper(@tagName(kind)[0])}}),
+        },
+        .c => switch (mst) {
+            0 => 0x0684_0000,
+            1 => 0x0600_0000 + (0x0002_0000 * ofs),
+            2 => 0x0600_0000 + (0x0002_0000 * (ofs & 0b01)),
+            3 => @panic("VRAMCNT_C: Slot OFS(0-3)"),
+            4 => 0x0620_0000,
+            else => std.debug.panic("Invalid MST for VRAMCNT_{s}", .{[_]u8{std.ascii.toUpper(@tagName(kind)[0])}}),
+        },
+        .d => switch (mst) {
+            0 => 0x0686_0000,
+            1 => 0x0600_0000 + (0x0002_0000 * ofs),
+            2 => 0x0600_0000 + (0x0002_0000 * (ofs & 0b01)),
+            3 => @panic("VRAMCNT_D: Slot OFS(0-3)"),
+            4 => 0x0660_0000,
+            else => std.debug.panic("Invalid MST for VRAMCNT_{s}", .{[_]u8{std.ascii.toUpper(@tagName(kind)[0])}}),
+        },
+        .e => switch (mst) {
+            0 => 0x0688_0000,
+            1 => 0x0600_0000,
+            2 => 0x0640_0000,
+            3 => @panic("VRAMCNT_E: Slots 0-3"),
+            else => std.debug.panic("Invalid MST for VRAMCNT_{s}", .{[_]u8{std.ascii.toUpper(@tagName(kind)[0])}}),
+        },
+        .f => switch (mst) {
+            0 => 0x0689_0000,
+            1 => 0x0600_0000 + (0x0000_4000 * (ofs & 0b01)) + (0x0001_0000 * (ofs >> 1)),
+            2 => 0x0640_0000 + (0x0000_4000 * (ofs & 0b01)) + (0x0001_0000 * (ofs >> 1)),
+            3 => @panic("VRAMCNT_F: Slot (OFS.0*1)+(OFS.1*4)"),
+            4 => @panic("VRAMCNT_F: Slot 0-1 (OFS=0), Slot 2-3 (OFS=1)"),
+            5 => @panic("VRAMCNT_F: Slot 0"),
+            else => std.debug.panic("Invalid MST for VRAMCNT_{s}", .{[_]u8{std.ascii.toUpper(@tagName(kind)[0])}}),
+        },
+        .g => switch (mst) {
+            0 => 0x0689_4000,
+            1 => 0x0600_0000 + (0x0000_4000 * (ofs & 0b01)) + (0x0001_0000 * (ofs >> 1)),
+            2 => 0x0640_0000 + (0x0000_4000 * (ofs & 0b01)) + (0x0001_0000 * (ofs >> 1)),
+            3 => @panic("VRAMCNT_G: Slot (OFS.0*1)+(OFS.1*4)"),
+            4 => @panic("VRAMCNT_G: Slot 0-1 (OFS=0), Slot 2-3 (OFS=1)"),
+            5 => @panic("VRAMCNT_G: Slot 0"),
+            else => std.debug.panic("Invalid MST for VRAMCNT_{s}", .{[_]u8{std.ascii.toUpper(@tagName(kind)[0])}}),
+        },
+        .h => switch (mst) {
+            0 => 0x0689_8000,
+            1 => 0x0620_0000,
+            2 => @panic("VRAMCNT_H: Slot 0-3"),
+            else => std.debug.panic("Invalid MST for VRAMCNT_{s}", .{[_]u8{std.ascii.toUpper(@tagName(kind)[0])}}),
+        },
+        .i => switch (mst) {
+            0 => 0x068A_0000,
+            1 => 0x0620_8000,
+            2 => 0x0660_0000,
+            3 => @panic("Slot 0"),
+            else => std.debug.panic("Invalid MST for VRAMCNT_{s}", .{[_]u8{std.ascii.toUpper(@tagName(kind)[0])}}),
+        },
+    };
+}
+
+fn buf_offset(comptime kind: Kind) usize {
+    // zig fmt: off
+        return switch (kind) {
+            .a => 0,                                                            // 0x00000
+            .b => (128 * KiB) * 1,                                              // 0x20000 (+ 0x20000)
+            .c => (128 * KiB) * 2,                                              // 0x40000 (+ 0x20000)
+            .d => (128 * KiB) * 3,                                              // 0x60000 (+ 0x20000)
+            .e => (128 * KiB) * 4,                                              // 0x80000 (+ 0x20000)
+            .f => (128 * KiB) * 4 + (64 * KiB),                                 // 0x90000 (+ 0x10000)
+            .g => (128 * KiB) * 4 + (64 * KiB) + (16 * KiB) * 1,                // 0x94000 (+ 0x04000)
+            .h => (128 * KiB) * 4 + (64 * KiB) + (16 * KiB) * 2,                // 0x98000 (+ 0x04000)
+            .i => (128 * KiB) * 4 + (64 * KiB) + (16 * KiB) * 2 + (32 * KiB)    // 0xA0000 (+ 0x08000)
+        };
+        // zig fmt: on
+}
+
+fn CntType(comptime kind: Kind) type {
+    const Vramcnt = @import("../nds9/io.zig").Vramcnt;
+
+    return switch (kind) {
+        .a => Vramcnt.A,
+        .b => Vramcnt.A,
+        .c => Vramcnt.C,
+        .d => Vramcnt.C,
+        .e => Vramcnt.E,
+        .f => Vramcnt.C,
+        .g => Vramcnt.C,
+        .h => Vramcnt.H,
+        .i => Vramcnt.H,
+    };
+}
+
+fn cntValue(self: *const @This(), comptime kind: Kind) CntType(kind) {
+    return switch (kind) {
+        .a => self.io.cnt_a,
+        .b => self.io.cnt_b,
+        .c => self.io.cnt_c,
+        .d => self.io.cnt_d,
+        .e => self.io.cnt_e,
+        .f => self.io.cnt_f,
+        .g => self.io.cnt_g,
+        .h => self.io.cnt_h,
+        .i => self.io.cnt_i,
+    };
+}
+
+// TODO: We always update the entirety of VRAM when that argubably isn't necessary
+pub fn update(self: *@This()) void {
+    const nds9_tbl = @constCast(self.nds9_table);
+    const nds7_tbl = @constCast(self.nds7_table);
+
+    for (nds9_tbl, nds7_tbl, 0..) |*nds9_ptr, *nds7_ptr, i| {
+        const addr = 0x0600_0000 + (i * page_size);
+
+        inline for (std.meta.fields(Kind)) |f| {
+            const kind = @field(Kind, f.name);
+            const cnt = cntValue(self, kind);
+            const ofs = switch (kind) {
+                .e, .h, .i => 0,
+                else => cnt.offset.read(),
+            };
+
+            const min = range(kind, cnt.mst.read(), ofs);
+            const max = min + kind.size();
+            const offset = addr & (kind.size() - 1);
+
+            if (min <= addr and addr < max) {
+                if ((kind == .c or kind == .d) and cnt.mst.read() == 2) {
+                    // Allocate to ARM7
+                    nds7_ptr.* = self._buf[buf_offset(kind) + offset ..].ptr;
+                } else {
+                    nds9_ptr.* = self._buf[buf_offset(kind) + offset ..].ptr;
+                }
+            }
+        }
+    }
+}
+
+pub fn read(self: @This(), comptime T: type, comptime proc: System.Process, address: u32) T {
+    const bits = @typeInfo(IntFittingRange(0, page_size - 1)).Int.bits;
+    const masked_addr = address & (addr_space_size - 1);
+    const page = masked_addr >> bits;
+    const offset = masked_addr & (page_size - 1);
+    const table = if (proc == .nds9) self.nds9_table else self.nds7_table;
+
+    if (table[page]) |some_ptr| {
+        const ptr: [*]const T = @ptrCast(@alignCast(some_ptr));
+
+        return ptr[offset / @sizeOf(T)];
+    }
+
+    log.err("{s}: read(T: {}, addr: 0x{X:0>8}) was in un-mapped VRAM space", .{ @tagName(proc), T, address });
+    return 0x00;
+}
+
+pub fn write(self: *@This(), comptime T: type, comptime proc: System.Process, address: u32, value: T) void {
+    const bits = @typeInfo(IntFittingRange(0, page_size - 1)).Int.bits;
+    const masked_addr = address & (addr_space_size - 1);
+    const page = masked_addr >> bits;
+    const offset = masked_addr & (page_size - 1);
+    const table = if (proc == .nds9) self.nds9_table else self.nds7_table;
+
+    if (table[page]) |some_ptr| {
+        const ptr: [*]T = @ptrCast(@alignCast(some_ptr));
+        ptr[offset / @sizeOf(T)] = value;
+
+        return;
+    }
+
+    log.err("{s}: write(T: {}, addr: 0x{X:0>8}, value: 0x{X:0>8}) was in un-mapped VRA< space", .{ @tagName(proc), T, address, value });
+}

src/core/ppu/engine.zig

@@ -0,0 +1,340 @@
+const std = @import("std");
+const Bus = @import("../nds9/Bus.zig");
+
+const FrameBuffer = @import("../ppu.zig").FrameBuffer;
+
+const DispcntA = @import("../nds9/io.zig").DispcntA;
+const DispcntB = @import("../nds9/io.zig").DispcntB;
+
+const Ppu = @import("../ppu.zig").Ppu;
+
+const width = @import("../ppu.zig").screen_width;
+const height = @import("../ppu.zig").screen_height;
+
+const KiB = 0x400;
+
+const EngineKind = enum { a, b };
+
+pub const EngineA = Engine(.a);
+pub const EngineB = Engine(.b);
+
+fn Engine(comptime kind: EngineKind) type {
+    const log = std.log.scoped(.engine2d); // TODO: specify between 2D-A and 2D-B
+
+    // FIXME: don't commit zig crimes
+    const Type = struct {
+        fn inner(comptime TypeA: type, comptime TypeB: type) type {
+            return if (kind == .a) TypeA else TypeB;
+        }
+    }.inner;
+
+    return struct {
+        dispcnt: Type(DispcntA, DispcntB) = .{ .raw = 0x0000_0000 },
+
+        bg: [4]bg.Text = .{ .{}, .{}, .{}, .{} },
+
+        // TODO: Rename
+        scanline: Scanline,
+
+        pub fn init(allocator: std.mem.Allocator) !@This() {
+            return .{
+                .scanline = try Scanline.init(allocator),
+            };
+        }
+
+        pub fn deinit(self: @This(), allocator: std.mem.Allocator) void {
+            self.scanline.deinit(allocator);
+        }
+
+        pub fn drawScanline(self: *@This(), bus: *Bus, fb: *FrameBuffer) void {
+            const disp_mode = self.dispcnt.display_mode.read();
+
+            switch (disp_mode) {
+                0 => { // Display Off
+                    const buf = switch (kind) {
+                        .a => if (bus.ppu.io.powcnt.display_swap.read()) fb.top(.back) else fb.btm(.back),
+                        .b => if (bus.ppu.io.powcnt.display_swap.read()) fb.btm(.back) else fb.top(.back),
+                    };
+
+                    @memset(buf, 0xFF); // set everything to white
+                },
+                1 => {
+                    const bg_mode = self.dispcnt.bg_mode.read();
+                    const bg_enable = self.dispcnt.bg_enable.read();
+                    const scanline: u32 = bus.ppu.io.nds9.vcount.scanline.read();
+
+                    switch (bg_mode) {
+                        //  BG0     BG1     BG2     BG3
+                        //  Text/3D Text    Text    Text
+                        0 => {
+                            // TODO: Fetch Sprites
+
+                            for (0..4) |layer| {
+                                // TODO: Draw Sprites
+
+                                inline for (0..4) |i| {
+                                    if (layer == self.bg[i].cnt.priority.read() and (bg_enable >> i) & 1 == 1) self.drawBackground(i, bus);
+                                }
+                            }
+
+                            const buf = switch (kind) {
+                                .a => if (bus.ppu.io.powcnt.display_swap.read()) fb.top(.back) else fb.btm(.back),
+                                .b => if (bus.ppu.io.powcnt.display_swap.read()) fb.btm(.back) else fb.top(.back),
+                            };
+
+                            const scanline_buf = blk: {
+                                const rgba_ptr: *[width * height]u32 = @ptrCast(@alignCast(buf));
+                                break :blk rgba_ptr[width * scanline ..][0..width];
+                            };
+
+                            self.renderTextMode(bus.dbgRead(u16, 0x0500_0000), scanline_buf);
+                        },
+                        else => |mode| {
+                            log.err("TODO: Implement Mode {}", .{mode});
+                            @panic("fatal error");
+                        },
+                    }
+                },
+                2 => { // VRAM display
+                    if (kind == .b) return;
+                    // TODO: Master Brightness can still affect this mode
+
+                    const scanline: u32 = bus.ppu.io.nds9.vcount.scanline.read();
+                    const buf = if (bus.ppu.io.powcnt.display_swap.read()) fb.top(.back) else fb.btm(.back);
+
+                    const scanline_buf = blk: {
+                        const rgba_ptr: *[width * height]u32 = @ptrCast(@alignCast(buf));
+                        break :blk rgba_ptr[width * scanline ..][0..width];
+                    };
+
+                    const base_addr: u32 = 0x0680_0000 + (width * @sizeOf(u16)) * @as(u32, scanline);
+
+                    for (scanline_buf, 0..) |*rgba, i| {
+                        const addr = base_addr + @as(u32, @intCast(i)) * @sizeOf(u16);
+                        rgba.* = rgba888(bus.dbgRead(u16, addr));
+                    }
+                },
+                3 => {
+                    if (kind == .b) return;
+
+                    @panic("TODO: main memory display");
+                },
+            }
+        }
+
+        fn drawBackground(self: *@This(), comptime layer: u2, bus: *Bus) void {
+            const screen_base = blk: {
+                const bgcnt_off: u32 = self.bg[layer].cnt.screen_base.read();
+                const dispcnt_off: u32 = if (kind == .a) self.dispcnt.screen_base.read() else 0;
+
+                break :blk (2 * KiB) * bgcnt_off + (64 * KiB) * dispcnt_off;
+            };
+
+            const char_base = blk: {
+                const bgcnt_off: u32 = self.bg[layer].cnt.char_base.read();
+                const dispcnt_off: u32 = if (kind == .a) self.dispcnt.char_base.read() else 0;
+
+                break :blk (16 * KiB) * bgcnt_off + (64 * KiB) * dispcnt_off;
+            };
+
+            const is_8bpp = self.bg[layer].cnt.colour_mode.read();
+            const size = self.bg[layer].cnt.size.read();
+
+            // In 4bpp: 1 byte represents two pixels so the length is (8 x 8) / 2
+            // In 8bpp: 1 byte represents one pixel so the length is 8 x 8
+            const tile_len: u32 = if (is_8bpp) 0x40 else 0x20;
+            const tile_row_offset: u32 = if (is_8bpp) 0x8 else 0x4;
+
+            const vofs: u32 = self.bg[layer].vofs.offset.read();
+            const hofs: u32 = self.bg[layer].hofs.offset.read();
+
+            const y: u32 = vofs + bus.ppu.io.nds9.vcount.scanline.read();
+
+            for (0..width) |idx| {
+                const i: u32 = @intCast(idx);
+                const x = hofs + i;
+
+                // TODO: Windowing
+
+                // Grab the Screen Entry from VRAM
+                const entry_addr = screen_base + tilemapOffset(size, x, y);
+                const entry: bg.Screen.Entry = @bitCast(bus.read(u16, 0x0600_0000 + entry_addr));
+
+                // Calculate the Address of the Tile in the designated Charblock
+                // We also take this opportunity to flip tiles if necessary
+                const tile_id: u32 = entry.tile_id.read();
+
+                // Calculate row and column offsets. Understand that
+                // `tile_len`, `tile_row_offset` and `col` are subject to different
+                // values depending on whether we are in 4bpp or 8bpp mode.
+                const row = @as(u3, @truncate(y)) ^ if (entry.v_flip.read()) 7 else @as(u3, 0);
+                const col = @as(u3, @truncate(x)) ^ if (entry.h_flip.read()) 7 else @as(u3, 0);
+                const tile_addr = char_base + (tile_id * tile_len) + (row * tile_row_offset) + if (is_8bpp) col else col >> 1;
+
+                const tile = bus.read(u8, 0x0600_0000 + tile_addr);
+                // If we're in 8bpp, then the tile value is an index into the palette,
+                // If we're in 4bpp, we have to account for a pal bank value in the Screen entry
+                // and then we can index the palette
+                const pal_addr: u32 = if (!is_8bpp) get4bppTilePalette(entry.pal_bank.read(), col, tile) else tile;
+
+                if (pal_addr != 0) {
+                    self.drawBackgroundPixel(layer, i, bus.read(u16, 0x0500_0000 + pal_addr * 2));
+                }
+            }
+        }
+
+        inline fn get4bppTilePalette(pal_bank: u4, col: u3, tile: u8) u8 {
+            const nybble_tile = tile >> ((col & 1) << 2) & 0xF;
+            if (nybble_tile == 0) return 0;
+
+            return (@as(u8, pal_bank) << 4) | nybble_tile;
+        }
+
+        fn renderTextMode(self: *@This(), backdrop: u16, frame_buf: []u32) void {
+            for (self.scanline.top(), self.scanline.btm(), frame_buf) |maybe_top, maybe_btm, *rgba| {
+                _ = maybe_btm;
+
+                const bgr555 = switch (maybe_top) {
+                    .set => |px| px,
+                    else => backdrop,
+                };
+
+                rgba.* = rgba888(bgr555);
+            }
+
+            self.scanline.reset();
+        }
+
+        // TODO: Comment this + get a better understanding
+        fn tilemapOffset(size: u2, x: u32, y: u32) u32 {
+            // Current Row: (y % PIXEL_COUNT) / 8
+            // Current COlumn: (x % PIXEL_COUNT) / 8
+            // Length of 1 row of Screen Entries: 0x40
+            // Length of 1 Screen Entry: 0x2 is the size of a screen entry
+            @setRuntimeSafety(false);
+
+            return switch (size) {
+                0 => (x % 256 / 8) * 2 + (y % 256 / 8) * 0x40, // 256 x 256
+                1 => blk: {
+                    // 512 x 256
+                    const offset: u32 = if (x & 0x1FF > 0xFF) 0x800 else 0;
+                    break :blk offset + (x % 256 / 8) * 2 + (y % 256 / 8) * 0x40;
+                },
+                2 => blk: {
+                    // 256 x 512
+                    const offset: u32 = if (y & 0x1FF > 0xFF) 0x800 else 0;
+                    break :blk offset + (x % 256 / 8) * 2 + (y % 256 / 8) * 0x40;
+                },
+                3 => blk: {
+                    // 512 x 512
+                    const offset: u32 = if (x & 0x1FF > 0xFF) 0x800 else 0;
+                    const offset_2: u32 = if (y & 0x1FF > 0xFF) 0x800 else 0;
+                    break :blk offset + offset_2 + (x % 256 / 8) * 2 + (y % 512 / 8) * 0x40;
+                },
+            };
+        }
+
+        fn drawBackgroundPixel(self: *@This(), comptime layer: u2, i: u32, bgr555: u16) void {
+            _ = layer;
+
+            self.scanline.top()[i] = Scanline.Pixel.from(.Background, bgr555);
+        }
+    };
+}
+
+const Scanline = struct {
+    const Pixel = union(enum) {
+        // TODO: Rename
+        const Layer = enum { Background, Sprite };
+
+        set: u16,
+        obj_set: u16,
+        unset: void,
+        hidden: void,
+
+        fn from(comptime layer: Layer, bgr555: u16) Pixel {
+            return switch (layer) {
+                .Background => .{ .set = bgr555 },
+                .Sprite => .{ .obj_set = bgr555 },
+            };
+        }
+
+        pub fn isSet(self: @This()) bool {
+            return switch (self) {
+                .set, .obj_set => true,
+                .unset, .hidden => false,
+            };
+        }
+    };
+
+    layers: [2][]Pixel,
+    buf: []Pixel,
+
+    fn init(allocator: std.mem.Allocator) !@This() {
+        const buf = try allocator.alloc(Pixel, width * 2); // Top & Bottom Scanline
+        @memset(buf, .unset);
+
+        return .{
+            // Top & Bototm Layers
+            .layers = [_][]Pixel{ buf[0..][0..width], buf[width..][0..width] },
+            .buf = buf,
+        };
+    }
+
+    fn reset(self: *@This()) void {
+        @memset(self.buf, .unset);
+    }
+
+    fn deinit(self: @This(), allocator: std.mem.Allocator) void {
+        allocator.free(self.buf);
+    }
+
+    fn top(self: *@This()) []Pixel {
+        return self.layers[0];
+    }
+
+    fn btm(self: *@This()) []Pixel {
+        return self.layers[1];
+    }
+};
+
+const bg = struct {
+    const Text = struct {
+        const io = @import("../nds9/io.zig");
+
+        /// Read / Write
+        cnt: io.Bgcnt = .{ .raw = 0x0000 },
+        /// Write Only
+        hofs: io.Hofs = .{ .raw = 0x0000 },
+        /// Write Only
+        vofs: io.Vofs = .{ .raw = 0x0000 },
+    };
+
+    const Screen = struct {
+        const Entry = extern union {
+            const Bitfield = @import("bitfield").Bitfield;
+            const Bit = @import("bitfield").Bit;
+
+            tile_id: Bitfield(u16, 0, 10),
+            h_flip: Bit(u16, 10),
+            v_flip: Bit(u16, 11),
+            pal_bank: Bitfield(u16, 12, 4),
+            raw: u16,
+        };
+    };
+
+    const Affine = @compileError("TODO: Implement Affine Backgrounds");
+};
+
+inline fn rgba888(bgr555: u16) u32 {
+    const b: u32 = bgr555 >> 10 & 0x1F;
+    const g: u32 = bgr555 >> 5 & 0x1F;
+    const r: u32 = bgr555 & 0x1F;
+
+    // zig fmt: off
+    return (r << 3 | r >> 2) << 24
+        |  (g << 3 | g >> 2) << 16
+        |  (b << 3 | b >> 2) << 8
+        |  0xFF;
+    // zig fmt: on
+}

src/main.zig

@@ -51,6 +51,9 @@ pub fn main() !void {
         var bus7 = try System.Bus7.init(allocator, &scheduler, ctx);
         var bus9 = try System.Bus9.init(allocator, &scheduler, ctx);
 
+        // TODO: Think of a better way to do this
+        bus7.io.configure(&bus9.ppu);
+
         var arm7tdmi = System.Arm7tdmi.init(IScheduler.init(&scheduler), IBus.init(&bus7));
         var arm946es = System.Arm946es.init(IScheduler.init(&scheduler), IBus.init(&bus9), ICoprocessor.init(&cp15));
 
@@ -62,6 +65,8 @@ pub fn main() !void {
     const rom_title = try emu.load(allocator, system, rom_path);
     if (firm_path) |path| try emu.loadFirm(allocator, system, path);
 
+    emu.fastBoot(system);
+
     var ui = try Ui.init(allocator);
     defer ui.deinit(allocator);
 

src/platform.zig

@@ -8,7 +8,7 @@ const imgui = @import("ui/imgui.zig");
 const emu = @import("core/emu.zig");
 
 const System = @import("core/emu.zig").System;
-const KeyInput = @import("core/nds9/io.zig").KeyInput;
+const KeyInput = @import("core/io.zig").KeyInput;
 const Scheduler = @import("core/Scheduler.zig");
 
 const Allocator = std.mem.Allocator;
@@ -141,7 +141,7 @@ pub const Ui = struct {
                             else => {},
                         }
 
-                        system.bus9.io.keyinput.fetchAnd(~keyinput.raw, .Monotonic);
+                        system.bus9.io.shr.keyinput.fetchAnd(~keyinput.raw, .Monotonic);
                     },
                     SDL.SDL_KEYUP => {
                         // TODO: Make use of compare_and_xor?
@@ -162,7 +162,7 @@ pub const Ui = struct {
                             else => {},
                         }
 
-                        system.bus9.io.keyinput.fetchOr(keyinput.raw, .Monotonic);
+                        system.bus9.io.shr.keyinput.fetchOr(keyinput.raw, .Monotonic);
                     },
                     else => {},
                 }