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fix: pass more test roms

This commit is contained in:
Rekai Nyangadzayi Musuka 2023-12-27 16:29:23 -06:00
parent 51076597e8
commit f55b733646
2 changed files with 9 additions and 1 deletions
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2
src/core/nds9/dma.zig
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@ -219,7 +219,7 @@ fn Controller(comptime id: u2) type {
const start_timing: Kind = @enumFromInt(new.start_timing.read());
switch (start_timing) {
.immediate, .vblank => {},
.immediate, .vblank, .hblank => {},
else => log.err("TODO: Implement DMA({}) {s} mode", .{ id, @tagName(start_timing) }),
}

8
src/core/nds9/io.zig
View File

@ -65,6 +65,7 @@ pub fn read(bus: *const Bus, comptime T: type, address: u32) T {
0x0400_0210 => bus.io.ie.raw,
0x0400_0214 => bus.io.irq.raw,
0x0400_0280 => bus.io.div.cnt.raw,
0x0400_02A0, 0x0400_02A4 => @truncate(bus.io.div.result >> shift(u64, address)),
0x0400_02A8, 0x0400_02AC => @truncate(bus.io.div.remainder >> shift(u64, address)),
0x0400_02B4 => @truncate(bus.io.sqrt.result),
@ -175,6 +176,8 @@ pub fn write(bus: *Bus, comptime T: type, address: u32, value: T) void {
bus.wram.update(bus.io.shr.wramcnt);
},
0x0400_0280 => bus.io.div.cnt.raw = value,
0x0400_0290, 0x0400_0294 => {
bus.io.div.numerator = subset(u64, u32, address, bus.io.div.numerator, value);
bus.io.div.schedule(bus.scheduler);
@ -185,6 +188,11 @@ pub fn write(bus: *Bus, comptime T: type, address: u32, value: T) void {
bus.io.div.schedule(bus.scheduler);
},
0x0400_02A0, 0x0400_02A4 => bus.io.div.result = subset(u64, u32, address, bus.io.div.result, value),
0x0400_02A8, 0x0400_02AC => bus.io.div.remainder = subset(u64, u32, address, bus.io.div.remainder, value),
0x0400_02B0 => bus.io.sqrt.cnt.raw = value,
0x0400_02B8, 0x0400_02BC => {
bus.io.sqrt.param = subset(u64, u32, address, bus.io.sqrt.param, value);
bus.io.sqrt.schedule(bus.scheduler);