diff --git a/src/core/nds9/dma.zig b/src/core/nds9/dma.zig index 6a281f2..fb1ab39 100644 --- a/src/core/nds9/dma.zig +++ b/src/core/nds9/dma.zig @@ -219,7 +219,7 @@ fn Controller(comptime id: u2) type { const start_timing: Kind = @enumFromInt(new.start_timing.read()); switch (start_timing) { - .immediate, .vblank => {}, + .immediate, .vblank, .hblank => {}, else => log.err("TODO: Implement DMA({}) {s} mode", .{ id, @tagName(start_timing) }), } diff --git a/src/core/nds9/io.zig b/src/core/nds9/io.zig index c776aca..30e698c 100644 --- a/src/core/nds9/io.zig +++ b/src/core/nds9/io.zig @@ -65,6 +65,7 @@ pub fn read(bus: *const Bus, comptime T: type, address: u32) T { 0x0400_0210 => bus.io.ie.raw, 0x0400_0214 => bus.io.irq.raw, + 0x0400_0280 => bus.io.div.cnt.raw, 0x0400_02A0, 0x0400_02A4 => @truncate(bus.io.div.result >> shift(u64, address)), 0x0400_02A8, 0x0400_02AC => @truncate(bus.io.div.remainder >> shift(u64, address)), 0x0400_02B4 => @truncate(bus.io.sqrt.result), @@ -175,6 +176,8 @@ pub fn write(bus: *Bus, comptime T: type, address: u32, value: T) void { bus.wram.update(bus.io.shr.wramcnt); }, + 0x0400_0280 => bus.io.div.cnt.raw = value, + 0x0400_0290, 0x0400_0294 => { bus.io.div.numerator = subset(u64, u32, address, bus.io.div.numerator, value); bus.io.div.schedule(bus.scheduler); @@ -185,6 +188,11 @@ pub fn write(bus: *Bus, comptime T: type, address: u32, value: T) void { bus.io.div.schedule(bus.scheduler); }, + 0x0400_02A0, 0x0400_02A4 => bus.io.div.result = subset(u64, u32, address, bus.io.div.result, value), + 0x0400_02A8, 0x0400_02AC => bus.io.div.remainder = subset(u64, u32, address, bus.io.div.remainder, value), + + 0x0400_02B0 => bus.io.sqrt.cnt.raw = value, + 0x0400_02B8, 0x0400_02BC => { bus.io.sqrt.param = subset(u64, u32, address, bus.io.sqrt.param, value); bus.io.sqrt.schedule(bus.scheduler);