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chore: upgrade to Zig v2024.1.0-mach

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This commit is contained in:
Rekai Nyangadzayi Musuka
2024-02-12 18:24:43 -06:00
parent 62db837442
commit 0ad017cf43
18 changed files with 94 additions and 69 deletions
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2
src/core/emu.zig
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@@ -407,7 +407,7 @@ pub fn fastBoot(system: System) void {
pub const debug = struct {
const Interface = @import("gdbstub").Emulator;
const Server = @import("gdbstub").Server;
const AtomicBool = std.atomic.Atomic(bool);
const AtomicBool = std.atomic.Value(bool);
const log = std.log.scoped(.gdbstub);
const nds7 = struct {

16
src/core/io.zig
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@@ -415,22 +415,22 @@ pub const KeyInput = extern union {
const AtomicKeyInput = struct {
const Self = @This();
const Ordering = std.atomic.Ordering;
const AtomicOrder = std.builtin.AtomicOrder;
inner: KeyInput = .{ .raw = 0x03FF },
pub inline fn load(self: *const Self, comptime ordering: Ordering) u16 {
return switch (ordering) {
pub inline fn load(self: *const Self, comptime order: AtomicOrder) u16 {
return switch (order) {
.AcqRel, .Release => @compileError("not supported for atomic loads"),
else => @atomicLoad(u16, &self.inner.raw, ordering),
else => @atomicLoad(u16, &self.inner.raw, order),
};
}
pub inline fn fetchOr(self: *Self, value: u16, comptime ordering: Ordering) void {
_ = @atomicRmw(u16, &self.inner.raw, .Or, value, ordering);
pub inline fn fetchOr(self: *Self, value: u16, comptime order: AtomicOrder) void {
_ = @atomicRmw(u16, &self.inner.raw, .Or, value, order);
}
pub inline fn fetchAnd(self: *Self, value: u16, comptime ordering: Ordering) void {
_ = @atomicRmw(u16, &self.inner.raw, .And, value, ordering);
pub inline fn fetchAnd(self: *Self, value: u16, comptime order: AtomicOrder) void {
_ = @atomicRmw(u16, &self.inner.raw, .And, value, order);
}
};

3
src/core/nds7/Bios.zig
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@@ -29,7 +29,6 @@ pub fn deinit(self: @This(), allocator: Allocator) void {
// Note: Parts of 16MiB addrspace that aren't mapped to BIOS are typically undefined
pub fn read(self: *const @This(), comptime T: type, address: u32) T {
const readInt = std.mem.readIntLittle;
const byte_count = @divExact(@typeInfo(T).Int.bits, 8);
// if (address >= len) return 0x0000_0000; // TODO: What is undefined actually?
@@ -39,7 +38,7 @@ pub fn read(self: *const @This(), comptime T: type, address: u32) T {
@panic("TODO: ability to load in NDS7 BIOS just-in-time");
};
return readInt(T, ptr[address & (len - 1) ..][0..byte_count]);
return std.mem.readInt(T, ptr[address & (len - 1) ..][0..byte_count], .little);
}
pub fn write(_: *const @This(), comptime T: type, address: u32, value: T) void {

15
src/core/nds7/Bus.zig
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@@ -62,8 +62,6 @@ pub fn dbgRead(self: *@This(), comptime T: type, address: u32) T {
fn _read(self: *@This(), comptime T: type, comptime mode: Mode, address: u32) T {
const byte_count = @divExact(@typeInfo(T).Int.bits, 8);
const readInt = std.mem.readIntLittle;
const aligned_addr = forceAlign(T, address);
switch (mode) {
@@ -74,12 +72,12 @@ fn _read(self: *@This(), comptime T: type, comptime mode: Mode, address: u32) T
return switch (aligned_addr) {
0x0000_0000...0x01FF_FFFF => self.bios.read(T, address),
0x0200_0000...0x02FF_FFFF => readInt(T, self.main[aligned_addr & 0x003F_FFFF ..][0..byte_count]),
0x0200_0000...0x02FF_FFFF => std.mem.readInt(T, self.main[aligned_addr & 0x003F_FFFF ..][0..byte_count], .little),
0x0300_0000...0x037F_FFFF => switch (self.io.shr.wramcnt.mode.read()) {
0b00 => readInt(T, self.wram[aligned_addr & 0x0000_FFFF ..][0..byte_count]),
0b00 => std.mem.readInt(T, self.wram[aligned_addr & 0x0000_FFFF ..][0..byte_count], .little),
else => self.shr_wram.read(T, .nds7, aligned_addr),
},
0x0380_0000...0x03FF_FFFF => readInt(T, self.wram[aligned_addr & 0x0000_FFFF ..][0..byte_count]),
0x0380_0000...0x03FF_FFFF => std.mem.readInt(T, self.wram[aligned_addr & 0x0000_FFFF ..][0..byte_count], .little),
0x0400_0000...0x04FF_FFFF => io.read(self, T, aligned_addr),
0x0600_0000...0x06FF_FFFF => self.vram.read(T, .nds7, aligned_addr),
@@ -97,7 +95,6 @@ pub fn dbgWrite(self: *@This(), comptime T: type, address: u32, value: T) void {
fn _write(self: *@This(), comptime T: type, comptime mode: Mode, address: u32, value: T) void {
const byte_count = @divExact(@typeInfo(T).Int.bits, 8);
const writeInt = std.mem.writeIntLittle;
const aligned_addr = forceAlign(T, address);
@@ -109,12 +106,12 @@ fn _write(self: *@This(), comptime T: type, comptime mode: Mode, address: u32, v
switch (aligned_addr) {
0x0000_0000...0x01FF_FFFF => self.bios.write(T, address, value),
0x0200_0000...0x02FF_FFFF => writeInt(T, self.main[aligned_addr & 0x003F_FFFF ..][0..byte_count], value),
0x0200_0000...0x02FF_FFFF => std.mem.writeInt(T, self.main[aligned_addr & 0x003F_FFFF ..][0..byte_count], value, .little),
0x0300_0000...0x037F_FFFF => switch (self.io.shr.wramcnt.mode.read()) {
0b00 => writeInt(T, self.wram[aligned_addr & 0x0000_FFFF ..][0..byte_count], value),
0b00 => std.mem.writeInt(T, self.wram[aligned_addr & 0x0000_FFFF ..][0..byte_count], value, .little),
else => self.shr_wram.write(T, .nds7, aligned_addr, value),
},
0x0380_0000...0x03FF_FFFF => writeInt(T, self.wram[aligned_addr & 0x0000_FFFF ..][0..byte_count], value),
0x0380_0000...0x03FF_FFFF => std.mem.writeInt(T, self.wram[aligned_addr & 0x0000_FFFF ..][0..byte_count], value, .little),
0x0400_0000...0x04FF_FFFF => io.write(self, T, aligned_addr, value),
0x0600_0000...0x06FF_FFFF => self.vram.write(T, .nds7, aligned_addr, value),
else => log.warn("unexpected: write(T: {}, addr: 0x{X:0>8}, value: 0x{X:0>8})", .{ T, address, value }),

3
src/core/nds9/Bios.zig
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@@ -31,7 +31,6 @@ pub fn deinit(self: @This(), allocator: Allocator) void {
// Note: Parts of 16MiB addrspace that aren't mapped to BIOS are typically undefined
pub fn read(self: *const @This(), comptime T: type, address: u32) T {
const readInt = std.mem.readIntLittle;
const byte_count = @divExact(@typeInfo(T).Int.bits, 8);
// if (address >= len) return 0x0000_0000; // TODO: What is undefined actually?
@@ -41,7 +40,7 @@ pub fn read(self: *const @This(), comptime T: type, address: u32) T {
@panic("TODO: ability to load in NDS9 BIOS just-in-time");
};
return readInt(T, ptr[address & (len - 1) ..][0..byte_count]);
return std.mem.readInt(T, ptr[address & (len - 1) ..][0..byte_count], .little);
}
pub fn write(_: *const @This(), comptime T: type, address: u32, value: T) void {

16
src/core/nds9/Bus.zig
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@@ -66,8 +66,6 @@ pub fn dbgRead(self: *@This(), comptime T: type, address: u32) T {
fn _read(self: *@This(), comptime T: type, comptime mode: Mode, address: u32) T {
const byte_count = @divExact(@typeInfo(T).Int.bits, 8);
const readInt = std.mem.readIntLittle;
const aligned_addr = forceAlign(T, address);
switch (mode) {
@@ -77,12 +75,12 @@ fn _read(self: *@This(), comptime T: type, comptime mode: Mode, address: u32) T
}
return switch (aligned_addr) {
0x0200_0000...0x02FF_FFFF => readInt(T, self.main[aligned_addr & (4 * MiB - 1) ..][0..byte_count]),
0x0200_0000...0x02FF_FFFF => std.mem.readInt(T, self.main[aligned_addr & (4 * MiB - 1) ..][0..byte_count], .little),
0x0300_0000...0x03FF_FFFF => self.wram.read(T, .nds9, aligned_addr),
0x0400_0000...0x04FF_FFFF => io.read(self, T, aligned_addr),
0x0500_0000...0x05FF_FFFF => readInt(T, self.makeshift_palram[aligned_addr & (2 * KiB - 1) ..][0..@sizeOf(T)]),
0x0500_0000...0x05FF_FFFF => std.mem.readInt(T, self.makeshift_palram[aligned_addr & (2 * KiB - 1) ..][0..@sizeOf(T)], .little),
0x0600_0000...0x06FF_FFFF => self.ppu.vram.read(T, .nds9, aligned_addr),
0x0700_0000...0x07FF_FFFF => readInt(T, self.ppu.oam.buf[aligned_addr & (2 * KiB - 1) ..][0..byte_count]),
0x0700_0000...0x07FF_FFFF => std.mem.readInt(T, self.ppu.oam.buf[aligned_addr & (2 * KiB - 1) ..][0..byte_count], .little),
0xFFFF_0000...0xFFFF_FFFF => self.bios.read(T, address),
else => warn("unexpected: read(T: {}, addr: 0x{X:0>8}) {} ", .{ T, address, T }),
};
@@ -98,8 +96,6 @@ pub fn dbgWrite(self: *@This(), comptime T: type, address: u32, value: T) void {
fn _write(self: *@This(), comptime T: type, comptime mode: Mode, address: u32, value: T) void {
const byte_count = @divExact(@typeInfo(T).Int.bits, 8);
const writeInt = std.mem.writeIntLittle;
const aligned_addr = forceAlign(T, address);
switch (mode) {
@@ -109,12 +105,12 @@ fn _write(self: *@This(), comptime T: type, comptime mode: Mode, address: u32, v
}
switch (aligned_addr) {
0x0200_0000...0x02FF_FFFF => writeInt(T, self.main[aligned_addr & (4 * MiB - 1) ..][0..byte_count], value),
0x0200_0000...0x02FF_FFFF => std.mem.writeInt(T, self.main[aligned_addr & (4 * MiB - 1) ..][0..byte_count], value, .little),
0x0300_0000...0x03FF_FFFF => self.wram.write(T, .nds9, aligned_addr, value),
0x0400_0000...0x04FF_FFFF => io.write(self, T, aligned_addr, value),
0x0500_0000...0x05FF_FFFF => writeInt(T, self.makeshift_palram[aligned_addr & (2 * KiB - 1) ..][0..@sizeOf(T)], value),
0x0500_0000...0x05FF_FFFF => std.mem.writeInt(T, self.makeshift_palram[aligned_addr & (2 * KiB - 1) ..][0..@sizeOf(T)], value, .little),
0x0600_0000...0x06FF_FFFF => self.ppu.vram.write(T, .nds9, aligned_addr, value),
0x0700_0000...0x07FF_FFFF => writeInt(T, self.ppu.oam.buf[aligned_addr & (2 * KiB - 1) ..][0..@sizeOf(T)], value),
0x0700_0000...0x07FF_FFFF => std.mem.writeInt(T, self.ppu.oam.buf[aligned_addr & (2 * KiB - 1) ..][0..@sizeOf(T)], value, .little),
0xFFFF_0000...0xFFFF_FFFF => self.bios.write(T, address, value),
else => log.warn("unexpected: write(T: {}, addr: 0x{X:0>8}, value: 0x{X:0>8})", .{ T, address, value }),
}

12
src/core/nds9/io.zig
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@@ -55,7 +55,7 @@ pub fn read(bus: *const Bus, comptime T: type, address: u32) T {
u32 => switch (address) {
// DMA Transfers
0x0400_00B0...0x0400_00DC => dma.read(T, &bus.dma, address) orelse 0x0000_0000,
0x0400_00E0...0x0400_00EC => std.mem.readIntLittle(T, bus.io.dma_fill[address & 0xF ..][0..@sizeOf(T)]),
0x0400_00E0...0x0400_00EC => std.mem.readInt(T, bus.io.dma_fill[address & 0xF ..][0..@sizeOf(T)], .little),
// Timers
0x0400_0100...0x0400_010C => warn("TODO: impl timer", .{}),
@@ -89,7 +89,7 @@ pub fn read(bus: *const Bus, comptime T: type, address: u32) T {
// DMA Transfers
0x0400_00B0...0x0400_00DE => dma.read(T, &bus.dma, address) orelse 0x0000,
0x0400_00E0...0x0400_00EE => std.mem.readIntLittle(T, bus.io.dma_fill[address & 0xF ..][0..@sizeOf(T)]),
0x0400_00E0...0x0400_00EE => std.mem.readInt(T, bus.io.dma_fill[address & 0xF ..][0..@sizeOf(T)], .little),
// Timers
0x0400_0100...0x0400_010E => warn("TODO: impl timer", .{}),
@@ -122,7 +122,7 @@ pub fn read(bus: *const Bus, comptime T: type, address: u32) T {
u8 => switch (address) {
// DMA Transfers
0x0400_00B0...0x0400_00DF => dma.read(T, &bus.dma, address) orelse 0x00,
0x0400_00E0...0x0400_00EF => std.mem.readIntLittle(T, bus.io.dma_fill[address & 0xF ..][0..@sizeOf(T)]),
0x0400_00E0...0x0400_00EF => std.mem.readInt(T, bus.io.dma_fill[address & 0xF ..][0..@sizeOf(T)], .little),
// Timers
0x0400_0100...0x0400_010F => warn("TODO: impl timer", .{}),
@@ -170,7 +170,7 @@ pub fn write(bus: *Bus, comptime T: type, address: u32, value: T) void {
// DMA Transfers
0x0400_00B0...0x0400_00DC => dma.write(T, &bus.dma, address, value),
0x0400_00E0...0x0400_00EC => std.mem.writeIntLittle(T, bus.io.dma_fill[address & 0xF ..][0..@sizeOf(T)], value),
0x0400_00E0...0x0400_00EC => std.mem.writeInt(T, bus.io.dma_fill[address & 0xF ..][0..@sizeOf(T)], value, .little),
// Timers
0x0400_0100...0x0400_010C => log.warn("TODO: impl timer", .{}),
@@ -262,7 +262,7 @@ pub fn write(bus: *Bus, comptime T: type, address: u32, value: T) void {
// DMA Transfers
0x0400_00B0...0x0400_00DE => dma.write(T, &bus.dma, address, value),
0x0400_00E0...0x0400_00EE => std.mem.writeIntLittle(T, bus.io.dma_fill[address & 0xF ..][0..@sizeOf(T)], value),
0x0400_00E0...0x0400_00EE => std.mem.writeInt(T, bus.io.dma_fill[address & 0xF ..][0..@sizeOf(T)], value, .little),
// Timers
0x0400_0100...0x0400_010E => log.warn("TODO: impl timer", .{}),
@@ -302,7 +302,7 @@ pub fn write(bus: *Bus, comptime T: type, address: u32, value: T) void {
u8 => switch (address) {
// DMA Transfers
0x0400_00B0...0x0400_00DF => dma.write(T, &bus.dma, address, value),
0x0400_00E0...0x0400_00EF => std.mem.writeIntLittle(T, bus.io.dma_fill[address & 0xF ..][0..@sizeOf(T)], value),
0x0400_00E0...0x0400_00EF => std.mem.writeInt(T, bus.io.dma_fill[address & 0xF ..][0..@sizeOf(T)], value, .little),
// Timers
0x0400_0100...0x0400_010F => log.warn("TODO: impl timer", .{}),

4
src/main.zig
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@@ -27,7 +27,7 @@ pub fn main() !void {
const allocator = gpa.allocator();
const result = try clap.parse(clap.Help, &cli_params, clap.parsers.default, .{});
const result = try clap.parse(clap.Help, &cli_params, clap.parsers.default, .{ .allocator = allocator });
defer result.deinit();
const rom_path = try handlePositional(result);
@@ -75,7 +75,7 @@ pub fn main() !void {
ui.setTitle(rom_title);
try ui.run(&scheduler, system);
} else {
var should_quit: std.atomic.Atomic(bool) = std.atomic.Atomic(bool).init(false);
var should_quit: std.atomic.Value(bool) = std.atomic.Value(bool).init(false);
try emu.debug.run(allocator, system, &scheduler, &should_quit);
}

2
src/platform.zig
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@@ -33,7 +33,7 @@ pub const Ui = struct {
state: imgui.State,
pub fn init(allocator: Allocator) !Self {
var state = imgui.State{};
const state = imgui.State{};
if (SDL.SDL_Init(SDL.SDL_INIT_VIDEO | SDL.SDL_INIT_EVENTS | SDL.SDL_INIT_AUDIO) < 0) panic();
if (SDL.SDL_GL_SetAttribute(SDL.SDL_GL_CONTEXT_PROFILE_MASK, SDL.SDL_GL_CONTEXT_PROFILE_CORE) < 0) panic();