398 lines
14 KiB
Rust
398 lines
14 KiB
Rust
use crate::apu::Apu;
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use crate::cartridge::Cartridge;
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use crate::high_ram::HighRam;
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use crate::interrupt::{Interrupt, InterruptFlag};
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use crate::joypad::Joypad;
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use crate::ppu::{Ppu, PpuMode};
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use crate::serial::Serial;
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use crate::timer::Timer;
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use crate::work_ram::{VariableWorkRam, WorkRam};
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pub(crate) const BOOT_SIZE: usize = 0x100;
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#[derive(Debug, Default)]
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pub struct Bus {
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boot: Option<[u8; BOOT_SIZE]>, // Boot ROM is 256b long
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pub(crate) cart: Option<Cartridge>,
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pub(crate) ppu: Ppu,
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work_ram: WorkRam,
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var_ram: VariableWorkRam,
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timer: Timer,
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int: Interrupt,
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pub(crate) apu: Apu,
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high_ram: HighRam,
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serial: Serial,
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pub(crate) joyp: Joypad,
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}
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impl Bus {
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pub(crate) fn with_boot(rom: [u8; 256]) -> Self {
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Self {
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boot: Some(rom),
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..Default::default()
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}
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}
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#[allow(dead_code)]
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pub(crate) fn boot_mapped(&self) -> bool {
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self.boot.is_some()
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}
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#[inline]
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pub(crate) fn clock(&mut self) {
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self.tick(4);
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}
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#[inline]
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fn tick(&mut self, limit: u8) {
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for _ in 0..limit {
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self.timer.tick();
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if let Some(c) = self.cart.as_mut() {
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c.tick()
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}
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self.ppu.tick();
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self.apu.tick(self.timer.divider);
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self.dma_tick()
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}
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}
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fn dma_tick(&mut self) {
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if let Some((src_addr, dest_addr)) = self.ppu.dma.tick() {
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let byte = self.oam_read_byte(src_addr);
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self.oam_write_byte(dest_addr, byte);
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}
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}
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}
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impl Bus {
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pub(crate) fn oam_read_byte(&self, addr: u16) -> u8 {
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match addr {
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0x0000..=0x7FFF => {
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// 16KB ROM bank 00 (ends at 0x3FFF)
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// and 16KB ROM Bank 01 -> NN (switchable via MB)
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if addr < 0x100 {
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if let Some(boot) = self.boot {
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return boot[addr as usize];
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}
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}
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match self.cart.as_ref() {
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Some(cart) => cart.read_byte(addr),
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None => 0xFF,
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}
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}
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0x8000..=0x9FFF => self.ppu.read_byte(addr), // 8KB Video RAM
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0xA000..=0xBFFF => match self.cart.as_ref() {
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// 8KB External RAM
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Some(cart) => cart.read_byte(addr),
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None => 0xFF,
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},
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0xC000..=0xCFFF => self.work_ram.read_byte(addr), // 4KB Work RAM Bank 0
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0xD000..=0xDFFF => self.var_ram.read_byte(addr), // 4KB Work RAM Bank 1 -> N
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0xE000..=0xFDFF => {
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// Mirror of 0xC000 to 0xDDFF (ECHO RAM)
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let masked_addr = addr & 0x1FFF;
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let equiv_addr = 0xC000 + masked_addr;
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match masked_addr {
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// 0xE000 ..= 0xEFFF
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0x0000..=0x0FFF => {
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// 4KB Work RAM Bank 0
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self.work_ram.read_byte(equiv_addr)
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}
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// 0xF000 ..= 0xFDFF
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0x1000..=0x1DFF => {
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// 4KB Work RAM Bank 1 -> N
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self.var_ram.read_byte(equiv_addr)
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}
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_ => unreachable!("{:#06X} was incorrectly handled by ECHO RAM", addr),
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}
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}
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_ => panic!("OAM Transfer abnormally tried reading from {:#06X}", addr),
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}
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}
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pub(crate) fn oam_write_byte(&mut self, addr: u16, byte: u8) {
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self.ppu.oam.write_byte(addr, byte);
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}
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}
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impl BusIo for Bus {
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fn read_byte(&self, addr: u16) -> u8 {
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match addr {
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0x0000..=0x7FFF => {
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// 16KB ROM bank 00 (ends at 0x3FFF)
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// and 16KB ROM Bank 01 -> NN (switchable via MB)
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if addr < 0x100 {
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if let Some(boot) = self.boot {
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return boot[addr as usize];
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}
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}
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match self.cart.as_ref() {
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Some(cart) => cart.read_byte(addr),
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None => 0xFF,
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}
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}
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0x8000..=0x9FFF => {
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// 8KB Video RAM
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match self.ppu.stat.mode() {
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PpuMode::Drawing => 0xFF,
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_ => self.ppu.read_byte(addr),
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}
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}
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0xA000..=0xBFFF => match self.cart.as_ref() {
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// 8KB External RAM
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Some(cart) => cart.read_byte(addr),
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None => 0xFF,
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},
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0xC000..=0xCFFF => self.work_ram.read_byte(addr), // 4KB Work RAM Bank 0
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0xD000..=0xDFFF => self.var_ram.read_byte(addr), // 4KB Work RAM Bank 1 -> N
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0xE000..=0xFDFF => {
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// Mirror of 0xC000 to 0xDDFF (ECHO RAM)
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let masked_addr = addr & 0x1FFF;
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let equiv_addr = 0xC000 + masked_addr;
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match masked_addr {
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// 0xE000 ..= 0xEFFF
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0x0000..=0x0FFF => {
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// 4KB Work RAM Bank 0
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self.work_ram.read_byte(equiv_addr)
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}
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// 0xF000 ..= 0xFDFF
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0x1000..=0x1DFF => {
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// 4KB Work RAM Bank 1 -> N
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self.var_ram.read_byte(equiv_addr)
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}
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_ => unreachable!("{:#06X} was incorrectly handled by ECHO RAM", addr),
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}
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}
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0xFE00..=0xFE9F => {
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// Sprite Attribute Table
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use PpuMode::{HBlank, VBlank};
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match self.ppu.stat.mode() {
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HBlank | VBlank => self.ppu.oam.read_byte(addr),
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_ => 0xFF,
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}
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}
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0xFEA0..=0xFEFF => {
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// Prohibited Memory
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use PpuMode::{HBlank, VBlank};
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match self.ppu.stat.mode() {
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HBlank | VBlank => 0x00,
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_ => 0xFF, // TODO: OAM Sprite bug now occurs on the DMG
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}
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}
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0xFF00..=0xFF7F => {
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// IO Registers
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// Every address here starts with 0xFF so we can just check the
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// low byte to figure out which register it is
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match addr & 0x00FF {
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0x00 => self.joyp.p1,
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0x01 => self.serial.next,
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0x02 => self.serial.ctrl.into(),
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0x04 => (self.timer.divider >> 8) as u8,
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0x05 => self.timer.tima(),
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0x06 => self.timer.modulo,
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0x07 => self.timer.ctrl.into(),
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0x0F => self.interrupt_flag().into(),
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0x10..=0x3F => self.apu.read_byte(addr),
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0x40 => self.ppu.ctrl.into(),
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0x41 => self.ppu.stat.into(),
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0x42 => self.ppu.pos.scroll_y,
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0x43 => self.ppu.pos.scroll_x,
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0x44 => self.ppu.pos.line_y,
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0x45 => self.ppu.pos.ly_compare as u8,
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0x46 => self.ppu.dma.start.into(),
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0x47 => self.ppu.monochrome.bg_palette.into(),
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0x48 => self.ppu.monochrome.obj_palette_0.into(),
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0x49 => self.ppu.monochrome.obj_palette_1.into(),
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0x4A => self.ppu.pos.window_y,
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0x4B => self.ppu.pos.window_x,
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0x4F => 0xFF, // CGB VRAM Bank Select
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_ => {
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tracing::warn!("Attempted read from {:#06X} on IO", addr);
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0xFF
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}
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}
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}
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0xFF80..=0xFFFE => {
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// High RAM
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self.high_ram.read_byte(addr)
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}
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0xFFFF => {
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// Interrupts Enable Register
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self.int.enable.into()
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}
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}
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}
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fn write_byte(&mut self, addr: u16, byte: u8) {
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match addr {
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0x0000..=0x7FFF => {
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// 16KB ROM bank 00 (ends at 0x3FFF)
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// and 16KB ROM Bank 01 -> NN (switchable via MB)
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if let Some(cart) = self.cart.as_mut() {
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cart.write_byte(addr, byte);
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}
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}
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0x8000..=0x9FFF => {
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// 8KB Video RAM
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match self.ppu.stat.mode() {
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PpuMode::Drawing => {}
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_ => self.ppu.write_byte(addr, byte),
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}
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}
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0xA000..=0xBFFF => {
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// 8KB External RAM
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if let Some(cart) = self.cart.as_mut() {
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cart.write_byte(addr, byte);
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}
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}
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0xC000..=0xCFFF => self.work_ram.write_byte(addr, byte), // 4KB Work RAM Bank 0
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0xD000..=0xDFFF => self.var_ram.write_byte(addr, byte), // 4KB Work RAM Bank 1 -> N
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0xE000..=0xFDFF => {
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// Mirror of 0xC000 to 0xDDFF (ECHO RAM)
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let masked_addr = addr & 0x1FFF;
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let equiv_addr = 0xC000 + masked_addr;
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match masked_addr {
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// 0xE000 ..= 0xEFFF
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0x0000..=0x0FFF => {
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// 4KB Work RAM Bank 0
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self.work_ram.write_byte(equiv_addr, byte);
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}
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// 0xF000 ..= 0xFDFF
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0x1000..=0x1DFF => {
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// 4KB Work RAM Bank 1 -> N
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self.var_ram.write_byte(equiv_addr, byte);
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}
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_ => unreachable!("{:#06X} was incorrectly handled by ECHO RAM", addr),
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}
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}
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0xFE00..=0xFE9F => {
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// Sprite Attribute Table
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use PpuMode::{HBlank, VBlank};
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match self.ppu.stat.mode() {
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HBlank | VBlank => self.ppu.oam.write_byte(addr, byte),
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_ => {}
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}
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}
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0xFEA0..=0xFEFF => {} // FIXME: As far as I know, writes to here do nothing.
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0xFF00..=0xFF7F => {
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// IO Registers
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// Every address here starts with 0xFF so we can just check the
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// low byte to figure out which register it is
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match addr & 0x00FF {
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0x00 => self.joyp.update(byte),
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0x01 => self.serial.next = byte,
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0x02 => self.serial.ctrl = byte.into(),
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0x04 => self.timer.divider = 0x0000,
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0x05 => self.timer.set_tima(byte),
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0x06 => self.timer.modulo = byte,
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0x07 => self.timer.ctrl = byte.into(),
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0x0F => self.set_interrupt_flag(byte),
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0x10..=0x3F => self.apu.write_byte(addr, byte),
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0x40 => self.ppu.ctrl = byte.into(),
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0x41 => self.ppu.stat.update(byte),
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0x42 => self.ppu.pos.scroll_y = byte,
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0x43 => self.ppu.pos.scroll_x = byte,
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0x44 => self.ppu.pos.line_y = byte,
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0x45 => {
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// Update LYC
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self.ppu.pos.ly_compare = byte;
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// Update Coincidence Flag
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let are_equal = self.ppu.pos.line_y == byte;
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self.ppu.stat.set_coincidence(are_equal);
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// If enabled, request a LCD STAT interrupt
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if self.ppu.stat.coincidence_int() && are_equal {
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self.ppu.int.set_lcd_stat(true);
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}
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}
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0x46 => self.ppu.dma.start.update(byte, &mut self.ppu.dma.state),
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0x47 => self.ppu.monochrome.bg_palette = byte.into(),
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0x48 => self.ppu.monochrome.obj_palette_0 = byte.into(),
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0x49 => self.ppu.monochrome.obj_palette_1 = byte.into(),
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0x4A => self.ppu.pos.window_y = byte,
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0x4B => self.ppu.pos.window_x = byte,
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0x4D => {} // CGB Specific Register
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0x4F => {} // CGB VRAM Bank Select
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0x50 => {
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// Disable Boot ROM
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if byte != 0 {
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self.boot = None;
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}
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}
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0x70 => {} // CGB WRAM Bank Select
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_ => tracing::warn!("Attempted write of {:#04X} to {:#06X} on IO", byte, addr),
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};
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}
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0xFF80..=0xFFFE => {
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// High RAM
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self.high_ram.write_byte(addr, byte);
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}
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0xFFFF => {
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// Interrupts Enable Register
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self.int.enable = byte.into();
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}
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}
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}
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}
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impl Bus {
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fn interrupt_flag(&self) -> InterruptFlag {
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// Read the current interrupt information from the PPU
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let vblank = self.ppu.int.vblank();
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let lcd_stat = self.ppu.int.lcd_stat();
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// Read the current interrupt information from the Joypad
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let joypad = self.joyp.interrupt();
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// Read the current interrupt information from the Timer
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let timer = self.timer.interrupt();
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// Copy the Interrupt Flag register 0xFF0F
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let mut flag = self.int.flag;
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// Update the flag to have the most accurate information
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flag.set_vblank(vblank);
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flag.set_lcd_stat(lcd_stat);
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flag.set_joypad(joypad);
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flag.set_timer(timer);
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flag
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}
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fn set_interrupt_flag(&mut self, byte: u8) {
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// Update the Interrupt register 0xFF0F
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self.int.flag = byte.into();
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let vblank = self.int.flag.vblank();
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let lcd_stat = self.int.flag.lcd_stat();
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let joypad = self.int.flag.joypad();
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let timer = self.int.flag.timer();
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// Update the PPU's instance of the following interrupts
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self.ppu.int.set_vblank(vblank);
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self.ppu.int.set_lcd_stat(lcd_stat);
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// Update the Joypad's instance of the following interrupts
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self.joyp.set_interrupt(joypad);
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// Update the Timer's instance of the following interrupts
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self.timer.set_interrupt(timer);
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}
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}
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pub(crate) trait BusIo {
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fn read_byte(&self, addr: u16) -> u8;
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fn write_byte(&mut self, addr: u16, byte: u8);
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}
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