6087e3b20b
chore: remove Cycle struct and begin scheduler design
2021-09-12 04:56:34 -03:00
8625bec059
feat: clock bus on instruction read-write
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continuous-integration/drone/push Build is failing
Commit also includes general work towards passing mem-timings.
Note: while cpu_instrs.gb passes, instr_timing.gb and mem_timing.gb both
are stuck in infinite loops (Currently, it seems like a timing issue).
This is a major regression that hopefully shouldn't last for too long.
2021-08-14 00:10:51 -05:00
7112cd15e3
chore(cpu): refactor SM83 implementation
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continuous-integration/drone/push Build is passing
Instruction::decode no longer requires mutable access to the CPU
2021-07-31 20:29:13 -05:00
9d0e099a97
chore: remove unnecessary derivations from structs
2021-07-28 00:09:07 -05:00
9b3a5d49d2
chore: update error messages in expect() calls
2021-07-08 18:50:58 -05:00
a904503b90
chore: document IO registers
2021-06-09 13:43:46 -05:00
e8e6c41dbe
fix(dma): initial version of dma transfer now works
2021-06-06 23:57:54 -05:00
d623800005
fix: apply clippy suggestions
2021-06-06 21:30:08 -05:00
878edd4082
chore: replace pub with pub(crate) when possible
2021-06-06 19:14:28 -05:00
b7b213b6b9
chore(bus): implement read/write blocks when dma is active
2021-06-05 20:53:35 -05:00
811a9f9cc9
feat(dma): implement non-working dma transfer
2021-06-04 13:47:06 -05:00
