Rekai Nyangadzayi Musuka
9d2fbd2427
chore: remove unecessary print statements
2021-04-05 01:20:03 -05:00
Rekai Nyangadzayi Musuka
748c32c446
fix(cpu): use enums only of maintaining IME register state
2021-04-05 01:10:03 -05:00
Rekai Nyangadzayi Musuka
77c7c610d0
chore(cpu): rename ImeSet to ImeEnabled
2021-04-05 00:53:46 -05:00
Rekai Nyangadzayi Musuka
a15a6a25b6
feat(cpu): properly implement EI instruction
2021-04-05 00:52:12 -05:00
Rekai Nyangadzayi Musuka
4ace092257
chore: update cargo.lock
2021-04-05 00:50:53 -05:00
Rekai Nyangadzayi Musuka
62bd88945f
chore: rename a couple of interrupt instances to "int" instead of
...
"interrupt"
2021-04-04 01:52:53 -05:00
Rekai Nyangadzayi Musuka
7c9bff61f6
fix(ppu): add missing check for enabled interrupt
2021-04-04 01:50:49 -05:00
Rekai Nyangadzayi Musuka
777abd1c10
chore: rename some symbols
2021-04-04 01:31:31 -05:00
Rekai Nyangadzayi Musuka
4dd7a0d9ce
chore: fix several clippy warnings
2021-04-04 01:19:39 -05:00
Rekai Nyangadzayi Musuka
cb1bcdb859
feat(cpu): implement DAA instruction
2021-04-04 01:03:44 -05:00
Rekai Nyangadzayi Musuka
25e44f3e49
chore: fix condition when logs are printed
2021-03-27 15:07:17 -05:00
Rekai Nyangadzayi Musuka
2b05571c49
chore: rename Cycles newtype to Cycle
2021-03-27 12:10:18 -05:00
Rekai Nyangadzayi Musuka
bce14348f8
feat: enable halt and rework timer registers
2021-03-27 11:56:47 -05:00
Rekai Nyangadzayi Musuka
2bf877d1ec
fix(cpu): Ensure mask the high bits of the flag register
...
There was a bug where POP AF returned 0x1301. In this example, the A
register would be set to 0x13, and the Flag register woud be set to
0x01, which is an invalid state considering only bits 4 -> 7 of the flag
register are used. This commit masks the flag register with & 0xF0
whenever it is read or written to so that we can ensure that only the
high bits can ever be potentially set
2021-03-26 20:25:30 -05:00
Rekai Nyangadzayi Musuka
15781b3d5a
fix(instructions): correct the flags being set in ADD HL, r16
2021-03-26 20:19:48 -05:00
Rekai Nyangadzayi Musuka
a6d5553035
fix(cartridge): reimplement apply_rom_size_bitmask
2021-03-26 20:18:49 -05:00
Rekai Nyangadzayi Musuka
a82e3d3372
feat: implement HALT behaviour
...
note: while the logic is there, the instruction currently does not do
anything because we don't halde it in Cpu::step(). The code that does is
currently commented out and there should be some underlying bugs still
present. Nevertheless it is a good start
2021-03-23 23:05:27 -05:00
Rekai Nyangadzayi Musuka
c16f318fd1
fix: remove unnecessary allocation when loading boot rom
2021-03-23 21:21:18 -05:00
Rekai Nyangadzayi Musuka
48ac8317a8
fix(bus): fix off by one error when reading from boot rom
2021-03-23 21:01:33 -05:00
Rekai Nyangadzayi Musuka
e5fb07c4d1
chore: refactor parts of instruction.rs
2021-03-23 20:22:11 -05:00
Rekai Nyangadzayi Musuka
501d93c37b
chore: clean up code in one instruction
2021-03-23 18:21:59 -05:00
Rekai Nyangadzayi Musuka
1b7d778c1d
chore: clean up some instruction code
2021-03-23 02:11:40 -05:00
Rekai Nyangadzayi Musuka
6f11640f24
chore: replace CALL instruction with RST in interrupt handler
2021-03-23 02:11:06 -05:00
Rekai Nyangadzayi Musuka
342e6616ac
chore: improve unreachable! and panic! error messages
2021-03-22 22:33:56 -05:00
Rekai Nyangadzayi Musuka
2813b762dd
chore: replace select unreachable! macros with todo! and unreachable!
2021-03-22 21:52:28 -05:00
Rekai Nyangadzayi Musuka
9301a36682
chore: remove all unwraps from the project
2021-03-22 21:48:12 -05:00
Rekai Nyangadzayi Musuka
45466a5733
feat: implement clap for cli and improve error messages
2021-03-22 21:41:22 -05:00
Rekai Nyangadzayi Musuka
d7d9fd857f
fix: squash bugs in cpu intrucion implementation
2021-03-21 21:16:23 -05:00
Rekai Nyangadzayi Musuka
8a1540c9e9
fix: replaced unnecessary &mut self with &self
2021-03-21 19:56:38 -05:00
Rekai Nyangadzayi Musuka
dc45688e4f
feat: implement timers
2021-03-21 03:03:03 -05:00
Rekai Nyangadzayi Musuka
4db6f1de6e
chore: move LR35902_CLOCK_SPEED to lib.rs
2021-03-21 02:10:56 -05:00
Rekai Nyangadzayi Musuka
b548610fdb
chore: re-enable scrolling
2021-03-21 02:08:29 -05:00
Rekai Nyangadzayi Musuka
fe586d77ac
feat: stub 0xFF05
2021-03-21 02:01:19 -05:00
Rekai Nyangadzayi Musuka
15da6cb7d2
fix: squash several bugs in MBC1 implementation
2021-03-21 01:52:29 -05:00
Rekai Nyangadzayi Musuka
5a42d76f1e
feat: implement LCDSTAT interrupt
2021-03-21 00:01:21 -05:00
Rekai Nyangadzayi Musuka
c64417fdce
fix: horizontally flip ppu so the Nin***** logo is readable
2021-03-20 23:24:06 -05:00
Rekai Nyangadzayi Musuka
7462061937
chore: be more specific with integer types
2021-03-20 22:19:55 -05:00
Rekai Nyangadzayi Musuka
f78651d8d7
feat: implement programmable background palette
2021-03-20 22:19:13 -05:00
Rekai Nyangadzayi Musuka
b213a6e545
feat: make 0xFF0F aware of joypad struct interrupt bool
2021-03-20 21:21:55 -05:00
Rekai Nyangadzayi Musuka
36e572b783
feat: implement Joypad register
2021-03-20 21:11:45 -05:00
Rekai Nyangadzayi Musuka
fc303b6265
chore: rename "as u8" to "as Self" when implementing From Trait
2021-03-20 21:10:48 -05:00
Rekai Nyangadzayi Musuka
cd0eac9d37
chore: improve code quality
...
Removed a lot of magic constants. Gave them descriptive variable names
2021-03-20 20:26:49 -05:00
Rekai Nyangadzayi Musuka
0f4dec8a38
feat: implement cpu timing for emulator
...
When running the GB Boot ROM, a garbled Nin***** logo will appear
2021-03-20 19:56:26 -05:00
Rekai Nyangadzayi Musuka
d76b3b6101
chore: make Cycles::new a const fn
2021-03-20 19:55:39 -05:00
Rekai Nyangadzayi Musuka
2401cf7190
chore: implement default for cycles
2021-03-20 19:55:02 -05:00
Rekai Nyangadzayi Musuka
f365633c1e
fix: allow for the ppu to modify interrupt flags
2021-03-20 19:53:56 -05:00
Rekai Nyangadzayi Musuka
f45c2439c1
chore: update dependencies
2021-03-20 17:49:36 -05:00
Rekai Nyangadzayi Musuka
558f9e7c72
feat: implement cpu interrupts
2021-03-18 21:07:19 -05:00
Rekai Nyangadzayi Musuka
fb38ef3f68
feat: emu slowly draws scanline to pixelbuffer
2021-03-18 21:06:57 -05:00
Rekai Nyangadzayi Musuka
4663e8c960
chore: unifty read_byte and write_byte across hardware
2021-03-17 00:29:36 -05:00
