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fix(cart): reset sub-cycle counting in RTC 

specifically when RTC S is written to
This commit is contained in:
Rekai Nyangadzayi Musuka 2021-11-07 13:05:41 -06:00
parent f2c49b398c
commit ebcd5bec5c
1 changed files with 5 additions and 1 deletions
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6
src/cartridge.rs
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@ -538,7 +538,11 @@ impl MBCIo for MBC3 {
self.memory[0x2000 * self.ram_bank as usize + (addr as usize - 0xA000)] = byte self.memory[0x2000 * self.ram_bank as usize + (addr as usize - 0xA000)] = byte
} }
Some(MBC3Device::Clock(rtc_reg)) if self.devs_enabled => match rtc_reg { Some(MBC3Device::Clock(rtc_reg)) if self.devs_enabled => match rtc_reg {
Second => self.rtc.sec = byte & 0x3F, Second => {
self.rtc.sec = byte & 0x3F;
// Writing to RTC S resets the internal sub-second counter
self.rtc.cycles = 0;
}
Minute => self.rtc.min = byte & 0x3F, Minute => self.rtc.min = byte & 0x3F,
Hour => self.rtc.hr = byte & 0x1F, Hour => self.rtc.hr = byte & 0x1F,
DayLow => self.rtc.day_low = byte & 0xFF, DayLow => self.rtc.day_low = byte & 0xFF,