chore(cart): improve code quality of RtcClock
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6f76571d6c
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@ -289,12 +289,12 @@ impl MBCIo for MBC1 {
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}
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}
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impl RtcTick for MBC1 {
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impl RtClockTick for MBC1 {
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fn tick(&mut self) {}
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}
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#[derive(Debug, Default, Clone, Copy)]
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struct Rtc {
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struct RtClock {
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/// 6-bit unsigned integer
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sec: u8,
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/// 6-bit unsigned integer
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@ -307,7 +307,7 @@ struct Rtc {
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cycles: Cycle,
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}
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impl Rtc {
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impl RtClock {
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fn inc_day(&mut self) {
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// TODO: Figure out order of operations, the brackets are a bit too defenseive here
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let days: u16 = (((self.day_high.ninth() as u16) << 8) | self.day_low as u16) + 1;
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@ -321,7 +321,7 @@ impl Rtc {
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}
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}
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impl RtcTick for Rtc {
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impl RtClockTick for RtClock {
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fn tick(&mut self) {
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// This is the sort of situation where you'd want to use a scheduler.
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if self.day_high.halt() {
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@ -353,7 +353,7 @@ impl RtcTick for Rtc {
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}
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}
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trait RtcTick {
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trait RtClockTick {
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fn tick(&mut self);
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}
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@ -393,7 +393,7 @@ impl From<DayHigh> for u8 {
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#[derive(Debug, Clone, Copy)]
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enum MBC3Device {
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ExternalRam,
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Rtc(RtcRegister),
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Clock(RtcRegister),
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}
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#[derive(Debug, Clone, Copy)]
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@ -420,8 +420,8 @@ struct MBC3 {
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prev_latch_write: Option<u8>,
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has_battery: bool,
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rtc: Rtc,
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rtc_latch: Option<Rtc>,
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rtc: RtClock,
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rtc_latch: Option<RtClock>,
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}
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impl MBC3 {
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@ -481,21 +481,18 @@ impl MBCIo for MBC3 {
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Some(MBC3Device::ExternalRam) if self.devs_enabled => {
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Value(self.memory[0x2000 * self.ram_bank as usize + (addr as usize - 0xA000)])
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}
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Some(MBC3Device::Rtc(rtc_reg)) if self.devs_enabled => Value(match rtc_reg {
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Second => self.rtc_latch.as_ref().map(|rtc| rtc.sec).unwrap_or(0xFF),
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Minute => self.rtc_latch.as_ref().map(|rtc| rtc.min).unwrap_or(0xFF),
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Hour => self.rtc_latch.as_ref().map(|rtc| rtc.hr).unwrap_or(0xFF),
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DayLow => self
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.rtc_latch
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Some(MBC3Device::Clock(reg)) if self.devs_enabled => Value(
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self.rtc_latch
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.as_ref()
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.map(|rtc| rtc.day_low)
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.map(|rtc| match reg {
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Second => rtc.sec,
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Minute => rtc.min,
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Hour => rtc.hr,
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DayLow => rtc.day_low,
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DayHigh => rtc.day_high.into(),
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})
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.unwrap_or(0xFF),
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DayHigh => self
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.rtc_latch
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.as_ref()
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.map(|rtc| rtc.day_high.into())
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.unwrap_or(0xFF),
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}),
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),
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_ => Value(0xFF),
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},
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_ => unreachable!("A read from {:#06X} should not be handled by MBC3", addr),
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@ -520,11 +517,11 @@ impl MBCIo for MBC3 {
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self.ram_bank = byte & 0x03;
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self.mapped = Some(MBC3Device::ExternalRam);
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}
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0x08 => self.mapped = Some(MBC3Device::Rtc(Second)),
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0x09 => self.mapped = Some(MBC3Device::Rtc(Minute)),
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0x0A => self.mapped = Some(MBC3Device::Rtc(Hour)),
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0x0B => self.mapped = Some(MBC3Device::Rtc(DayLow)),
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0x0C => self.mapped = Some(MBC3Device::Rtc(DayHigh)),
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0x08 => self.mapped = Some(MBC3Device::Clock(Second)),
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0x09 => self.mapped = Some(MBC3Device::Clock(Minute)),
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0x0A => self.mapped = Some(MBC3Device::Clock(Hour)),
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0x0B => self.mapped = Some(MBC3Device::Clock(DayLow)),
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0x0C => self.mapped = Some(MBC3Device::Clock(DayHigh)),
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_ => {}
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},
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@ -540,7 +537,7 @@ impl MBCIo for MBC3 {
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Some(MBC3Device::ExternalRam) if self.devs_enabled => {
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self.memory[0x2000 * self.ram_bank as usize + (addr as usize - 0xA000)] = byte
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}
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Some(MBC3Device::Rtc(rtc_reg)) if self.devs_enabled => match rtc_reg {
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Some(MBC3Device::Clock(rtc_reg)) if self.devs_enabled => match rtc_reg {
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Second => self.rtc.sec = byte & 0x3F,
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Minute => self.rtc.min = byte & 0x3F,
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Hour => self.rtc.hr = byte & 0x1F,
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@ -554,7 +551,7 @@ impl MBCIo for MBC3 {
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}
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}
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impl RtcTick for MBC3 {
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impl RtClockTick for MBC3 {
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fn tick(&mut self) {
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self.rtc.tick();
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}
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@ -647,7 +644,7 @@ impl MBCIo for MBC5 {
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}
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}
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impl RtcTick for MBC5 {
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impl RtClockTick for MBC5 {
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fn tick(&mut self) {}
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}
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@ -739,7 +736,7 @@ impl MBCIo for MBC2 {
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}
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}
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impl RtcTick for MBC2 {
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impl RtClockTick for MBC2 {
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fn tick(&mut self) {}
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}
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@ -766,11 +763,11 @@ impl MBCIo for NoMBC {
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}
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}
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impl RtcTick for NoMBC {
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impl RtClockTick for NoMBC {
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fn tick(&mut self) {}
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}
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trait MBCIo: Savable + RtcTick {
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trait MBCIo: Savable + RtClockTick {
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fn handle_read(&self, addr: u16) -> MBCResult;
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fn handle_write(&mut self, addr: u16, byte: u8);
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}
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