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Implement decode for all x=2 unprefixed opcodes

This commit is contained in:
Rekai Nyangadzayi Musuka 2020-08-24 00:42:16 -05:00
parent 378a559106
commit deec130381
1 changed files with 38 additions and 4 deletions
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42
src/instruction.rs
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@ -22,6 +22,13 @@ pub enum Instruction {
SCF, SCF,
CCF, CCF,
HALT, HALT,
ADC(Argument, Argument),
SUB,
SBC(Argument, Argument),
AND,
XOR,
OR,
CP,
} }
pub enum AllRegisters { pub enum AllRegisters {
@ -127,7 +134,7 @@ impl Instruction {
(0, 5, _, y, _) => Instruction::DEC(Self::table_r(y)), // DEC r[y] (0, 5, _, y, _) => Instruction::DEC(Self::table_r(y)), // DEC r[y]
(0, 6, _, y, _) => Instruction::LD( (0, 6, _, y, _) => Instruction::LD(
// LD r[y], n // LD r[y], n
Self::ld_table_r(y), Self::arg_table_r(y),
Argument::ImmediateByte(n), Argument::ImmediateByte(n),
), ),
(0, 7, _, 0, _) => Instruction::RLCA, (0, 7, _, 0, _) => Instruction::RLCA,
@ -141,9 +148,10 @@ impl Instruction {
(1, 6, _, 6, _) => Instruction::HALT, (1, 6, _, 6, _) => Instruction::HALT,
(1, z, _, y, _) => Instruction::LD( (1, z, _, y, _) => Instruction::LD(
// LD r[y], r[z] // LD r[y], r[z]
Self::ld_table_r(y), Self::arg_table_r(y),
Self::ld_table_r(z), Self::arg_table_r(z),
), ),
(2, z, _, y, _) => Self::table_alu(y, z),
_ => unreachable!(), _ => unreachable!(),
} }
} }
@ -152,7 +160,7 @@ impl Instruction {
unimplemented!() unimplemented!()
} }
fn ld_table_r(index: u8) -> Argument { fn arg_table_r(index: u8) -> Argument {
match Self::table_r(index) { match Self::table_r(index) {
AllRegisters::U8(register) => Argument::Register(register), AllRegisters::U8(register) => Argument::Register(register),
AllRegisters::IndirectHL => Argument::IndirectRegister(RegisterPair::HL), AllRegisters::IndirectHL => Argument::IndirectRegister(RegisterPair::HL),
@ -203,6 +211,32 @@ impl Instruction {
_ => unreachable!(), _ => unreachable!(),
} }
} }
fn table_alu(fn_index: u8, reg_index: u8) -> Instruction {
match fn_index {
0 => Instruction::ADD(
// ADD A, r[z]
Argument::Register(Register::A),
Self::arg_table_r(reg_index),
),
1 => Instruction::ADC(
// ADC A, r[z]
Argument::Register(Register::A),
Self::arg_table_r(reg_index),
),
2 => Instruction::SUB,
3 => Instruction::SBC(
// SBC A, r[z]
Argument::Register(Register::A),
Self::arg_table_r(reg_index),
),
4 => Instruction::AND,
5 => Instruction::XOR,
6 => Instruction::OR,
7 => Instruction::CP,
_ => unreachable!(),
}
}
} }
pub enum Condition { pub enum Condition {