From deec130381556119513745781a5c7ee4c16bf9cc Mon Sep 17 00:00:00 2001
From: Rekai Musuka <rekai@musuka.dev>
Date: Mon, 24 Aug 2020 00:42:16 -0500
Subject: [PATCH] Implement decode for all x=2 unprefixed opcodes

---
 src/instruction.rs | 42 ++++++++++++++++++++++++++++++++++++++----
 1 file changed, 38 insertions(+), 4 deletions(-)

diff --git a/src/instruction.rs b/src/instruction.rs
index d901c79..935ae58 100644
--- a/src/instruction.rs
+++ b/src/instruction.rs
@@ -22,6 +22,13 @@ pub enum Instruction {
     SCF,
     CCF,
     HALT,
+    ADC(Argument, Argument),
+    SUB,
+    SBC(Argument, Argument),
+    AND,
+    XOR,
+    OR,
+    CP,
 }
 
 pub enum AllRegisters {
@@ -127,7 +134,7 @@ impl Instruction {
             (0, 5, _, y, _) => Instruction::DEC(Self::table_r(y)),                     // DEC r[y]
             (0, 6, _, y, _) => Instruction::LD(
                 // LD r[y], n
-                Self::ld_table_r(y),
+                Self::arg_table_r(y),
                 Argument::ImmediateByte(n),
             ),
             (0, 7, _, 0, _) => Instruction::RLCA,
@@ -141,9 +148,10 @@ impl Instruction {
             (1, 6, _, 6, _) => Instruction::HALT,
             (1, z, _, y, _) => Instruction::LD(
                 // LD r[y], r[z]
-                Self::ld_table_r(y),
-                Self::ld_table_r(z),
+                Self::arg_table_r(y),
+                Self::arg_table_r(z),
             ),
+            (2, z, _, y, _) => Self::table_alu(y, z),
             _ => unreachable!(),
         }
     }
@@ -152,7 +160,7 @@ impl Instruction {
         unimplemented!()
     }
 
-    fn ld_table_r(index: u8) -> Argument {
+    fn arg_table_r(index: u8) -> Argument {
         match Self::table_r(index) {
             AllRegisters::U8(register) => Argument::Register(register),
             AllRegisters::IndirectHL => Argument::IndirectRegister(RegisterPair::HL),
@@ -203,6 +211,32 @@ impl Instruction {
             _ => unreachable!(),
         }
     }
+
+    fn table_alu(fn_index: u8, reg_index: u8) -> Instruction {
+        match fn_index {
+            0 => Instruction::ADD(
+                // ADD A, r[z]
+                Argument::Register(Register::A),
+                Self::arg_table_r(reg_index),
+            ),
+            1 => Instruction::ADC(
+                // ADC A, r[z]
+                Argument::Register(Register::A),
+                Self::arg_table_r(reg_index),
+            ),
+            2 => Instruction::SUB,
+            3 => Instruction::SBC(
+                // SBC A, r[z]
+                Argument::Register(Register::A),
+                Self::arg_table_r(reg_index),
+            ),
+            4 => Instruction::AND,
+            5 => Instruction::XOR,
+            6 => Instruction::OR,
+            7 => Instruction::CP,
+            _ => unreachable!(),
+        }
+    }
 }
 
 pub enum Condition {