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chore(cpu): move RST behaviour to a method

This commit is contained in:
Rekai Nyangadzayi Musuka 2021-04-07 23:05:03 -05:00
parent 0eb40a8109
commit cf3b79f0dc
2 changed files with 13 additions and 6 deletions
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4
src/cpu.rs
View File

@ -222,13 +222,13 @@ impl Cpu {
}; };
let _ = match vector { let _ = match vector {
Some(register) => { Some(address) => {
// Write the Changes to 0xFF0F and 0xFFFF registers // Write the Changes to 0xFF0F and 0xFFFF registers
self.write_byte(0xFF0F, req.into()); self.write_byte(0xFF0F, req.into());
// Disable all future interrupts // Disable all future interrupts
self.set_ime(ImeState::Disabled); self.set_ime(ImeState::Disabled);
self.execute(Instruction::RST(register)) Instruction::reset(self, address)
} }
None => Cycle::new(0), // NO Interrupts were enabled and / or requested None => Cycle::new(0), // NO Interrupts were enabled and / or requested
}; };

15
src/instruction.rs
View File

@ -1092,10 +1092,10 @@ impl Instruction {
} }
Instruction::RST(n) => { Instruction::RST(n) => {
// RST n | Push current address onto the stack, jump to 0x0000 + n // RST n | Push current address onto the stack, jump to 0x0000 + n
let addr = cpu.register_pair(RegisterPair::PC);
Self::push(cpu, addr); // The same behaviour will occur when handling an interrupt so this code
cpu.set_register_pair(RegisterPair::PC, n as u16); // is relegated to a method
Cycle::new(16) Self::reset(cpu, n)
} }
Instruction::RLC(reg) => { Instruction::RLC(reg) => {
// RLC r[z] | Rotate register r[z] left // RLC r[z] | Rotate register r[z] left
@ -1614,6 +1614,13 @@ impl Instruction {
(lower << 4) | upper (lower << 4) | upper
} }
pub fn reset(cpu: &mut Cpu, vector: u8) -> Cycle {
let addr = cpu.register_pair(RegisterPair::PC);
Self::push(cpu, addr);
cpu.set_register_pair(RegisterPair::PC, vector as u16);
Cycle::new(16)
}
} }
impl Instruction { impl Instruction {