diff --git a/src/cpu.rs b/src/cpu.rs
index b2c3f45..7dafb42 100644
--- a/src/cpu.rs
+++ b/src/cpu.rs
@@ -222,13 +222,13 @@ impl Cpu {
             };
 
             let _ = match vector {
-                Some(register) => {
+                Some(address) => {
                     //  Write the Changes to 0xFF0F and 0xFFFF registers
                     self.write_byte(0xFF0F, req.into());
 
                     // Disable all future interrupts
                     self.set_ime(ImeState::Disabled);
-                    self.execute(Instruction::RST(register))
+                    Instruction::reset(self, address)
                 }
                 None => Cycle::new(0), // NO Interrupts were enabled and / or requested
             };
diff --git a/src/instruction.rs b/src/instruction.rs
index 0182eca..1d3b615 100644
--- a/src/instruction.rs
+++ b/src/instruction.rs
@@ -1092,10 +1092,10 @@ impl Instruction {
             }
             Instruction::RST(n) => {
                 // RST n | Push current address onto the stack, jump to 0x0000 + n
-                let addr = cpu.register_pair(RegisterPair::PC);
-                Self::push(cpu, addr);
-                cpu.set_register_pair(RegisterPair::PC, n as u16);
-                Cycle::new(16)
+
+                // The same behaviour will occur when handling an interrupt so this code
+                // is relegated to a method
+                Self::reset(cpu, n)
             }
             Instruction::RLC(reg) => {
                 // RLC r[z] | Rotate register r[z] left
@@ -1614,6 +1614,13 @@ impl Instruction {
 
         (lower << 4) | upper
     }
+
+    pub fn reset(cpu: &mut Cpu, vector: u8) -> Cycle {
+        let addr = cpu.register_pair(RegisterPair::PC);
+        Self::push(cpu, addr);
+        cpu.set_register_pair(RegisterPair::PC, vector as u16);
+        Cycle::new(16)
+    }
 }
 
 impl Instruction {