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chore: rename properties in bus.rs

This commit is contained in:
Rekai Nyangadzayi Musuka 2021-04-27 04:06:08 -05:00
parent 9d01b2458d
commit 9003617459
1 changed files with 16 additions and 16 deletions
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32
src/bus.rs
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@ -17,12 +17,12 @@ pub struct Bus {
boot: Option<[u8; BOOT_ROM_SIZE]>, // Boot ROM is 256b long boot: Option<[u8; BOOT_ROM_SIZE]>, // Boot ROM is 256b long
cartridge: Option<Cartridge>, cartridge: Option<Cartridge>,
pub ppu: Ppu, pub ppu: Ppu,
wram: WorkRam, work_ram: WorkRam,
vwram: VariableWorkRam, var_ram: VariableWorkRam,
timer: Timer, timer: Timer,
int: Interrupt, int: Interrupt,
sound: Sound, sound: Sound,
hram: HighRam, high_ram: HighRam,
serial: Serial, serial: Serial,
joypad: Joypad, joypad: Joypad,
} }
@ -33,12 +33,12 @@ impl Default for Bus {
boot: None, boot: None,
cartridge: None, cartridge: None,
ppu: Default::default(), ppu: Default::default(),
wram: Default::default(), work_ram: Default::default(),
vwram: Default::default(), var_ram: Default::default(),
timer: Default::default(), timer: Default::default(),
int: Default::default(), int: Default::default(),
sound: Default::default(), sound: Default::default(),
hram: Default::default(), high_ram: Default::default(),
serial: Default::default(), serial: Default::default(),
joypad: Default::default(), joypad: Default::default(),
} }
@ -106,11 +106,11 @@ impl Bus {
}, },
0xC000..=0xCFFF => { 0xC000..=0xCFFF => {
// 4KB Work RAM Bank 0 // 4KB Work RAM Bank 0
self.wram.read_byte(addr) self.work_ram.read_byte(addr)
} }
0xD000..=0xDFFF => { 0xD000..=0xDFFF => {
// 4KB Work RAM Bank 1 -> N // 4KB Work RAM Bank 1 -> N
self.vwram.read_byte(addr) self.var_ram.read_byte(addr)
} }
0xE000..=0xFDFF => { 0xE000..=0xFDFF => {
// Mirror of 0xC000 to 0xDDFF // Mirror of 0xC000 to 0xDDFF
@ -119,11 +119,11 @@ impl Bus {
match addr { match addr {
0xE000..=0xEFFF => { 0xE000..=0xEFFF => {
// 4KB Work RAM Bank 0 // 4KB Work RAM Bank 0
self.wram.read_byte(addr) self.work_ram.read_byte(addr)
} }
0xF000..=0xFDFF => { 0xF000..=0xFDFF => {
// 4KB Work RAM Bank 1 -> N // 4KB Work RAM Bank 1 -> N
self.vwram.read_byte(addr) self.var_ram.read_byte(addr)
} }
_ => unreachable!("{:#06X} was incorrectly handled by ECHO RAM", addr), _ => unreachable!("{:#06X} was incorrectly handled by ECHO RAM", addr),
} }
@ -172,7 +172,7 @@ impl Bus {
} }
0xFF80..=0xFFFE => { 0xFF80..=0xFFFE => {
// High RAM // High RAM
self.hram.read_byte(addr) self.high_ram.read_byte(addr)
} }
0xFFFF => { 0xFFFF => {
// Interrupts Enable Register // Interrupts Enable Register
@ -210,11 +210,11 @@ impl Bus {
} }
0xC000..=0xCFFF => { 0xC000..=0xCFFF => {
// 4KB Work RAM Bank 0 // 4KB Work RAM Bank 0
self.wram.write_byte(addr, byte); self.work_ram.write_byte(addr, byte);
} }
0xD000..=0xDFFF => { 0xD000..=0xDFFF => {
// 4KB Work RAM Bank 1 -> N // 4KB Work RAM Bank 1 -> N
self.vwram.write_byte(addr, byte); self.var_ram.write_byte(addr, byte);
} }
0xE000..=0xFDFF => { 0xE000..=0xFDFF => {
// Mirror of 0xC000 to 0xDDFF // Mirror of 0xC000 to 0xDDFF
@ -223,11 +223,11 @@ impl Bus {
match addr { match addr {
0xE000..=0xEFFF => { 0xE000..=0xEFFF => {
// 4KB Work RAM Bank 0 // 4KB Work RAM Bank 0
self.wram.write_byte(addr, byte); self.work_ram.write_byte(addr, byte);
} }
0xF000..=0xFDFF => { 0xF000..=0xFDFF => {
// 4KB Work RAM Bank 1 -> N // 4KB Work RAM Bank 1 -> N
self.vwram.write_byte(addr, byte); self.var_ram.write_byte(addr, byte);
} }
_ => unreachable!("{:#06X} was incorrectly handled by ECHO RAM", addr), _ => unreachable!("{:#06X} was incorrectly handled by ECHO RAM", addr),
} }
@ -291,7 +291,7 @@ impl Bus {
} }
0xFF80..=0xFFFE => { 0xFF80..=0xFFFE => {
// High RAM // High RAM
self.hram.write_byte(addr, byte); self.high_ram.write_byte(addr, byte);
} }
0xFFFF => { 0xFFFF => {
// Interrupts Enable Register // Interrupts Enable Register