chore: rename properties in bus.rs
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parent
9d01b2458d
commit
9003617459
32
src/bus.rs
32
src/bus.rs
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@ -17,12 +17,12 @@ pub struct Bus {
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boot: Option<[u8; BOOT_ROM_SIZE]>, // Boot ROM is 256b long
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cartridge: Option<Cartridge>,
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pub ppu: Ppu,
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wram: WorkRam,
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vwram: VariableWorkRam,
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work_ram: WorkRam,
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var_ram: VariableWorkRam,
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timer: Timer,
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int: Interrupt,
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sound: Sound,
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hram: HighRam,
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high_ram: HighRam,
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serial: Serial,
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joypad: Joypad,
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}
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@ -33,12 +33,12 @@ impl Default for Bus {
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boot: None,
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cartridge: None,
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ppu: Default::default(),
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wram: Default::default(),
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vwram: Default::default(),
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work_ram: Default::default(),
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var_ram: Default::default(),
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timer: Default::default(),
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int: Default::default(),
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sound: Default::default(),
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hram: Default::default(),
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high_ram: Default::default(),
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serial: Default::default(),
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joypad: Default::default(),
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}
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@ -106,11 +106,11 @@ impl Bus {
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},
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0xC000..=0xCFFF => {
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// 4KB Work RAM Bank 0
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self.wram.read_byte(addr)
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self.work_ram.read_byte(addr)
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}
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0xD000..=0xDFFF => {
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// 4KB Work RAM Bank 1 -> N
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self.vwram.read_byte(addr)
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self.var_ram.read_byte(addr)
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}
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0xE000..=0xFDFF => {
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// Mirror of 0xC000 to 0xDDFF
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@ -119,11 +119,11 @@ impl Bus {
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match addr {
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0xE000..=0xEFFF => {
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// 4KB Work RAM Bank 0
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self.wram.read_byte(addr)
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self.work_ram.read_byte(addr)
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}
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0xF000..=0xFDFF => {
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// 4KB Work RAM Bank 1 -> N
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self.vwram.read_byte(addr)
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self.var_ram.read_byte(addr)
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}
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_ => unreachable!("{:#06X} was incorrectly handled by ECHO RAM", addr),
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}
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@ -172,7 +172,7 @@ impl Bus {
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}
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0xFF80..=0xFFFE => {
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// High RAM
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self.hram.read_byte(addr)
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self.high_ram.read_byte(addr)
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}
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0xFFFF => {
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// Interrupts Enable Register
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@ -210,11 +210,11 @@ impl Bus {
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}
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0xC000..=0xCFFF => {
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// 4KB Work RAM Bank 0
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self.wram.write_byte(addr, byte);
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self.work_ram.write_byte(addr, byte);
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}
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0xD000..=0xDFFF => {
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// 4KB Work RAM Bank 1 -> N
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self.vwram.write_byte(addr, byte);
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self.var_ram.write_byte(addr, byte);
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}
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0xE000..=0xFDFF => {
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// Mirror of 0xC000 to 0xDDFF
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@ -223,11 +223,11 @@ impl Bus {
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match addr {
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0xE000..=0xEFFF => {
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// 4KB Work RAM Bank 0
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self.wram.write_byte(addr, byte);
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self.work_ram.write_byte(addr, byte);
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}
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0xF000..=0xFDFF => {
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// 4KB Work RAM Bank 1 -> N
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self.vwram.write_byte(addr, byte);
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self.var_ram.write_byte(addr, byte);
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}
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_ => unreachable!("{:#06X} was incorrectly handled by ECHO RAM", addr),
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}
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@ -291,7 +291,7 @@ impl Bus {
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}
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0xFF80..=0xFFFE => {
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// High RAM
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self.hram.write_byte(addr, byte);
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self.high_ram.write_byte(addr, byte);
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}
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0xFFFF => {
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// Interrupts Enable Register
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