feat: clock bus on instruction read-write

Commit also includes general work towards passing mem-timings.

Note: while cpu_instrs.gb passes, instr_timing.gb and mem_timing.gb both
are stuck in infinite loops (Currently, it seems like a timing issue).
This is a major regression that hopefully shouldn't last for too long.

src/work_ram.rs

@@ -28,48 +28,25 @@ impl Default for WorkRam {
     }
 }
 
-#[derive(Debug, Clone, Copy)]
-enum BankNumber {
-    One = 1,
-    Two = 2,
-    Three = 3,
-    Four = 4,
-    Five = 5,
-    Six = 6,
-    Seven = 7,
-}
-
 #[derive(Debug)]
 pub(crate) struct VariableWorkRam {
-    current: BankNumber,
-    bank_n: Box<[[u8; VARIABLE_WORK_RAM_SIZE]; 7]>, // 4K for Variable amount of Banks (Banks 1 -> 7) in Game Boy Colour
+    buf: Box<[u8; VARIABLE_WORK_RAM_SIZE]>, // 4K for Variable amount of Banks (Banks 1 -> 7) in Game Boy Colour
 }
 
 impl Default for VariableWorkRam {
     fn default() -> Self {
         Self {
-            current: BankNumber::One,
-            bank_n: Box::new([[0u8; VARIABLE_WORK_RAM_SIZE]; 7]),
+            buf: Box::new([0u8; VARIABLE_WORK_RAM_SIZE]),
         }
     }
 }
 
-impl VariableWorkRam {
-    fn set_current_bank(&mut self, bank: BankNumber) {
-        self.current = bank;
-    }
-
-    fn get_current_bank(&self) -> &BankNumber {
-        &self.current
-    }
-}
-
 impl BusIo for VariableWorkRam {
     fn write_byte(&mut self, addr: u16, byte: u8) {
-        self.bank_n[self.current as usize][addr as usize - VARIABLE_WORK_RAM_START_ADDRESS] = byte;
+        self.buf[addr as usize - VARIABLE_WORK_RAM_START_ADDRESS] = byte;
     }
 
     fn read_byte(&self, addr: u16) -> u8 {
-        self.bank_n[self.current as usize][addr as usize - VARIABLE_WORK_RAM_START_ADDRESS]
+        self.buf[addr as usize - VARIABLE_WORK_RAM_START_ADDRESS]
     }
 }