Rekai Musuka
8625bec059
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continuous-integration/drone/push Build is failing
Commit also includes general work towards passing mem-timings. Note: while cpu_instrs.gb passes, instr_timing.gb and mem_timing.gb both are stuck in infinite loops (Currently, it seems like a timing issue). This is a major regression that hopefully shouldn't last for too long.
53 lines
1.3 KiB
Rust
53 lines
1.3 KiB
Rust
use crate::bus::BusIo;
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const WORK_RAM_SIZE: usize = 0x1000;
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const VARIABLE_WORK_RAM_SIZE: usize = WORK_RAM_SIZE;
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const WORK_RAM_START_ADDRESS: usize = 0xC000;
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const VARIABLE_WORK_RAM_START_ADDRESS: usize = 0xD000;
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#[derive(Debug)]
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pub(crate) struct WorkRam {
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bank: Box<[u8; WORK_RAM_SIZE]>,
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}
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impl BusIo for WorkRam {
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fn write_byte(&mut self, addr: u16, byte: u8) {
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self.bank[addr as usize - WORK_RAM_START_ADDRESS] = byte;
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}
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fn read_byte(&self, addr: u16) -> u8 {
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self.bank[addr as usize - WORK_RAM_START_ADDRESS]
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}
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}
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impl Default for WorkRam {
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fn default() -> Self {
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Self {
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bank: Box::new([0u8; WORK_RAM_SIZE]),
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}
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}
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}
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#[derive(Debug)]
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pub(crate) struct VariableWorkRam {
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buf: Box<[u8; VARIABLE_WORK_RAM_SIZE]>, // 4K for Variable amount of Banks (Banks 1 -> 7) in Game Boy Colour
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}
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impl Default for VariableWorkRam {
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fn default() -> Self {
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Self {
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buf: Box::new([0u8; VARIABLE_WORK_RAM_SIZE]),
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}
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}
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}
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impl BusIo for VariableWorkRam {
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fn write_byte(&mut self, addr: u16, byte: u8) {
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self.buf[addr as usize - VARIABLE_WORK_RAM_START_ADDRESS] = byte;
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}
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fn read_byte(&self, addr: u16) -> u8 {
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self.buf[addr as usize - VARIABLE_WORK_RAM_START_ADDRESS]
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}
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}
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