fix(apu): remove redundant code
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parent
d794a94b68
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634bc2d2c0
43
src/timer.rs
43
src/timer.rs
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@ -22,29 +22,16 @@ impl Timer {
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use TimerSpeed::*;
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match self.state {
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TIMAOverflow(_) | AbortedTIMAOverflow(_) => self.state = self.state.next(),
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TIMAOverflow(_) | AbortedTIMAOverflow(_) => self.next(),
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LoadTMA => {
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self.counter = self.modulo;
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self.interrupt = true;
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self.state.next();
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self.next();
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}
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Normal => {}
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}
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if let TIMAOverflow(step) | AbortedTIMAOverflow(step) = self.state {
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if step < 3 {
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self.state = self.state.next();
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} else {
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if self.state == TIMAOverflow(step) {
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self.counter = self.modulo;
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self.interrupt = true;
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}
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self.state = Normal;
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}
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}
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self.divider = self.divider.wrapping_add(1);
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// Get Bit Position
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@ -103,6 +90,18 @@ impl Timer {
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self.state = State::TIMAOverflow(0);
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}
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}
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fn next(&mut self) {
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use State::*;
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self.state = match self.state {
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Normal | LoadTMA => Normal,
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AbortedTIMAOverflow(4) => Normal,
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TIMAOverflow(4) => LoadTMA,
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AbortedTIMAOverflow(step) => AbortedTIMAOverflow(step + 1),
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TIMAOverflow(step) => TIMAOverflow(step + 1),
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}
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}
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}
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impl Default for Timer {
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@ -184,17 +183,3 @@ enum State {
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Normal,
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LoadTMA,
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}
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impl State {
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fn next(&self) -> Self {
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use State::*;
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match self {
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Normal | LoadTMA => Normal,
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TIMAOverflow(3) => LoadTMA,
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AbortedTIMAOverflow(3) => Normal,
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TIMAOverflow(step) => TIMAOverflow(step + 1),
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AbortedTIMAOverflow(step) => AbortedTIMAOverflow(step + 1),
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}
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}
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}
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