From 634bc2d2c0595e17b172832150e7dec5ae3e9973 Mon Sep 17 00:00:00 2001
From: Rekai Musuka <rekai@musuka.dev>
Date: Sun, 22 Aug 2021 01:48:34 -0500
Subject: [PATCH] fix(apu): remove redundant code

---
 src/timer.rs | 43 ++++++++++++++-----------------------------
 1 file changed, 14 insertions(+), 29 deletions(-)

diff --git a/src/timer.rs b/src/timer.rs
index 3ef7080..1250fbc 100644
--- a/src/timer.rs
+++ b/src/timer.rs
@@ -22,29 +22,16 @@ impl Timer {
         use TimerSpeed::*;
 
         match self.state {
-            TIMAOverflow(_) | AbortedTIMAOverflow(_) => self.state = self.state.next(),
+            TIMAOverflow(_) | AbortedTIMAOverflow(_) => self.next(),
             LoadTMA => {
                 self.counter = self.modulo;
                 self.interrupt = true;
 
-                self.state.next();
+                self.next();
             }
             Normal => {}
         }
 
-        if let TIMAOverflow(step) | AbortedTIMAOverflow(step) = self.state {
-            if step < 3 {
-                self.state = self.state.next();
-            } else {
-                if self.state == TIMAOverflow(step) {
-                    self.counter = self.modulo;
-                    self.interrupt = true;
-                }
-
-                self.state = Normal;
-            }
-        }
-
         self.divider = self.divider.wrapping_add(1);
 
         // Get Bit Position
@@ -103,6 +90,18 @@ impl Timer {
             self.state = State::TIMAOverflow(0);
         }
     }
+
+    fn next(&mut self) {
+        use State::*;
+
+        self.state = match self.state {
+            Normal | LoadTMA => Normal,
+            AbortedTIMAOverflow(4) => Normal,
+            TIMAOverflow(4) => LoadTMA,
+            AbortedTIMAOverflow(step) => AbortedTIMAOverflow(step + 1),
+            TIMAOverflow(step) => TIMAOverflow(step + 1),
+        }
+    }
 }
 
 impl Default for Timer {
@@ -184,17 +183,3 @@ enum State {
     Normal,
     LoadTMA,
 }
-
-impl State {
-    fn next(&self) -> Self {
-        use State::*;
-
-        match self {
-            Normal | LoadTMA => Normal,
-            TIMAOverflow(3) => LoadTMA,
-            AbortedTIMAOverflow(3) => Normal,
-            TIMAOverflow(step) => TIMAOverflow(step + 1),
-            AbortedTIMAOverflow(step) => AbortedTIMAOverflow(step + 1),
-        }
-    }
-}