fix(apu): remove redundant code

This commit is contained in:
Rekai Nyangadzayi Musuka 2021-08-22 01:48:34 -05:00
parent d794a94b68
commit 634bc2d2c0
1 changed files with 14 additions and 29 deletions

View File

@ -22,29 +22,16 @@ impl Timer {
use TimerSpeed::*; use TimerSpeed::*;
match self.state { match self.state {
TIMAOverflow(_) | AbortedTIMAOverflow(_) => self.state = self.state.next(), TIMAOverflow(_) | AbortedTIMAOverflow(_) => self.next(),
LoadTMA => { LoadTMA => {
self.counter = self.modulo; self.counter = self.modulo;
self.interrupt = true; self.interrupt = true;
self.state.next(); self.next();
} }
Normal => {} Normal => {}
} }
if let TIMAOverflow(step) | AbortedTIMAOverflow(step) = self.state {
if step < 3 {
self.state = self.state.next();
} else {
if self.state == TIMAOverflow(step) {
self.counter = self.modulo;
self.interrupt = true;
}
self.state = Normal;
}
}
self.divider = self.divider.wrapping_add(1); self.divider = self.divider.wrapping_add(1);
// Get Bit Position // Get Bit Position
@ -103,6 +90,18 @@ impl Timer {
self.state = State::TIMAOverflow(0); self.state = State::TIMAOverflow(0);
} }
} }
fn next(&mut self) {
use State::*;
self.state = match self.state {
Normal | LoadTMA => Normal,
AbortedTIMAOverflow(4) => Normal,
TIMAOverflow(4) => LoadTMA,
AbortedTIMAOverflow(step) => AbortedTIMAOverflow(step + 1),
TIMAOverflow(step) => TIMAOverflow(step + 1),
}
}
} }
impl Default for Timer { impl Default for Timer {
@ -184,17 +183,3 @@ enum State {
Normal, Normal,
LoadTMA, LoadTMA,
} }
impl State {
fn next(&self) -> Self {
use State::*;
match self {
Normal | LoadTMA => Normal,
TIMAOverflow(3) => LoadTMA,
AbortedTIMAOverflow(3) => Normal,
TIMAOverflow(step) => TIMAOverflow(step + 1),
AbortedTIMAOverflow(step) => AbortedTIMAOverflow(step + 1),
}
}
}