fix(cpu): fix timing issue involving when the bus is clocked

src/cpu.rs

@@ -122,15 +122,15 @@ impl Cpu {
             }
         };
 
-        // FIXME: Regression, this is not a proper fix,
+        // TODO: With how we currently handle audio
-        // the FIFO behaves weirdly using this code
+        // this --while being correct-- incurs a performance penalty
+        // as our emu is audio-bound.
+        let mut elapsed = 0x00;
         let pending: u32 = cycles.into();
-        let mut offset = 0;
+        while elapsed < pending {
-        for _ in 0..(pending + offset) {
             if !self.bus.is_mpsc_still_full() {
                 self.bus.clock();
-            } else {
+                elapsed += 1;
-                offset += 1;
             }
         }