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chore: make clippy happy

This commit is contained in:
Rekai Nyangadzayi Musuka 2021-03-16 01:05:13 -05:00
parent bfde24cc8d
commit 19f642eafe
8 changed files with 90 additions and 88 deletions
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14
src/bus.rs
View File

@ -1,25 +1,25 @@
use super::cartridge::Cartridge; use super::cartridge::Cartridge;
use super::high_ram::HighRAM; use super::high_ram::HighRam;
use super::instruction::Cycles; use super::instruction::Cycles;
use super::interrupt::Interrupt; use super::interrupt::Interrupt;
use super::ppu::PPU; use super::ppu::Ppu;
use super::serial::Serial; use super::serial::Serial;
use super::sound::Sound; use super::sound::Sound;
use super::timer::Timer; use super::timer::Timer;
use super::work_ram::{VariableWorkRAM, WorkRAM}; use super::work_ram::{VariableWorkRam, WorkRam};
use std::{convert::TryInto, fs::File, io::Read}; use std::{convert::TryInto, fs::File, io::Read};
#[derive(Debug, Clone)] #[derive(Debug, Clone)]
pub struct Bus { pub struct Bus {
boot: Option<[u8; 256]>, // Boot ROM is 256b long boot: Option<[u8; 256]>, // Boot ROM is 256b long
cartridge: Option<Cartridge>, cartridge: Option<Cartridge>,
pub ppu: PPU, pub ppu: Ppu,
wram: WorkRAM, wram: WorkRam,
vwram: VariableWorkRAM, vwram: VariableWorkRam,
timer: Timer, timer: Timer,
interrupt: Interrupt, interrupt: Interrupt,
sound: Sound, sound: Sound,
hram: HighRAM, hram: HighRam,
serial: Serial, serial: Serial,
} }

46
src/cartridge.rs
View File

@ -5,7 +5,7 @@ use std::path::Path;
#[derive(Debug, Clone, Default)] #[derive(Debug, Clone, Default)]
pub struct Cartridge { pub struct Cartridge {
memory: Vec<u8>, memory: Vec<u8>,
mbc: Box<dyn MBC>, mbc: Box<dyn Mbc>,
} }
impl Cartridge { impl Cartridge {
@ -20,7 +20,7 @@ impl Cartridge {
}) })
} }
fn detect_mbc(memory: &[u8]) -> Box<dyn MBC> { fn detect_mbc(memory: &[u8]) -> Box<dyn Mbc> {
let ram_size = Self::find_ram_size(&memory); let ram_size = Self::find_ram_size(&memory);
let bank_count = Self::find_bank_count(&memory); let bank_count = Self::find_bank_count(&memory);
let mbc_kind = Self::find_mbc(&memory); let mbc_kind = Self::find_mbc(&memory);
@ -40,7 +40,7 @@ impl Cartridge {
Box::new(mbc) Box::new(mbc)
} }
fn find_ram_size(memory: &[u8]) -> RAMSize { fn find_ram_size(memory: &[u8]) -> RamSize {
let id = memory[0x0149]; let id = memory[0x0149];
id.into() id.into()
} }
@ -89,7 +89,7 @@ struct MBC1 {
current_rom_bank: u8, // 5-bit Number current_rom_bank: u8, // 5-bit Number
current_ram_bank: u8, // 2-bit number current_ram_bank: u8, // 2-bit number
mode: bool, mode: bool,
ram_size: RAMSize, ram_size: RamSize,
ram: Box<[u8]>, ram: Box<[u8]>,
bank_count: BankCount, bank_count: BankCount,
ram_enabled: bool, ram_enabled: bool,
@ -139,7 +139,7 @@ impl MBC1 {
} }
} }
impl MBC for MBC1 { impl Mbc for MBC1 {
fn handle_read(&self, addr: u16) -> MBCResult { fn handle_read(&self, addr: u16) -> MBCResult {
use MBCResult::*; use MBCResult::*;
@ -159,10 +159,10 @@ impl MBC for MBC1 {
0xA000..=0xBFFF => { 0xA000..=0xBFFF => {
if self.ram_enabled { if self.ram_enabled {
let ram_addr = match self.ram_size { let ram_addr = match self.ram_size {
RAMSize::_2KB | RAMSize::_8KB => { RamSize::_2KB | RamSize::_8KB => {
(addr as u32 - 0xA000) % self.ram_size.to_byte_count() (addr as u32 - 0xA000) % self.ram_size.to_byte_count()
} }
RAMSize::_32KB => { RamSize::_32KB => {
if self.mode { if self.mode {
0x2000 * self.current_ram_bank as u32 + (addr as u32 - 0xA000) 0x2000 * self.current_ram_bank as u32 + (addr as u32 - 0xA000)
} else { } else {
@ -196,17 +196,17 @@ impl MBC for MBC1 {
0xA000..=0xBFFF => { 0xA000..=0xBFFF => {
if self.ram_enabled { if self.ram_enabled {
let ram_addr = match self.ram_size { let ram_addr = match self.ram_size {
RAMSize::_2KB | RAMSize::_8KB => { RamSize::_2KB | RamSize::_8KB => {
(addr as u32 - 0xA000) % self.ram_size.to_byte_count() (addr as u32 - 0xA000) % self.ram_size.to_byte_count()
} }
RAMSize::_32KB => { RamSize::_32KB => {
if self.mode { if self.mode {
0x2000 * (self.current_ram_bank as u32) + (addr as u32 - 0xA000) 0x2000 * (self.current_ram_bank as u32) + (addr as u32 - 0xA000)
} else { } else {
addr as u32 - 0xA000 addr as u32 - 0xA000
} }
} }
_ => unreachable!("RAMSize can not be greater than 32KB on MBC1"), _ => unreachable!("RAM size can not be greater than 32KB on MBC1"),
}; };
self.ram[ram_addr as usize] = byte; self.ram[ram_addr as usize] = byte;
@ -217,20 +217,20 @@ impl MBC for MBC1 {
} }
} }
trait MBC: CloneMBC { trait Mbc: CloneMBC {
fn handle_read(&self, addr: u16) -> MBCResult; fn handle_read(&self, addr: u16) -> MBCResult;
fn handle_write(&mut self, addr: u16, byte: u8); fn handle_write(&mut self, addr: u16, byte: u8);
} }
trait CloneMBC { trait CloneMBC {
fn clone_mbc<'a>(&self) -> Box<dyn MBC>; fn clone_mbc(&self) -> Box<dyn Mbc>;
} }
impl<T> CloneMBC for T impl<T> CloneMBC for T
where where
T: MBC + Clone + 'static, T: Mbc + Clone + 'static,
{ {
fn clone_mbc<'a>(&self) -> Box<dyn MBC> { fn clone_mbc<'a>(&self) -> Box<dyn Mbc> {
Box::new(self.clone()) Box::new(self.clone())
} }
} }
@ -254,7 +254,7 @@ impl Default for MBCKind {
} }
#[derive(Debug, Clone, Copy)] #[derive(Debug, Clone, Copy)]
enum RAMSize { enum RamSize {
None = 0, None = 0,
_2KB = 1, _2KB = 1,
_8KB = 2, _8KB = 2,
@ -263,9 +263,9 @@ enum RAMSize {
_64KB = 5, // Split into 8 RAm Banks _64KB = 5, // Split into 8 RAm Banks
} }
impl RAMSize { impl RamSize {
pub fn to_byte_count(&self) -> u32 { pub fn to_byte_count(&self) -> u32 {
use RAMSize::*; use RamSize::*;
match *self { match *self {
None => 0, None => 0,
@ -278,15 +278,15 @@ impl RAMSize {
} }
} }
impl Default for RAMSize { impl Default for RamSize {
fn default() -> Self { fn default() -> Self {
Self::None Self::None
} }
} }
impl From<u8> for RAMSize { impl From<u8> for RamSize {
fn from(byte: u8) -> Self { fn from(byte: u8) -> Self {
use RAMSize::*; use RamSize::*;
match byte { match byte {
0x00 => None, 0x00 => None,
@ -366,19 +366,19 @@ impl From<u8> for BankCount {
} }
} }
impl std::fmt::Debug for Box<dyn MBC> { impl std::fmt::Debug for Box<dyn Mbc> {
fn fmt(&self, _f: &mut std::fmt::Formatter<'_>) -> std::fmt::Result { fn fmt(&self, _f: &mut std::fmt::Formatter<'_>) -> std::fmt::Result {
todo!("Implement Debug for Box<dyn MBC> Trait Object"); todo!("Implement Debug for Box<dyn MBC> Trait Object");
} }
} }
impl std::clone::Clone for Box<dyn MBC> { impl std::clone::Clone for Box<dyn Mbc> {
fn clone(&self) -> Self { fn clone(&self) -> Self {
self.clone_mbc() self.clone_mbc()
} }
} }
impl std::default::Default for Box<dyn MBC> { impl std::default::Default for Box<dyn Mbc> {
fn default() -> Self { fn default() -> Self {
Box::new(MBC1::default()) Box::new(MBC1::default())
} }

4
src/cpu.rs
View File

@ -1,6 +1,6 @@
use super::bus::Bus; use super::bus::Bus;
use super::instruction::{Cycles, Instruction}; use super::instruction::{Cycles, Instruction};
use super::ppu::PPU; use super::ppu::Ppu;
use bitfield::bitfield; use bitfield::bitfield;
use std::{ use std::{
fmt::{Display, Formatter, Result as FmtResult}, fmt::{Display, Formatter, Result as FmtResult},
@ -130,7 +130,7 @@ impl Cpu {
} }
impl Cpu { impl Cpu {
pub fn get_ppu(&mut self) -> &mut PPU { pub fn get_ppu(&mut self) -> &mut Ppu {
&mut self.bus.ppu &mut self.bus.ppu
} }
} }

6
src/high_ram.rs
View File

@ -1,9 +1,9 @@
#[derive(Debug, Clone)] #[derive(Debug, Clone)]
pub struct HighRAM { pub struct HighRam {
buf: Box<[u8]>, buf: Box<[u8]>,
} }
impl Default for HighRAM { impl Default for HighRam {
fn default() -> Self { fn default() -> Self {
Self { Self {
buf: vec![0u8; 128].into_boxed_slice(), buf: vec![0u8; 128].into_boxed_slice(),
@ -11,7 +11,7 @@ impl Default for HighRAM {
} }
} }
impl HighRAM { impl HighRam {
pub fn write_byte(&mut self, index: usize, byte: u8) { pub fn write_byte(&mut self, index: usize, byte: u8) {
self.buf[index] = byte; self.buf[index] = byte;
} }

76
src/instruction.rs
View File

@ -2,6 +2,7 @@ use super::cpu::{Cpu, Flags, Register, RegisterPair};
use std::{convert::TryFrom, fmt::Debug}; use std::{convert::TryFrom, fmt::Debug};
#[derive(Debug, Copy, Clone)] #[derive(Debug, Copy, Clone)]
#[allow(clippy::upper_case_acronyms)]
pub enum Instruction { pub enum Instruction {
NOP, NOP,
LD(LDTarget, LDTarget), LD(LDTarget, LDTarget),
@ -342,7 +343,7 @@ impl Instruction {
Instruction::ADD(lhs, rhs) => match (lhs, rhs) { Instruction::ADD(lhs, rhs) => match (lhs, rhs) {
(MATHTarget::RegisterPair(RegisterPair::HL), MATHTarget::RegisterPair(pair)) => { (MATHTarget::RegisterPair(RegisterPair::HL), MATHTarget::RegisterPair(pair)) => {
// ADD HL, rp[p] | add register pair to HL. // ADD HL, rp[p] | add register pair to HL.
let mut flags: Flags = cpu.flags().clone(); let mut flags: Flags = *cpu.flags();
match pair { match pair {
RegisterPair::BC RegisterPair::BC
@ -362,7 +363,7 @@ impl Instruction {
} }
(MATHTarget::Register(InstrRegister::A), MATHTarget::Register(reg)) => { (MATHTarget::Register(InstrRegister::A), MATHTarget::Register(reg)) => {
// ADD A, r[z] | Add (A + r[z]) to register A // ADD A, r[z] | Add (A + r[z]) to register A
let mut flags: Flags = cpu.flags().clone(); let mut flags: Flags = *cpu.flags();
let a_value = cpu.register(Register::A); let a_value = cpu.register(Register::A);
let sum; let sum;
let cycles: Cycles; let cycles: Cycles;
@ -391,7 +392,7 @@ impl Instruction {
} }
(MATHTarget::RegisterPair(RegisterPair::SP), MATHTarget::ImmediateByte(d)) => { (MATHTarget::RegisterPair(RegisterPair::SP), MATHTarget::ImmediateByte(d)) => {
// ADD SP, d | Add d (is signed) to register pair SP. // ADD SP, d | Add d (is signed) to register pair SP.
let mut flags: Flags = cpu.flags().clone(); let mut flags: Flags = *cpu.flags();
let d = d as i8; let d = d as i8;
let sum = Self::add_u16_i8(cpu.register_pair(RegisterPair::SP), d, &mut flags); let sum = Self::add_u16_i8(cpu.register_pair(RegisterPair::SP), d, &mut flags);
cpu.set_register_pair(RegisterPair::SP, sum); cpu.set_register_pair(RegisterPair::SP, sum);
@ -399,7 +400,7 @@ impl Instruction {
} }
(MATHTarget::Register(InstrRegister::A), MATHTarget::ImmediateByte(n)) => { (MATHTarget::Register(InstrRegister::A), MATHTarget::ImmediateByte(n)) => {
// ADD A, n | Add n to register A // ADD A, n | Add n to register A
let mut flags: Flags = cpu.flags().clone(); let mut flags: Flags = *cpu.flags();
let sum = Self::add_u8s(cpu.register(Register::A), n, &mut flags); let sum = Self::add_u8s(cpu.register(Register::A), n, &mut flags);
cpu.set_register(Register::A, sum); cpu.set_register(Register::A, sum);
@ -412,7 +413,7 @@ impl Instruction {
match registers { match registers {
Registers::Byte(reg) => { Registers::Byte(reg) => {
// INC r[y] | Increment Register // INC r[y] | Increment Register
let mut flags: Flags = cpu.flags().clone(); let mut flags: Flags = *cpu.flags();
let cycles: Cycles; let cycles: Cycles;
match reg { match reg {
@ -468,7 +469,7 @@ impl Instruction {
} }
Instruction::DEC(Registers::Byte(reg)) => { Instruction::DEC(Registers::Byte(reg)) => {
// DEC r[y] | Decrement Register // DEC r[y] | Decrement Register
let mut flags: Flags = cpu.flags().clone(); let mut flags: Flags = *cpu.flags();
let cycles: Cycles; let cycles: Cycles;
match reg { match reg {
@ -497,7 +498,7 @@ impl Instruction {
} }
Instruction::RLCA => { Instruction::RLCA => {
// Rotate Register A left // Rotate Register A left
let mut flags: Flags = cpu.flags().clone(); let mut flags: Flags = *cpu.flags();
let a = cpu.register(Register::A); let a = cpu.register(Register::A);
let msb = a >> 7; let msb = a >> 7;
@ -510,7 +511,7 @@ impl Instruction {
} }
Instruction::RRCA => { Instruction::RRCA => {
// Rotate Register A right // Rotate Register A right
let mut flags: Flags = cpu.flags().clone(); let mut flags: Flags = *cpu.flags();
let a = cpu.register(Register::A); let a = cpu.register(Register::A);
let lsb = a & 0x01; let lsb = a & 0x01;
@ -523,7 +524,7 @@ impl Instruction {
} }
Instruction::RLA => { Instruction::RLA => {
// Rotate register A left through carry // Rotate register A left through carry
let mut flags: Flags = cpu.flags().clone(); let mut flags: Flags = *cpu.flags();
let a = cpu.register(Register::A); let a = cpu.register(Register::A);
let (rot_a, carry) = Self::rl_thru_carry(a, flags.c()); let (rot_a, carry) = Self::rl_thru_carry(a, flags.c());
@ -535,7 +536,7 @@ impl Instruction {
} }
Instruction::RRA => { Instruction::RRA => {
// Rotate register A right through carry // Rotate register A right through carry
let mut flags: Flags = cpu.flags().clone(); let mut flags: Flags = *cpu.flags();
let a = cpu.register(Register::A); let a = cpu.register(Register::A);
let (rot_a, carry) = Self::rr_thru_carry(a, flags.c()); let (rot_a, carry) = Self::rr_thru_carry(a, flags.c());
@ -548,7 +549,7 @@ impl Instruction {
Instruction::DAA => unimplemented!(), Instruction::DAA => unimplemented!(),
Instruction::CPL => { Instruction::CPL => {
// Compliment A register (inverse) // Compliment A register (inverse)
let mut flags: Flags = cpu.flags().clone(); let mut flags: Flags = *cpu.flags();
let a = cpu.register(Register::A); let a = cpu.register(Register::A);
flags.set_n(true); flags.set_n(true);
@ -560,7 +561,7 @@ impl Instruction {
} }
Instruction::SCF => { Instruction::SCF => {
// Set Carry Flag // Set Carry Flag
let mut flags: Flags = cpu.flags().clone(); let mut flags: Flags = *cpu.flags();
flags.set_n(false); flags.set_n(false);
flags.set_h(false); flags.set_h(false);
@ -571,7 +572,7 @@ impl Instruction {
} }
Instruction::CCF => { Instruction::CCF => {
// Compliment Carry Flag (inverse) // Compliment Carry Flag (inverse)
let mut flags: Flags = cpu.flags().clone(); let mut flags: Flags = *cpu.flags();
flags.set_n(false); flags.set_n(false);
flags.set_h(false); flags.set_h(false);
@ -585,7 +586,7 @@ impl Instruction {
MATHTarget::Register(reg) => { MATHTarget::Register(reg) => {
// ADC A, r[z] | Add register r[z] plus the Carry flag to A // ADC A, r[z] | Add register r[z] plus the Carry flag to A
// FIXME: Do I Add register A as well? // FIXME: Do I Add register A as well?
let mut flags: Flags = cpu.flags().clone(); let mut flags: Flags = *cpu.flags();
let a_value = cpu.register(Register::A); let a_value = cpu.register(Register::A);
let cycles: Cycles; let cycles: Cycles;
let sum; let sum;
@ -615,7 +616,7 @@ impl Instruction {
} }
MATHTarget::ImmediateByte(n) => { MATHTarget::ImmediateByte(n) => {
// ADC A, n | Add immediate byte plus the carry flag to A // ADC A, n | Add immediate byte plus the carry flag to A
let mut flags: Flags = cpu.flags().clone(); let mut flags: Flags = *cpu.flags();
let value = n + (flags.c() as u8); let value = n + (flags.c() as u8);
let sum = Self::add_u8s(cpu.register(Register::A), value, &mut flags); let sum = Self::add_u8s(cpu.register(Register::A), value, &mut flags);
@ -628,7 +629,7 @@ impl Instruction {
Instruction::SUB(target) => match target { Instruction::SUB(target) => match target {
MATHTarget::Register(reg) => { MATHTarget::Register(reg) => {
// SUB r[z] | Subtract the value in register r[z] from register A, then store in A // SUB r[z] | Subtract the value in register r[z] from register A, then store in A
let mut flags: Flags = cpu.flags().clone(); let mut flags: Flags = *cpu.flags();
let a_value = cpu.register(Register::A); let a_value = cpu.register(Register::A);
let cycles: Cycles; let cycles: Cycles;
let diff; let diff;
@ -658,7 +659,7 @@ impl Instruction {
} }
MATHTarget::ImmediateByte(n) => { MATHTarget::ImmediateByte(n) => {
// SUB n | Subtract the immediate byte from register A, then store in A // SUB n | Subtract the immediate byte from register A, then store in A
let mut flags: Flags = cpu.flags().clone(); let mut flags: Flags = *cpu.flags();
let diff = Self::sub_u8s(cpu.register(Register::A), n, &mut flags); let diff = Self::sub_u8s(cpu.register(Register::A), n, &mut flags);
cpu.set_flags(flags); cpu.set_flags(flags);
@ -671,7 +672,7 @@ impl Instruction {
MATHTarget::Register(reg) => { MATHTarget::Register(reg) => {
// SBC A, r[z] | Subtract the value from register r[z] from A, add the Carry flag and then store in A // SBC A, r[z] | Subtract the value from register r[z] from A, add the Carry flag and then store in A
// FIXME: See ADC, is this a correct understanding of this Instruction // FIXME: See ADC, is this a correct understanding of this Instruction
let mut flags: Flags = cpu.flags().clone(); let mut flags: Flags = *cpu.flags();
let a_value = cpu.register(Register::A); let a_value = cpu.register(Register::A);
let cycles: Cycles; let cycles: Cycles;
let diff; let diff;
@ -703,7 +704,7 @@ impl Instruction {
MATHTarget::ImmediateByte(n) => { MATHTarget::ImmediateByte(n) => {
// SBC A, n | Subtract the value from immediate byte from A, add the carry flag and then store in A // SBC A, n | Subtract the value from immediate byte from A, add the carry flag and then store in A
// FIXME: The Fixme above applies to this variant as well // FIXME: The Fixme above applies to this variant as well
let mut flags: Flags = cpu.flags().clone(); let mut flags: Flags = *cpu.flags();
let value = n + (flags.c() as u8); let value = n + (flags.c() as u8);
let diff = Self::sub_u8s(cpu.register(Register::A), value, &mut flags); let diff = Self::sub_u8s(cpu.register(Register::A), value, &mut flags);
@ -716,7 +717,7 @@ impl Instruction {
Instruction::AND(target) => match target { Instruction::AND(target) => match target {
MATHTarget::Register(reg) => { MATHTarget::Register(reg) => {
// AND r[z] | Bitwise AND register r[z] and register A, store in register A // AND r[z] | Bitwise AND register r[z] and register A, store in register A
let mut flags: Flags = cpu.flags().clone(); let mut flags: Flags = *cpu.flags();
let a_value = cpu.register(Register::A); let a_value = cpu.register(Register::A);
let cycles: Cycles; let cycles: Cycles;
let result; let result;
@ -747,7 +748,7 @@ impl Instruction {
} }
MATHTarget::ImmediateByte(n) => { MATHTarget::ImmediateByte(n) => {
// AND n | Bitwise AND immediate byte and register A, store in register A // AND n | Bitwise AND immediate byte and register A, store in register A
let mut flags: Flags = cpu.flags().clone(); let mut flags: Flags = *cpu.flags();
let result = cpu.register(Register::A) & n; let result = cpu.register(Register::A) & n;
flags.update(result == 0, false, true, false); flags.update(result == 0, false, true, false);
@ -760,7 +761,7 @@ impl Instruction {
Instruction::XOR(target) => match target { Instruction::XOR(target) => match target {
MATHTarget::Register(reg) => { MATHTarget::Register(reg) => {
// XOR r[z] | Bitwise XOR register r[z] and register A, store in register A // XOR r[z] | Bitwise XOR register r[z] and register A, store in register A
let mut flags: Flags = cpu.flags().clone(); let mut flags: Flags = *cpu.flags();
let a_value = cpu.register(Register::A); let a_value = cpu.register(Register::A);
let cycles: Cycles; let cycles: Cycles;
let result; let result;
@ -791,7 +792,7 @@ impl Instruction {
} }
MATHTarget::ImmediateByte(n) => { MATHTarget::ImmediateByte(n) => {
// XOR n | Bitwise XOR immediate byte and register A, store in register A // XOR n | Bitwise XOR immediate byte and register A, store in register A
let mut flags: Flags = cpu.flags().clone(); let mut flags: Flags = *cpu.flags();
let result = cpu.register(Register::A) ^ n; let result = cpu.register(Register::A) ^ n;
flags.update(result == 0, false, false, false); flags.update(result == 0, false, false, false);
@ -804,7 +805,7 @@ impl Instruction {
Instruction::OR(target) => match target { Instruction::OR(target) => match target {
MATHTarget::Register(reg) => { MATHTarget::Register(reg) => {
// OR r[z] | Bitwise OR register r[z] and register A, store in register A // OR r[z] | Bitwise OR register r[z] and register A, store in register A
let mut flags: Flags = cpu.flags().clone(); let mut flags: Flags = *cpu.flags();
let a_value = cpu.register(Register::A); let a_value = cpu.register(Register::A);
let cycles: Cycles; let cycles: Cycles;
let result; let result;
@ -835,7 +836,7 @@ impl Instruction {
} }
MATHTarget::ImmediateByte(n) => { MATHTarget::ImmediateByte(n) => {
// OR n | Bitwise OR on immediate byte n and register A, store in register A // OR n | Bitwise OR on immediate byte n and register A, store in register A
let mut flags: Flags = cpu.flags().clone(); let mut flags: Flags = *cpu.flags();
let result = cpu.register(Register::A) | n; let result = cpu.register(Register::A) | n;
flags.update(result == 0, false, false, false); flags.update(result == 0, false, false, false);
@ -848,7 +849,7 @@ impl Instruction {
Instruction::CP(target) => match target { Instruction::CP(target) => match target {
MATHTarget::Register(reg) => { MATHTarget::Register(reg) => {
// CP r[z] | Same behaviour as SUB, except the result is not stored. // CP r[z] | Same behaviour as SUB, except the result is not stored.
let mut flags: Flags = cpu.flags().clone(); let mut flags: Flags = *cpu.flags();
let a_value = cpu.register(Register::A); let a_value = cpu.register(Register::A);
let cycles: Cycles; let cycles: Cycles;
@ -876,7 +877,7 @@ impl Instruction {
} }
MATHTarget::ImmediateByte(n) => { MATHTarget::ImmediateByte(n) => {
// CP n | Same behaviour as SUB, except the result is not stored, // CP n | Same behaviour as SUB, except the result is not stored,
let mut flags: Flags = cpu.flags().clone(); let mut flags: Flags = *cpu.flags();
let _ = Self::sub_u8s(cpu.register(Register::A), n, &mut flags); let _ = Self::sub_u8s(cpu.register(Register::A), n, &mut flags);
cpu.set_flags(flags); cpu.set_flags(flags);
@ -932,7 +933,7 @@ impl Instruction {
Instruction::LDHL(d) => { Instruction::LDHL(d) => {
// LDHL SP + d | Add SP + d to register HL // LDHL SP + d | Add SP + d to register HL
// LD HL, SP + d | Add SP + d to register HL // LD HL, SP + d | Add SP + d to register HL
let mut flags: Flags = cpu.flags().clone(); let mut flags: Flags = *cpu.flags();
let sum = Self::add_u16_i8(cpu.register_pair(RegisterPair::SP), d, &mut flags); let sum = Self::add_u16_i8(cpu.register_pair(RegisterPair::SP), d, &mut flags);
cpu.set_register_pair(RegisterPair::HL, sum); cpu.set_register_pair(RegisterPair::HL, sum);
Cycles::new(12) Cycles::new(12)
@ -1081,7 +1082,7 @@ impl Instruction {
} }
Instruction::RLC(reg) => { Instruction::RLC(reg) => {
// RLC r[z] | Rotate register r[z] left // RLC r[z] | Rotate register r[z] left
let mut flags: Flags = cpu.flags().clone(); let mut flags: Flags = *cpu.flags();
let msb; let msb;
let rot_reg; let rot_reg;
let cycles: Cycles; let cycles: Cycles;
@ -1121,7 +1122,7 @@ impl Instruction {
} }
Instruction::RRC(reg) => { Instruction::RRC(reg) => {
// RRC r[z] | Rotate Register r[z] right // RRC r[z] | Rotate Register r[z] right
let mut flags: Flags = cpu.flags().clone(); let mut flags: Flags = *cpu.flags();
let lsb; let lsb;
let rot_reg; let rot_reg;
let cycles: Cycles; let cycles: Cycles;
@ -1161,7 +1162,7 @@ impl Instruction {
} }
Instruction::RL(reg) => { Instruction::RL(reg) => {
// RL r[z] | Rotate register r[z] left through carry // RL r[z] | Rotate register r[z] left through carry
let mut flags: Flags = cpu.flags().clone(); let mut flags: Flags = *cpu.flags();
let carry; let carry;
let rot_reg; let rot_reg;
let cycles: Cycles; let cycles: Cycles;
@ -1204,7 +1205,7 @@ impl Instruction {
} }
Instruction::RR(reg) => { Instruction::RR(reg) => {
// RR r[z] | Rotate register r[z] right through carry // RR r[z] | Rotate register r[z] right through carry
let mut flags: Flags = cpu.flags().clone(); let mut flags: Flags = *cpu.flags();
let carry; let carry;
let rot_reg; let rot_reg;
let cycles: Cycles; let cycles: Cycles;
@ -1247,7 +1248,7 @@ impl Instruction {
} }
Instruction::SLA(reg) => { Instruction::SLA(reg) => {
// SLA r[z] | Shift left arithmetic register r[z] // SLA r[z] | Shift left arithmetic register r[z]
let mut flags: Flags = cpu.flags().clone(); let mut flags: Flags = *cpu.flags();
let shift_reg; let shift_reg;
let msb; let msb;
let cycles: Cycles; let cycles: Cycles;
@ -1288,7 +1289,7 @@ impl Instruction {
} }
Instruction::SRA(reg) => { Instruction::SRA(reg) => {
// SRA r[z] | Shift right arithmetic register r[z] // SRA r[z] | Shift right arithmetic register r[z]
let mut flags: Flags = cpu.flags().clone(); let mut flags: Flags = *cpu.flags();
let shift_reg; let shift_reg;
let lsb; let lsb;
let cycles: Cycles; let cycles: Cycles;
@ -1331,7 +1332,7 @@ impl Instruction {
} }
Instruction::SWAP(reg) => { Instruction::SWAP(reg) => {
// SWAP r[z] | Swap the 4 highest and lowest bits in a byte // SWAP r[z] | Swap the 4 highest and lowest bits in a byte
let mut flags: Flags = cpu.flags().clone(); let mut flags: Flags = *cpu.flags();
let swap_reg; let swap_reg;
let cycles: Cycles; let cycles: Cycles;
@ -1370,7 +1371,7 @@ impl Instruction {
} }
Instruction::SRL(reg) => { Instruction::SRL(reg) => {
// SRL r[z] | Shift right logic register r[z] // SRL r[z] | Shift right logic register r[z]
let mut flags: Flags = cpu.flags().clone(); let mut flags: Flags = *cpu.flags();
let lsb; let lsb;
let shift_reg; let shift_reg;
let cycles: Cycles; let cycles: Cycles;
@ -1411,7 +1412,7 @@ impl Instruction {
} }
Instruction::BIT(y, reg) => { Instruction::BIT(y, reg) => {
// BIT y, r[z] | Test y is in register r[z] // BIT y, r[z] | Test y is in register r[z]
let mut flags: Flags = cpu.flags().clone(); let mut flags: Flags = *cpu.flags();
let is_bit_set; let is_bit_set;
let cycles: Cycles; let cycles: Cycles;
match reg { match reg {
@ -1647,6 +1648,7 @@ impl Instruction {
fn from_unprefixed_byte(cpu: &mut Cpu, opcode: u8) -> Self { fn from_unprefixed_byte(cpu: &mut Cpu, opcode: u8) -> Self {
// https://gb-archive.github.io/salvage/decoding_gbz80_opcodes/Decoding%20Gamboy%20Z80%20Opcodes.html // https://gb-archive.github.io/salvage/decoding_gbz80_opcodes/Decoding%20Gamboy%20Z80%20Opcodes.html
let x = (opcode >> 6) & 0x03; let x = (opcode >> 6) & 0x03;
let y = (opcode >> 3) & 0x07; let y = (opcode >> 3) & 0x07;
let z = opcode & 0x07; let z = opcode & 0x07;

10
src/interrupt.rs
View File

@ -41,7 +41,7 @@ impl InterruptEnable {
pub fn set_vblank(&self, flag: &mut InterruptFlag, value: bool) { pub fn set_vblank(&self, flag: &mut InterruptFlag, value: bool) {
let prev = self._vblank(); let prev = self._vblank();
if prev == false && value { if !prev && value {
flag.set_vblank(true); flag.set_vblank(true);
} }
@ -51,7 +51,7 @@ impl InterruptEnable {
pub fn set_lcd_stat(&self, flag: &mut InterruptFlag, value: bool) { pub fn set_lcd_stat(&self, flag: &mut InterruptFlag, value: bool) {
let prev = self._lcd_stat(); let prev = self._lcd_stat();
if prev == false && value { if !prev && value {
flag.set_lcd_stat(true); flag.set_lcd_stat(true);
} }
@ -61,7 +61,7 @@ impl InterruptEnable {
pub fn set_timer(&self, flag: &mut InterruptFlag, value: bool) { pub fn set_timer(&self, flag: &mut InterruptFlag, value: bool) {
let prev = self._timer(); let prev = self._timer();
if prev == false && value { if !prev && value {
flag.set_timer(true); flag.set_timer(true);
} }
@ -71,7 +71,7 @@ impl InterruptEnable {
pub fn set_serial(&self, flag: &mut InterruptFlag, value: bool) { pub fn set_serial(&self, flag: &mut InterruptFlag, value: bool) {
let prev = self._serial(); let prev = self._serial();
if prev == false && value { if !prev && value {
flag.set_serial(true); flag.set_serial(true);
} }
@ -81,7 +81,7 @@ impl InterruptEnable {
pub fn set_joypad(&self, flag: &mut InterruptFlag, value: bool) { pub fn set_joypad(&self, flag: &mut InterruptFlag, value: bool) {
let prev = self._joypad(); let prev = self._joypad();
if prev == false && value { if !prev && value {
flag.set_joypad(true); flag.set_joypad(true);
} }

10
src/ppu.rs
View File

@ -4,7 +4,7 @@ use bitfield::bitfield;
const GB_WIDTH: usize = 160; const GB_WIDTH: usize = 160;
const GB_HEIGHT: usize = 144; const GB_HEIGHT: usize = 144;
#[derive(Debug, Clone)] #[derive(Debug, Clone)]
pub struct PPU { pub struct Ppu {
pub lcd_control: LCDControl, pub lcd_control: LCDControl,
pub monochrome: Monochrome, pub monochrome: Monochrome,
pub pos: ScreenPosition, pub pos: ScreenPosition,
@ -16,7 +16,7 @@ pub struct PPU {
mode: Mode, mode: Mode,
} }
impl PPU { impl Ppu {
pub fn step(&mut self, cycles: Cycles) { pub fn step(&mut self, cycles: Cycles) {
self.cycles += cycles; self.cycles += cycles;
@ -67,7 +67,7 @@ impl PPU {
} }
} }
impl Default for PPU { impl Default for Ppu {
fn default() -> Self { fn default() -> Self {
Self { Self {
lcd_control: Default::default(), lcd_control: Default::default(),
@ -131,7 +131,7 @@ impl From<LCDStatus> for u8 {
pub enum LCDMode { pub enum LCDMode {
HBlank = 0, HBlank = 0,
VBlank = 1, VBlank = 1,
OAM = 2, Oam = 2,
Transfer = 3, Transfer = 3,
} }
@ -140,7 +140,7 @@ impl From<u8> for LCDMode {
match byte { match byte {
0b00 => Self::HBlank, 0b00 => Self::HBlank,
0b01 => Self::VBlank, 0b01 => Self::VBlank,
0b10 => Self::OAM, 0b10 => Self::Oam,
0b11 => Self::Transfer, 0b11 => Self::Transfer,
_ => unreachable!("{:#04X} is not a valid value for LCDMode", byte), _ => unreachable!("{:#04X} is not a valid value for LCDMode", byte),
} }

12
src/work_ram.rs
View File

@ -1,9 +1,9 @@
#[derive(Debug, Clone)] #[derive(Debug, Clone)]
pub struct WorkRAM { pub struct WorkRam {
bank: Box<[u8]>, bank: Box<[u8]>,
} }
impl WorkRAM { impl WorkRam {
pub fn write_byte(&mut self, index: usize, byte: u8) { pub fn write_byte(&mut self, index: usize, byte: u8) {
self.bank[index] = byte; self.bank[index] = byte;
} }
@ -13,7 +13,7 @@ impl WorkRAM {
} }
} }
impl Default for WorkRAM { impl Default for WorkRam {
fn default() -> Self { fn default() -> Self {
Self { Self {
bank: vec![0u8; 4096].into_boxed_slice(), bank: vec![0u8; 4096].into_boxed_slice(),
@ -33,12 +33,12 @@ pub enum BankNumber {
} }
#[derive(Debug, Clone)] #[derive(Debug, Clone)]
pub struct VariableWorkRAM { pub struct VariableWorkRam {
current: BankNumber, current: BankNumber,
bank_n: Box<[[u8; 4096]]>, // 4K for Variable amount of Banks (Banks 1 -> 7) in Game Boy Colour bank_n: Box<[[u8; 4096]]>, // 4K for Variable amount of Banks (Banks 1 -> 7) in Game Boy Colour
} }
impl Default for VariableWorkRAM { impl Default for VariableWorkRam {
fn default() -> Self { fn default() -> Self {
Self { Self {
current: BankNumber::One, current: BankNumber::One,
@ -47,7 +47,7 @@ impl Default for VariableWorkRAM {
} }
} }
impl VariableWorkRAM { impl VariableWorkRam {
pub fn set_current_bank(&mut self, bank: BankNumber) { pub fn set_current_bank(&mut self, bank: BankNumber) {
self.current = bank; self.current = bank;
} }