From 19f642eafe5b585429eaff021810d1278493167a Mon Sep 17 00:00:00 2001 From: Rekai Musuka Date: Tue, 16 Mar 2021 01:05:13 -0500 Subject: [PATCH] chore: make clippy happy --- src/bus.rs | 14 ++++----- src/cartridge.rs | 46 ++++++++++++++-------------- src/cpu.rs | 4 +-- src/high_ram.rs | 6 ++-- src/instruction.rs | 76 ++++++++++++++++++++++++---------------------- src/interrupt.rs | 10 +++--- src/ppu.rs | 10 +++--- src/work_ram.rs | 12 ++++---- 8 files changed, 90 insertions(+), 88 deletions(-) diff --git a/src/bus.rs b/src/bus.rs index 1abf1c0..05fcd03 100644 --- a/src/bus.rs +++ b/src/bus.rs @@ -1,25 +1,25 @@ use super::cartridge::Cartridge; -use super::high_ram::HighRAM; +use super::high_ram::HighRam; use super::instruction::Cycles; use super::interrupt::Interrupt; -use super::ppu::PPU; +use super::ppu::Ppu; use super::serial::Serial; use super::sound::Sound; use super::timer::Timer; -use super::work_ram::{VariableWorkRAM, WorkRAM}; +use super::work_ram::{VariableWorkRam, WorkRam}; use std::{convert::TryInto, fs::File, io::Read}; #[derive(Debug, Clone)] pub struct Bus { boot: Option<[u8; 256]>, // Boot ROM is 256b long cartridge: Option, - pub ppu: PPU, - wram: WorkRAM, - vwram: VariableWorkRAM, + pub ppu: Ppu, + wram: WorkRam, + vwram: VariableWorkRam, timer: Timer, interrupt: Interrupt, sound: Sound, - hram: HighRAM, + hram: HighRam, serial: Serial, } diff --git a/src/cartridge.rs b/src/cartridge.rs index f8b863e..bf937fb 100644 --- a/src/cartridge.rs +++ b/src/cartridge.rs @@ -5,7 +5,7 @@ use std::path::Path; #[derive(Debug, Clone, Default)] pub struct Cartridge { memory: Vec, - mbc: Box, + mbc: Box, } impl Cartridge { @@ -20,7 +20,7 @@ impl Cartridge { }) } - fn detect_mbc(memory: &[u8]) -> Box { + fn detect_mbc(memory: &[u8]) -> Box { let ram_size = Self::find_ram_size(&memory); let bank_count = Self::find_bank_count(&memory); let mbc_kind = Self::find_mbc(&memory); @@ -40,7 +40,7 @@ impl Cartridge { Box::new(mbc) } - fn find_ram_size(memory: &[u8]) -> RAMSize { + fn find_ram_size(memory: &[u8]) -> RamSize { let id = memory[0x0149]; id.into() } @@ -89,7 +89,7 @@ struct MBC1 { current_rom_bank: u8, // 5-bit Number current_ram_bank: u8, // 2-bit number mode: bool, - ram_size: RAMSize, + ram_size: RamSize, ram: Box<[u8]>, bank_count: BankCount, ram_enabled: bool, @@ -139,7 +139,7 @@ impl MBC1 { } } -impl MBC for MBC1 { +impl Mbc for MBC1 { fn handle_read(&self, addr: u16) -> MBCResult { use MBCResult::*; @@ -159,10 +159,10 @@ impl MBC for MBC1 { 0xA000..=0xBFFF => { if self.ram_enabled { let ram_addr = match self.ram_size { - RAMSize::_2KB | RAMSize::_8KB => { + RamSize::_2KB | RamSize::_8KB => { (addr as u32 - 0xA000) % self.ram_size.to_byte_count() } - RAMSize::_32KB => { + RamSize::_32KB => { if self.mode { 0x2000 * self.current_ram_bank as u32 + (addr as u32 - 0xA000) } else { @@ -196,17 +196,17 @@ impl MBC for MBC1 { 0xA000..=0xBFFF => { if self.ram_enabled { let ram_addr = match self.ram_size { - RAMSize::_2KB | RAMSize::_8KB => { + RamSize::_2KB | RamSize::_8KB => { (addr as u32 - 0xA000) % self.ram_size.to_byte_count() } - RAMSize::_32KB => { + RamSize::_32KB => { if self.mode { 0x2000 * (self.current_ram_bank as u32) + (addr as u32 - 0xA000) } else { addr as u32 - 0xA000 } } - _ => unreachable!("RAMSize can not be greater than 32KB on MBC1"), + _ => unreachable!("RAM size can not be greater than 32KB on MBC1"), }; self.ram[ram_addr as usize] = byte; @@ -217,20 +217,20 @@ impl MBC for MBC1 { } } -trait MBC: CloneMBC { +trait Mbc: CloneMBC { fn handle_read(&self, addr: u16) -> MBCResult; fn handle_write(&mut self, addr: u16, byte: u8); } trait CloneMBC { - fn clone_mbc<'a>(&self) -> Box; + fn clone_mbc(&self) -> Box; } impl CloneMBC for T where - T: MBC + Clone + 'static, + T: Mbc + Clone + 'static, { - fn clone_mbc<'a>(&self) -> Box { + fn clone_mbc<'a>(&self) -> Box { Box::new(self.clone()) } } @@ -254,7 +254,7 @@ impl Default for MBCKind { } #[derive(Debug, Clone, Copy)] -enum RAMSize { +enum RamSize { None = 0, _2KB = 1, _8KB = 2, @@ -263,9 +263,9 @@ enum RAMSize { _64KB = 5, // Split into 8 RAm Banks } -impl RAMSize { +impl RamSize { pub fn to_byte_count(&self) -> u32 { - use RAMSize::*; + use RamSize::*; match *self { None => 0, @@ -278,15 +278,15 @@ impl RAMSize { } } -impl Default for RAMSize { +impl Default for RamSize { fn default() -> Self { Self::None } } -impl From for RAMSize { +impl From for RamSize { fn from(byte: u8) -> Self { - use RAMSize::*; + use RamSize::*; match byte { 0x00 => None, @@ -366,19 +366,19 @@ impl From for BankCount { } } -impl std::fmt::Debug for Box { +impl std::fmt::Debug for Box { fn fmt(&self, _f: &mut std::fmt::Formatter<'_>) -> std::fmt::Result { todo!("Implement Debug for Box Trait Object"); } } -impl std::clone::Clone for Box { +impl std::clone::Clone for Box { fn clone(&self) -> Self { self.clone_mbc() } } -impl std::default::Default for Box { +impl std::default::Default for Box { fn default() -> Self { Box::new(MBC1::default()) } diff --git a/src/cpu.rs b/src/cpu.rs index 910bb64..3b65951 100644 --- a/src/cpu.rs +++ b/src/cpu.rs @@ -1,6 +1,6 @@ use super::bus::Bus; use super::instruction::{Cycles, Instruction}; -use super::ppu::PPU; +use super::ppu::Ppu; use bitfield::bitfield; use std::{ fmt::{Display, Formatter, Result as FmtResult}, @@ -130,7 +130,7 @@ impl Cpu { } impl Cpu { - pub fn get_ppu(&mut self) -> &mut PPU { + pub fn get_ppu(&mut self) -> &mut Ppu { &mut self.bus.ppu } } diff --git a/src/high_ram.rs b/src/high_ram.rs index b445753..b7a871b 100644 --- a/src/high_ram.rs +++ b/src/high_ram.rs @@ -1,9 +1,9 @@ #[derive(Debug, Clone)] -pub struct HighRAM { +pub struct HighRam { buf: Box<[u8]>, } -impl Default for HighRAM { +impl Default for HighRam { fn default() -> Self { Self { buf: vec![0u8; 128].into_boxed_slice(), @@ -11,7 +11,7 @@ impl Default for HighRAM { } } -impl HighRAM { +impl HighRam { pub fn write_byte(&mut self, index: usize, byte: u8) { self.buf[index] = byte; } diff --git a/src/instruction.rs b/src/instruction.rs index 898902d..1af60bc 100644 --- a/src/instruction.rs +++ b/src/instruction.rs @@ -2,6 +2,7 @@ use super::cpu::{Cpu, Flags, Register, RegisterPair}; use std::{convert::TryFrom, fmt::Debug}; #[derive(Debug, Copy, Clone)] +#[allow(clippy::upper_case_acronyms)] pub enum Instruction { NOP, LD(LDTarget, LDTarget), @@ -342,7 +343,7 @@ impl Instruction { Instruction::ADD(lhs, rhs) => match (lhs, rhs) { (MATHTarget::RegisterPair(RegisterPair::HL), MATHTarget::RegisterPair(pair)) => { // ADD HL, rp[p] | add register pair to HL. - let mut flags: Flags = cpu.flags().clone(); + let mut flags: Flags = *cpu.flags(); match pair { RegisterPair::BC @@ -362,7 +363,7 @@ impl Instruction { } (MATHTarget::Register(InstrRegister::A), MATHTarget::Register(reg)) => { // ADD A, r[z] | Add (A + r[z]) to register A - let mut flags: Flags = cpu.flags().clone(); + let mut flags: Flags = *cpu.flags(); let a_value = cpu.register(Register::A); let sum; let cycles: Cycles; @@ -391,7 +392,7 @@ impl Instruction { } (MATHTarget::RegisterPair(RegisterPair::SP), MATHTarget::ImmediateByte(d)) => { // ADD SP, d | Add d (is signed) to register pair SP. - let mut flags: Flags = cpu.flags().clone(); + let mut flags: Flags = *cpu.flags(); let d = d as i8; let sum = Self::add_u16_i8(cpu.register_pair(RegisterPair::SP), d, &mut flags); cpu.set_register_pair(RegisterPair::SP, sum); @@ -399,7 +400,7 @@ impl Instruction { } (MATHTarget::Register(InstrRegister::A), MATHTarget::ImmediateByte(n)) => { // ADD A, n | Add n to register A - let mut flags: Flags = cpu.flags().clone(); + let mut flags: Flags = *cpu.flags(); let sum = Self::add_u8s(cpu.register(Register::A), n, &mut flags); cpu.set_register(Register::A, sum); @@ -412,7 +413,7 @@ impl Instruction { match registers { Registers::Byte(reg) => { // INC r[y] | Increment Register - let mut flags: Flags = cpu.flags().clone(); + let mut flags: Flags = *cpu.flags(); let cycles: Cycles; match reg { @@ -468,7 +469,7 @@ impl Instruction { } Instruction::DEC(Registers::Byte(reg)) => { // DEC r[y] | Decrement Register - let mut flags: Flags = cpu.flags().clone(); + let mut flags: Flags = *cpu.flags(); let cycles: Cycles; match reg { @@ -497,7 +498,7 @@ impl Instruction { } Instruction::RLCA => { // Rotate Register A left - let mut flags: Flags = cpu.flags().clone(); + let mut flags: Flags = *cpu.flags(); let a = cpu.register(Register::A); let msb = a >> 7; @@ -510,7 +511,7 @@ impl Instruction { } Instruction::RRCA => { // Rotate Register A right - let mut flags: Flags = cpu.flags().clone(); + let mut flags: Flags = *cpu.flags(); let a = cpu.register(Register::A); let lsb = a & 0x01; @@ -523,7 +524,7 @@ impl Instruction { } Instruction::RLA => { // Rotate register A left through carry - let mut flags: Flags = cpu.flags().clone(); + let mut flags: Flags = *cpu.flags(); let a = cpu.register(Register::A); let (rot_a, carry) = Self::rl_thru_carry(a, flags.c()); @@ -535,7 +536,7 @@ impl Instruction { } Instruction::RRA => { // Rotate register A right through carry - let mut flags: Flags = cpu.flags().clone(); + let mut flags: Flags = *cpu.flags(); let a = cpu.register(Register::A); let (rot_a, carry) = Self::rr_thru_carry(a, flags.c()); @@ -548,7 +549,7 @@ impl Instruction { Instruction::DAA => unimplemented!(), Instruction::CPL => { // Compliment A register (inverse) - let mut flags: Flags = cpu.flags().clone(); + let mut flags: Flags = *cpu.flags(); let a = cpu.register(Register::A); flags.set_n(true); @@ -560,7 +561,7 @@ impl Instruction { } Instruction::SCF => { // Set Carry Flag - let mut flags: Flags = cpu.flags().clone(); + let mut flags: Flags = *cpu.flags(); flags.set_n(false); flags.set_h(false); @@ -571,7 +572,7 @@ impl Instruction { } Instruction::CCF => { // Compliment Carry Flag (inverse) - let mut flags: Flags = cpu.flags().clone(); + let mut flags: Flags = *cpu.flags(); flags.set_n(false); flags.set_h(false); @@ -585,7 +586,7 @@ impl Instruction { MATHTarget::Register(reg) => { // ADC A, r[z] | Add register r[z] plus the Carry flag to A // FIXME: Do I Add register A as well? - let mut flags: Flags = cpu.flags().clone(); + let mut flags: Flags = *cpu.flags(); let a_value = cpu.register(Register::A); let cycles: Cycles; let sum; @@ -615,7 +616,7 @@ impl Instruction { } MATHTarget::ImmediateByte(n) => { // ADC A, n | Add immediate byte plus the carry flag to A - let mut flags: Flags = cpu.flags().clone(); + let mut flags: Flags = *cpu.flags(); let value = n + (flags.c() as u8); let sum = Self::add_u8s(cpu.register(Register::A), value, &mut flags); @@ -628,7 +629,7 @@ impl Instruction { Instruction::SUB(target) => match target { MATHTarget::Register(reg) => { // SUB r[z] | Subtract the value in register r[z] from register A, then store in A - let mut flags: Flags = cpu.flags().clone(); + let mut flags: Flags = *cpu.flags(); let a_value = cpu.register(Register::A); let cycles: Cycles; let diff; @@ -658,7 +659,7 @@ impl Instruction { } MATHTarget::ImmediateByte(n) => { // SUB n | Subtract the immediate byte from register A, then store in A - let mut flags: Flags = cpu.flags().clone(); + let mut flags: Flags = *cpu.flags(); let diff = Self::sub_u8s(cpu.register(Register::A), n, &mut flags); cpu.set_flags(flags); @@ -671,7 +672,7 @@ impl Instruction { MATHTarget::Register(reg) => { // SBC A, r[z] | Subtract the value from register r[z] from A, add the Carry flag and then store in A // FIXME: See ADC, is this a correct understanding of this Instruction - let mut flags: Flags = cpu.flags().clone(); + let mut flags: Flags = *cpu.flags(); let a_value = cpu.register(Register::A); let cycles: Cycles; let diff; @@ -703,7 +704,7 @@ impl Instruction { MATHTarget::ImmediateByte(n) => { // SBC A, n | Subtract the value from immediate byte from A, add the carry flag and then store in A // FIXME: The Fixme above applies to this variant as well - let mut flags: Flags = cpu.flags().clone(); + let mut flags: Flags = *cpu.flags(); let value = n + (flags.c() as u8); let diff = Self::sub_u8s(cpu.register(Register::A), value, &mut flags); @@ -716,7 +717,7 @@ impl Instruction { Instruction::AND(target) => match target { MATHTarget::Register(reg) => { // AND r[z] | Bitwise AND register r[z] and register A, store in register A - let mut flags: Flags = cpu.flags().clone(); + let mut flags: Flags = *cpu.flags(); let a_value = cpu.register(Register::A); let cycles: Cycles; let result; @@ -747,7 +748,7 @@ impl Instruction { } MATHTarget::ImmediateByte(n) => { // AND n | Bitwise AND immediate byte and register A, store in register A - let mut flags: Flags = cpu.flags().clone(); + let mut flags: Flags = *cpu.flags(); let result = cpu.register(Register::A) & n; flags.update(result == 0, false, true, false); @@ -760,7 +761,7 @@ impl Instruction { Instruction::XOR(target) => match target { MATHTarget::Register(reg) => { // XOR r[z] | Bitwise XOR register r[z] and register A, store in register A - let mut flags: Flags = cpu.flags().clone(); + let mut flags: Flags = *cpu.flags(); let a_value = cpu.register(Register::A); let cycles: Cycles; let result; @@ -791,7 +792,7 @@ impl Instruction { } MATHTarget::ImmediateByte(n) => { // XOR n | Bitwise XOR immediate byte and register A, store in register A - let mut flags: Flags = cpu.flags().clone(); + let mut flags: Flags = *cpu.flags(); let result = cpu.register(Register::A) ^ n; flags.update(result == 0, false, false, false); @@ -804,7 +805,7 @@ impl Instruction { Instruction::OR(target) => match target { MATHTarget::Register(reg) => { // OR r[z] | Bitwise OR register r[z] and register A, store in register A - let mut flags: Flags = cpu.flags().clone(); + let mut flags: Flags = *cpu.flags(); let a_value = cpu.register(Register::A); let cycles: Cycles; let result; @@ -835,7 +836,7 @@ impl Instruction { } MATHTarget::ImmediateByte(n) => { // OR n | Bitwise OR on immediate byte n and register A, store in register A - let mut flags: Flags = cpu.flags().clone(); + let mut flags: Flags = *cpu.flags(); let result = cpu.register(Register::A) | n; flags.update(result == 0, false, false, false); @@ -848,7 +849,7 @@ impl Instruction { Instruction::CP(target) => match target { MATHTarget::Register(reg) => { // CP r[z] | Same behaviour as SUB, except the result is not stored. - let mut flags: Flags = cpu.flags().clone(); + let mut flags: Flags = *cpu.flags(); let a_value = cpu.register(Register::A); let cycles: Cycles; @@ -876,7 +877,7 @@ impl Instruction { } MATHTarget::ImmediateByte(n) => { // CP n | Same behaviour as SUB, except the result is not stored, - let mut flags: Flags = cpu.flags().clone(); + let mut flags: Flags = *cpu.flags(); let _ = Self::sub_u8s(cpu.register(Register::A), n, &mut flags); cpu.set_flags(flags); @@ -932,7 +933,7 @@ impl Instruction { Instruction::LDHL(d) => { // LDHL SP + d | Add SP + d to register HL // LD HL, SP + d | Add SP + d to register HL - let mut flags: Flags = cpu.flags().clone(); + let mut flags: Flags = *cpu.flags(); let sum = Self::add_u16_i8(cpu.register_pair(RegisterPair::SP), d, &mut flags); cpu.set_register_pair(RegisterPair::HL, sum); Cycles::new(12) @@ -1081,7 +1082,7 @@ impl Instruction { } Instruction::RLC(reg) => { // RLC r[z] | Rotate register r[z] left - let mut flags: Flags = cpu.flags().clone(); + let mut flags: Flags = *cpu.flags(); let msb; let rot_reg; let cycles: Cycles; @@ -1121,7 +1122,7 @@ impl Instruction { } Instruction::RRC(reg) => { // RRC r[z] | Rotate Register r[z] right - let mut flags: Flags = cpu.flags().clone(); + let mut flags: Flags = *cpu.flags(); let lsb; let rot_reg; let cycles: Cycles; @@ -1161,7 +1162,7 @@ impl Instruction { } Instruction::RL(reg) => { // RL r[z] | Rotate register r[z] left through carry - let mut flags: Flags = cpu.flags().clone(); + let mut flags: Flags = *cpu.flags(); let carry; let rot_reg; let cycles: Cycles; @@ -1204,7 +1205,7 @@ impl Instruction { } Instruction::RR(reg) => { // RR r[z] | Rotate register r[z] right through carry - let mut flags: Flags = cpu.flags().clone(); + let mut flags: Flags = *cpu.flags(); let carry; let rot_reg; let cycles: Cycles; @@ -1247,7 +1248,7 @@ impl Instruction { } Instruction::SLA(reg) => { // SLA r[z] | Shift left arithmetic register r[z] - let mut flags: Flags = cpu.flags().clone(); + let mut flags: Flags = *cpu.flags(); let shift_reg; let msb; let cycles: Cycles; @@ -1288,7 +1289,7 @@ impl Instruction { } Instruction::SRA(reg) => { // SRA r[z] | Shift right arithmetic register r[z] - let mut flags: Flags = cpu.flags().clone(); + let mut flags: Flags = *cpu.flags(); let shift_reg; let lsb; let cycles: Cycles; @@ -1331,7 +1332,7 @@ impl Instruction { } Instruction::SWAP(reg) => { // SWAP r[z] | Swap the 4 highest and lowest bits in a byte - let mut flags: Flags = cpu.flags().clone(); + let mut flags: Flags = *cpu.flags(); let swap_reg; let cycles: Cycles; @@ -1370,7 +1371,7 @@ impl Instruction { } Instruction::SRL(reg) => { // SRL r[z] | Shift right logic register r[z] - let mut flags: Flags = cpu.flags().clone(); + let mut flags: Flags = *cpu.flags(); let lsb; let shift_reg; let cycles: Cycles; @@ -1411,7 +1412,7 @@ impl Instruction { } Instruction::BIT(y, reg) => { // BIT y, r[z] | Test y is in register r[z] - let mut flags: Flags = cpu.flags().clone(); + let mut flags: Flags = *cpu.flags(); let is_bit_set; let cycles: Cycles; match reg { @@ -1647,6 +1648,7 @@ impl Instruction { fn from_unprefixed_byte(cpu: &mut Cpu, opcode: u8) -> Self { // https://gb-archive.github.io/salvage/decoding_gbz80_opcodes/Decoding%20Gamboy%20Z80%20Opcodes.html + let x = (opcode >> 6) & 0x03; let y = (opcode >> 3) & 0x07; let z = opcode & 0x07; diff --git a/src/interrupt.rs b/src/interrupt.rs index e4d7362..0f5afff 100644 --- a/src/interrupt.rs +++ b/src/interrupt.rs @@ -41,7 +41,7 @@ impl InterruptEnable { pub fn set_vblank(&self, flag: &mut InterruptFlag, value: bool) { let prev = self._vblank(); - if prev == false && value { + if !prev && value { flag.set_vblank(true); } @@ -51,7 +51,7 @@ impl InterruptEnable { pub fn set_lcd_stat(&self, flag: &mut InterruptFlag, value: bool) { let prev = self._lcd_stat(); - if prev == false && value { + if !prev && value { flag.set_lcd_stat(true); } @@ -61,7 +61,7 @@ impl InterruptEnable { pub fn set_timer(&self, flag: &mut InterruptFlag, value: bool) { let prev = self._timer(); - if prev == false && value { + if !prev && value { flag.set_timer(true); } @@ -71,7 +71,7 @@ impl InterruptEnable { pub fn set_serial(&self, flag: &mut InterruptFlag, value: bool) { let prev = self._serial(); - if prev == false && value { + if !prev && value { flag.set_serial(true); } @@ -81,7 +81,7 @@ impl InterruptEnable { pub fn set_joypad(&self, flag: &mut InterruptFlag, value: bool) { let prev = self._joypad(); - if prev == false && value { + if !prev && value { flag.set_joypad(true); } diff --git a/src/ppu.rs b/src/ppu.rs index a5ea5e9..c59f247 100644 --- a/src/ppu.rs +++ b/src/ppu.rs @@ -4,7 +4,7 @@ use bitfield::bitfield; const GB_WIDTH: usize = 160; const GB_HEIGHT: usize = 144; #[derive(Debug, Clone)] -pub struct PPU { +pub struct Ppu { pub lcd_control: LCDControl, pub monochrome: Monochrome, pub pos: ScreenPosition, @@ -16,7 +16,7 @@ pub struct PPU { mode: Mode, } -impl PPU { +impl Ppu { pub fn step(&mut self, cycles: Cycles) { self.cycles += cycles; @@ -67,7 +67,7 @@ impl PPU { } } -impl Default for PPU { +impl Default for Ppu { fn default() -> Self { Self { lcd_control: Default::default(), @@ -131,7 +131,7 @@ impl From for u8 { pub enum LCDMode { HBlank = 0, VBlank = 1, - OAM = 2, + Oam = 2, Transfer = 3, } @@ -140,7 +140,7 @@ impl From for LCDMode { match byte { 0b00 => Self::HBlank, 0b01 => Self::VBlank, - 0b10 => Self::OAM, + 0b10 => Self::Oam, 0b11 => Self::Transfer, _ => unreachable!("{:#04X} is not a valid value for LCDMode", byte), } diff --git a/src/work_ram.rs b/src/work_ram.rs index 53c6360..0f2fcca 100644 --- a/src/work_ram.rs +++ b/src/work_ram.rs @@ -1,9 +1,9 @@ #[derive(Debug, Clone)] -pub struct WorkRAM { +pub struct WorkRam { bank: Box<[u8]>, } -impl WorkRAM { +impl WorkRam { pub fn write_byte(&mut self, index: usize, byte: u8) { self.bank[index] = byte; } @@ -13,7 +13,7 @@ impl WorkRAM { } } -impl Default for WorkRAM { +impl Default for WorkRam { fn default() -> Self { Self { bank: vec![0u8; 4096].into_boxed_slice(), @@ -33,12 +33,12 @@ pub enum BankNumber { } #[derive(Debug, Clone)] -pub struct VariableWorkRAM { +pub struct VariableWorkRam { current: BankNumber, bank_n: Box<[[u8; 4096]]>, // 4K for Variable amount of Banks (Banks 1 -> 7) in Game Boy Colour } -impl Default for VariableWorkRAM { +impl Default for VariableWorkRam { fn default() -> Self { Self { current: BankNumber::One, @@ -47,7 +47,7 @@ impl Default for VariableWorkRAM { } } -impl VariableWorkRAM { +impl VariableWorkRam { pub fn set_current_bank(&mut self, bank: BankNumber) { self.current = bank; }