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chore: panic TODO on Unconditional address space

This commit is contained in:
Rekai Nyangadzayi Musuka 2023-09-15 14:49:36 -05:00
parent 30cf951d2a
commit a3eefa6432
2 changed files with 29 additions and 22 deletions
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17
src/arm.zig
View File

@ -9,7 +9,8 @@ const Coprocessor = @import("lib.zig").Coprocessor;
const Bitfield = @import("bitfield").Bitfield;
const Bit = @import("bitfield").Bit;
const condition_lut = [_]u16{
fn condition_lut(comptime isa: Architecture) [16]u16 {
return [_]u16{
0xF0F0, // EQ - Equal
0x0F0F, // NE - Not Equal
0xCCCC, // CS - Unsigned higher or same
@ -25,8 +26,9 @@ const condition_lut = [_]u16{
0x0A05, // GT - greater than
0xF5FA, // LE - less than or equal
0xFFFF, // AL - always
0x0000, // NV - never
if (isa == .v4t) 0x0000 else 0xFFFF, // NV - never
};
}
pub fn Arm32(comptime isa: Architecture) type {
const is_v5te = isa == .v5te;
@ -365,8 +367,13 @@ pub fn Arm32(comptime isa: Architecture) type {
thumb.lut[thumb.idx(opcode)](self, opcode);
} else {
const opcode = self.pipe.step(self, u32) orelse return;
const cond: u4 = @truncate(opcode >> 28);
if (self.cpsr.check(Self.arch, cond)) {
if (isa == .v5te and cond == 0b1111) {
self.panic("TODO: Unconditional Instruction Extension Space\nopcode: 0x{X:0>8} | idx: 0x{X:} | ptr: {any}", .{ opcode, arm.idx(opcode), arm.lut[arm.idx(opcode)] });
}
if (self.cpsr.check(@truncate(opcode >> 28))) {
arm.lut[arm.idx(opcode)](self, opcode);
}
}
@ -499,9 +506,9 @@ pub const PSR = extern union {
std.debug.print("]\n", .{});
}
pub inline fn check(self: @This(), cond: u4) bool {
pub inline fn check(self: @This(), isa: Architecture, cond: u4) bool {
const flags: u4 = @truncate(self.raw >> 28);
return condition_lut[cond] & (@as(u16, 1) << flags) != 0;
return condition_lut(isa)[cond] & (@as(u16, 1) << flags) != 0;
}
};

2
src/arm/cpu/thumb/branch.zig
View File

@ -9,7 +9,7 @@ pub fn fmt16(comptime InstrFn: type, comptime cond: u4) InstrFn {
if (cond == 0xE or cond == 0xF)
cpu.panic("[CPU/THUMB.16] Undefined conditional branch with condition {}", .{cond});
if (!cpu.cpsr.check(cond)) return;
if (!cpu.cpsr.check(Arm32.arch, cond)) return;
cpu.r[15] +%= sext(u32, u8, opcode & 0xFF) << 1;
cpu.pipe.reload(cpu);