From a3eefa643268617d10e47ca972c4ba5bd05f131e Mon Sep 17 00:00:00 2001
From: Rekai Musuka <rekai@musuka.dev>
Date: Fri, 15 Sep 2023 14:49:36 -0500
Subject: [PATCH] chore: panic TODO on Unconditional address space

---
 src/arm.zig                  | 49 ++++++++++++++++++++----------------
 src/arm/cpu/thumb/branch.zig |  2 +-
 2 files changed, 29 insertions(+), 22 deletions(-)

diff --git a/src/arm.zig b/src/arm.zig
index 5a622bd..7ef3ac1 100644
--- a/src/arm.zig
+++ b/src/arm.zig
@@ -9,24 +9,26 @@ const Coprocessor = @import("lib.zig").Coprocessor;
 const Bitfield = @import("bitfield").Bitfield;
 const Bit = @import("bitfield").Bit;
 
-const condition_lut = [_]u16{
-    0xF0F0, // EQ - Equal
-    0x0F0F, // NE - Not Equal
-    0xCCCC, // CS - Unsigned higher or same
-    0x3333, // CC - Unsigned lower
-    0xFF00, // MI - Negative
-    0x00FF, // PL - Positive or Zero
-    0xAAAA, // VS - Overflow
-    0x5555, // VC - No Overflow
-    0x0C0C, // HI - unsigned hierh
-    0xF3F3, // LS - unsigned lower or same
-    0xAA55, // GE - greater or equal
-    0x55AA, // LT - less than
-    0x0A05, // GT - greater than
-    0xF5FA, // LE - less than or equal
-    0xFFFF, // AL - always
-    0x0000, // NV - never
-};
+fn condition_lut(comptime isa: Architecture) [16]u16 {
+    return [_]u16{
+        0xF0F0, // EQ - Equal
+        0x0F0F, // NE - Not Equal
+        0xCCCC, // CS - Unsigned higher or same
+        0x3333, // CC - Unsigned lower
+        0xFF00, // MI - Negative
+        0x00FF, // PL - Positive or Zero
+        0xAAAA, // VS - Overflow
+        0x5555, // VC - No Overflow
+        0x0C0C, // HI - unsigned hierh
+        0xF3F3, // LS - unsigned lower or same
+        0xAA55, // GE - greater or equal
+        0x55AA, // LT - less than
+        0x0A05, // GT - greater than
+        0xF5FA, // LE - less than or equal
+        0xFFFF, // AL - always
+        if (isa == .v4t) 0x0000 else 0xFFFF, // NV - never
+    };
+}
 
 pub fn Arm32(comptime isa: Architecture) type {
     const is_v5te = isa == .v5te;
@@ -365,8 +367,13 @@ pub fn Arm32(comptime isa: Architecture) type {
                 thumb.lut[thumb.idx(opcode)](self, opcode);
             } else {
                 const opcode = self.pipe.step(self, u32) orelse return;
+                const cond: u4 = @truncate(opcode >> 28);
+
+                if (self.cpsr.check(Self.arch, cond)) {
+                    if (isa == .v5te and cond == 0b1111) {
+                        self.panic("TODO: Unconditional Instruction Extension Space\nopcode: 0x{X:0>8} | idx: 0x{X:} | ptr: {any}", .{ opcode, arm.idx(opcode), arm.lut[arm.idx(opcode)] });
+                    }
 
-                if (self.cpsr.check(@truncate(opcode >> 28))) {
                     arm.lut[arm.idx(opcode)](self, opcode);
                 }
             }
@@ -499,9 +506,9 @@ pub const PSR = extern union {
         std.debug.print("]\n", .{});
     }
 
-    pub inline fn check(self: @This(), cond: u4) bool {
+    pub inline fn check(self: @This(), isa: Architecture, cond: u4) bool {
         const flags: u4 = @truncate(self.raw >> 28);
 
-        return condition_lut[cond] & (@as(u16, 1) << flags) != 0;
+        return condition_lut(isa)[cond] & (@as(u16, 1) << flags) != 0;
     }
 };
diff --git a/src/arm/cpu/thumb/branch.zig b/src/arm/cpu/thumb/branch.zig
index d2c287c..a011746 100644
--- a/src/arm/cpu/thumb/branch.zig
+++ b/src/arm/cpu/thumb/branch.zig
@@ -9,7 +9,7 @@ pub fn fmt16(comptime InstrFn: type, comptime cond: u4) InstrFn {
             if (cond == 0xE or cond == 0xF)
                 cpu.panic("[CPU/THUMB.16] Undefined conditional branch with condition {}", .{cond});
 
-            if (!cpu.cpsr.check(cond)) return;
+            if (!cpu.cpsr.check(Arm32.arch, cond)) return;
 
             cpu.r[15] +%= sext(u32, u8, opcode & 0xFF) << 1;
             cpu.pipe.reload(cpu);