267 lines
9.8 KiB
Zig
267 lines
9.8 KiB
Zig
const std = @import("std");
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const disp = @import("display.zig");
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const util = @import("util.zig");
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const sched = @import("scheduler.zig");
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const Chip8 = @import("chip8.zig").Chip8;
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const Instruction = @import("instruction.zig").Instruction;
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const Point = disp.Point;
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const Display = disp.Display;
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const Scheduler = sched.Scheduler;
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const EventKind = sched.EventKind;
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const OPS_PER_HZ = sched.OPS_PER_HZ;
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const panic = std.debug.panic;
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var prng = std.rand.DefaultPrng.init(1337);
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pub const Cpu = struct {
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i: u16,
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pc: u16,
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sp: u16,
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v: [16]u8,
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stack: [16]u16,
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scheduler: *Scheduler,
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pub fn new(scheduler: *Scheduler) Cpu {
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return .{
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.i = 0x0000,
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.pc = 0x0200,
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.sp = 0x0000,
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.v = [_]u8{0x00} ** 16,
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.stack = [_]u16{0x0000} ** 16,
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.scheduler = scheduler,
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};
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}
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};
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pub fn step(cpu: *Cpu, display: *Display, mem: *[0x1000]u8) u64 {
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const opcode = fetch(cpu, mem);
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// std.log.debug("0x{X:}", .{opcode});
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execute(cpu, display, mem, decode(opcode));
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return 1;
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}
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fn fetch(cpu: *Cpu, mem: *[0x1000]u8) u16 {
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const high: u16 = mem[cpu.pc];
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const low: u16 = mem[cpu.pc + 1];
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cpu.pc += 2;
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return high << 8 | low;
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}
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fn decode(opcode: u16) Instruction {
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const n1: u4 = @intCast(u4, (opcode & 0xF000) >> 12);
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const n2: u4 = @intCast(u4, (opcode & 0x0F00) >> 8);
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const n3: u4 = @intCast(u4, (opcode & 0x00F0) >> 4);
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const n4: u4 = @intCast(u4, (opcode & 0x000F) >> 0);
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return switch (n1) {
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0x0 => switch (n4) {
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0x0 => return Instruction.CLS, // 0x00E0 | CLS
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0xE => return Instruction.RET, // 0x00EE | RET
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else => panic("0x{X:} is an unknown 0x0-prefixed opcode", .{opcode}),
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},
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0x1 => Instruction{ .JP = util.calc12bit(n2, n3, n4) }, // 0x1nnn | JP u12
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0x2 => Instruction{ .CALL = util.calc12bit(n2, n3, n4) }, // 0x2nnn | CALL u12
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0x3 => Instruction{ .SE_Vx = .{ .x = n2, .kk = util.calc8bit(n3, n4) } }, // 0x3xkk | SE Vx, u8
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0x4 => Instruction{ .SNE_Vx = .{ .x = n2, .kk = util.calc8bit(n3, n4) } }, // 0x4xkk | SNE Vx, u8
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0x5 => Instruction{ .SE_Vx_Vy = .{ .x = n2, .y = n3 } }, // 0x5xy0 | SE Vx, Vy
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0x6 => Instruction{ .LD_Vx = .{ .x = n2, .kk = util.calc8bit(n3, n4) } }, // 0x6xkk | LD Vx, u8
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0x7 => Instruction{ .ADD_Vx = .{ .x = n2, .kk = util.calc8bit(n3, n4) } }, // 0x7xkk | ADD Vx, u8
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0x8 => switch (n4) {
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0x0 => return Instruction{ .LD_Vx_Vy = .{ .x = n2, .y = n3 } }, // 0x8xy0 | LD Vx, Vy
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0x1 => return Instruction{ .OR = .{ .x = n2, .y = n3 } }, // 0x8xy1 | OR Vx, Vy
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0x2 => return Instruction{ .AND = .{ .x = n2, .y = n3 } }, // 0x8xy2 | AND Vx, Vy
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0x3 => return Instruction{ .XOR = .{ .x = n2, .y = n3 } }, // 0x8xy3 | XOR Vx, Vy
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0x4 => return Instruction{ .ADD_Vx_Vy = .{ .x = n2, .y = n3 } }, // 0x8xy4 | ADD Vx, Vy
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0x5 => return Instruction{ .SUB = .{ .x = n2, .y = n3 } }, // 0x8xy5 | SUB Vx, Vy
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0x6 => return Instruction{ .SHR = .{ .x = n2, .y = n3 } }, // 0x8xy6 | SHR Vx, Vy
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0x7 => return Instruction{ .SUBN = .{ .x = n2, .y = n3 } }, // 0x8xy7 | SUBN Vx, Vy
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0xE => return Instruction{ .SHL = .{ .x = n2, .y = n3 } }, // 0x8xyE | SHL Vx, Vy
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else => panic("0x{X:} is an unknown 0x8-prefixed opcode", .{opcode}),
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},
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0x9 => Instruction{ .SNE_Vx_Vy = .{ .x = n2, .y = n3 } }, // 0x9xy0 | SNE Vx, Vy
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0xA => Instruction{ .LD_I = util.calc12bit(n2, n3, n4) }, // 0xAnnn | LD I, u12
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0xB => Instruction{ .JP_V0 = util.calc12bit(n2, n3, n4) }, // 0xBnnn | JP V0, u12
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0xC => Instruction{ .RND = .{ .x = n2, .kk = util.calc8bit(n3, n4) } }, // 0xCxkk | RND Vx, u8
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0xD => Instruction{ .DRW = .{ .x = n2, .y = n3, .n = n4 } }, // 0xDxyn | DRW Vx, Vy, u4
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0xE => switch (n3) {
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0x9 => return Instruction{ .SKP = n2 }, // 0xEx9E | SKP Vx
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0xA => return Instruction{ .SKNP = n2 }, // 0xExA1 | SKNP Vx
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else => panic("0x{X:} is an unknown 0xE-prefixed opcode", .{opcode}),
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},
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0xF => switch (n3) {
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0x0 => switch (n4) {
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0x7 => return Instruction{ .LD_Vx_DT = n2 }, // 0xFx07 | LD Vx, DT
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0xA => return Instruction{ .LD_Vx_K = n2 }, // 0xFx0A | LD Vx, K
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else => panic("0x{X:} is an unknown 0xFx0-prefixed opcode", .{opcode}),
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},
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0x1 => switch (n4) {
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0x5 => return Instruction{ .LD_DT_Vx = n2 }, // 0xFx15 | LD DT, Vx
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0x8 => return Instruction{ .LD_ST_Vx = n2 }, // 0xFx18 | LD ST, Vx
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0xE => return Instruction{ .ADD_I_Vx = n2 }, // 0xFx1E | ADD I, Vx
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else => panic("0x{X:} is an unknown 0xFx1-prefixed opcode", .{opcode}),
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},
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0x2 => return Instruction{ .LD_F_Vx = n2 }, // 0xFx29 | LD F, Vx
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0x3 => return Instruction{ .LD_B_Vx = n2 }, // 0xFx33 | LD B, Vx
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0x5 => return Instruction{ .LD_IPTR_Vx = n2 }, // 0xFx55 | LD [I], Vx
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0x6 => return Instruction{ .LD_Vx_IPTR = n2 }, // 0xFx64 | LD Vx, [I]
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else => panic("0x{X:} is an unknown 0xFx-prefixed opcode", .{opcode}),
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},
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};
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}
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fn execute(cpu: *Cpu, display: *Display, mem: *[0x1000]u8, instr: Instruction) void {
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const scheduler = cpu.scheduler;
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switch (instr) {
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.CLS => {
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display.buf = [_]u8{0x00} ** (disp.WIDTH * disp.HEIGHT);
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scheduler.push(EventKind.RequestRedraw, scheduler.now());
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},
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.RET => {
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cpu.pc = cpu.stack[cpu.sp];
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cpu.sp -= 1;
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},
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.JP => |addr| {
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cpu.pc = addr;
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},
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.CALL => |addr| {
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cpu.sp += 1;
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cpu.stack[cpu.sp] = cpu.pc;
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cpu.pc = addr;
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},
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.SE_Vx => |args| {
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if (cpu.v[args.x] == args.kk) {
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cpu.pc += 2;
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}
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},
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.SNE_Vx => |args| {
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if (cpu.v[args.x] != args.kk) {
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cpu.pc += 2;
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}
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},
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.SE_Vx_Vy => |args| {
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if (cpu.v[args.x] == cpu.v[args.y]) {
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cpu.pc += 2;
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}
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},
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.LD_Vx => |args| {
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cpu.v[args.x] = args.kk;
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},
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.ADD_Vx => |args| {
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cpu.v[args.x] +%= args.kk;
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},
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.LD_Vx_Vy => |args| {
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cpu.v[args.x] = cpu.v[args.y];
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},
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.OR => |args| {
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cpu.v[args.x] |= cpu.v[args.y];
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},
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.AND => |args| {
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cpu.v[args.x] &= cpu.v[args.y];
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},
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.XOR => |args| {
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cpu.v[args.x] ^= cpu.v[args.y];
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},
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.ADD_Vx_Vy => |args| {
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const did_overflow = @addWithOverflow(u8, cpu.v[args.x], cpu.v[args.y], &cpu.v[args.x]);
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cpu.v[0xF] = @boolToInt(did_overflow);
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},
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.SUB => |args| {
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cpu.v[0xF] = @boolToInt(cpu.v[args.x] > cpu.v[args.y]);
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cpu.v[args.x] -%= cpu.v[args.y];
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},
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.SHR => |args| {
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cpu.v[0xF] = @boolToInt((cpu.v[args.x] & 0x01) == 0x01);
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cpu.v[args.x] >>= 1;
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},
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.SUBN => |args| {
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cpu.v[0xF] = @boolToInt(cpu.v[args.y] > cpu.v[args.x]);
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cpu.v[args.x] = cpu.v[args.y] -% cpu.v[args.x];
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},
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.SHL => |args| {
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cpu.v[0xF] = @boolToInt(((cpu.v[args.x] >> 7) & 0x01) == 0x01);
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cpu.v[args.x] <<= 1;
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},
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.SNE_Vx_Vy => |args| {
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if (cpu.v[args.x] != cpu.v[args.y]) {
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cpu.pc += 2;
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}
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},
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.LD_I => |addr| {
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cpu.i = addr;
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},
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.JP_V0 => |addr| {
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cpu.pc = addr + cpu.v[0];
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},
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.RND => |args| {
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cpu.v[args.x] = prng.random.int(u8) & args.kk;
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},
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.DRW => |args| {
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const x = args.x;
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const y = args.y;
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const n = args.n;
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const draw_pos = Point{ .x = cpu.v[x], .y = cpu.v[y] };
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const sprite_data = mem[cpu.i..(cpu.i + n)];
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// Draw Sprite
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const collision = disp.drawSprite(display, &draw_pos, &sprite_data);
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cpu.v[0xF] = @boolToInt(collision);
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scheduler.push(EventKind.RequestRedraw, scheduler.now());
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},
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.SKP => |x| {
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std.log.debug("TODO: SKP V{}", .{x});
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},
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.SKNP => |x| {
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std.log.debug("TODO: SKNP V{}", .{x});
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},
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.LD_Vx_DT => |x| {
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if (scheduler.find(EventKind.DelayTimer)) |e| {
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const num = (e.timestamp - scheduler.now()) / OPS_PER_HZ;
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cpu.v[x] = @intCast(u8, num);
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} else {
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cpu.v[x] = 0;
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}
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},
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.LD_Vx_K => |x| {
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std.log.debug("TODO: LD V{}, K", .{x});
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},
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.LD_DT_Vx => |x| {
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const when = scheduler.now() + OPS_PER_HZ * @as(u64, cpu.v[x]);
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scheduler.ReplaceOrPush(EventKind.DelayTimer, when);
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},
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.LD_ST_Vx => |x| {
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const when = scheduler.now() + OPS_PER_HZ * @as(u64, cpu.v[x]);
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scheduler.ReplaceOrPush(EventKind.SoundTimer, when);
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},
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.ADD_I_Vx => |x| {
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const sum: u16 = cpu.i + cpu.v[x];
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cpu.v[0xF] = @boolToInt(sum >= 0x1000);
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cpu.i = sum & 0x0FFF;
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},
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.LD_F_Vx => |x| {
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cpu.i = 0x50 + (5 * cpu.v[x]);
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},
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.LD_B_Vx => |x| {
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var value = cpu.v[x];
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mem[cpu.i] = value / 100;
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mem[cpu.i + 1] = (value / 10) % 10;
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mem[cpu.i + 2] = value % 10;
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},
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.LD_IPTR_Vx => |x| {
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const upper = x + 1;
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std.mem.copy(u8, mem[(cpu.i)..(cpu.i + upper)], cpu.v[0..upper]);
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},
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.LD_Vx_IPTR => |x| {
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const upper = x + 1;
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std.mem.copy(u8, cpu.v[0..upper], mem[cpu.i..(cpu.i + upper)]);
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},
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}
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}
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