Rekai Musuka
e32d6534c6
some basic ROMs already boot (ARM946E-S only), working on Armwrestler and Rockwrestler next so I can ensure CPU compatability for but ARMv5TE and ARMv4T
101 lines
3.1 KiB
Zig
101 lines
3.1 KiB
Zig
const std = @import("std");
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const io = @import("io.zig");
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const Scheduler = @import("Scheduler.zig");
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const SharedIo = @import("../io.zig").Io;
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const Allocator = std.mem.Allocator;
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const Mode = enum { normal, debug };
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const MiB = 0x100000;
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const KiB = 0x400;
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const log = std.log.scoped(.nds7_bus);
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scheduler: *Scheduler,
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main: *[4 * MiB]u8,
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wram: *[64 * KiB]u8,
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io: io.Io,
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pub fn init(allocator: Allocator, scheduler: *Scheduler, shared_io: *SharedIo) !@This() {
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const main_mem = try allocator.create([4 * MiB]u8);
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errdefer allocator.destroy(main_mem);
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@memset(main_mem, 0);
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const wram = try allocator.create([64 * KiB]u8);
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errdefer allocator.destroy(wram);
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@memset(wram, 0);
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return .{
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.main = main_mem,
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.wram = wram,
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.scheduler = scheduler,
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.io = io.Io.init(shared_io),
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};
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}
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pub fn deinit(self: *@This(), allocator: Allocator) void {
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allocator.destroy(self.main);
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allocator.destroy(self.wram);
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}
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pub fn reset(_: *@This()) void {}
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pub fn read(self: *@This(), comptime T: type, address: u32) T {
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return self._read(T, .normal, address);
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}
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pub fn dbgRead(self: *@This(), comptime T: type, address: u32) T {
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return self._read(T, .debug, address);
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}
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fn _read(self: *@This(), comptime T: type, comptime mode: Mode, address: u32) T {
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const byte_count = @divExact(@typeInfo(T).Int.bits, 8);
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const readInt = std.mem.readIntLittle;
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switch (mode) {
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// .debug => log.debug("read {} from 0x{X:0>8}", .{ T, address }),
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.debug => {},
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else => self.scheduler.tick += 1,
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}
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return switch (address) {
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0x0200_0000...0x02FF_FFFF => readInt(T, self.main[address & 0x003F_FFFF ..][0..byte_count]),
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0x0380_0000...0x0380_FFFF => readInt(T, self.wram[address & 0x0000_FFFF ..][0..byte_count]),
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0x0400_0000...0x04FF_FFFF => io.read(self, T, address),
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else => warn("unexpected read: 0x{x:0>8} -> {}", .{ address, T }),
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};
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}
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pub fn write(self: *@This(), comptime T: type, address: u32, value: T) void {
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return self._write(T, .normal, address, value);
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}
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pub fn dbgWrite(self: *@This(), comptime T: type, address: u32, value: T) void {
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return self._write(T, .debug, address, value);
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}
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fn _write(self: *@This(), comptime T: type, comptime mode: Mode, address: u32, value: T) void {
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const byte_count = @divExact(@typeInfo(T).Int.bits, 8);
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const writeInt = std.mem.writeIntLittle;
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switch (mode) {
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// .debug => log.debug("wrote 0x{X:}{} to 0x{X:0>8}", .{ value, T, address }),
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.debug => {},
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else => self.scheduler.tick += 1,
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}
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switch (address) {
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0x0200_0000...0x02FF_FFFF => writeInt(T, self.main[address & 0x003F_FFFF ..][0..byte_count], value),
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0x0380_0000...0x0380_FFFF => writeInt(T, self.wram[address & 0x0000_FFFF ..][0..byte_count], value),
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0x0400_0000...0x04FF_FFFF => io.write(self, T, address, value),
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else => log.warn("unexpected write: 0x{X:}{} -> 0x{X:0>8}", .{ value, T, address }),
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}
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}
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fn warn(comptime format: []const u8, args: anytype) u0 {
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log.warn(format, args);
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return 0;
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}
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