437 lines
14 KiB
Zig
437 lines
14 KiB
Zig
const std = @import("std");
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const Bitfield = @import("bitfield").Bitfield;
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const Bit = @import("bitfield").Bit;
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const System = @import("emu.zig").System;
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const handleInterrupt = @import("emu.zig").handleInterrupt;
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const log = std.log.scoped(.shared_io);
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pub const Io = struct {
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/// Inter Process Communication FIFO
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ipc: Ipc = .{},
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wramcnt: WramCnt = .{ .raw = 0x00 },
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// Read Only
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keyinput: AtomicKeyInput = .{},
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};
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fn warn(comptime format: []const u8, args: anytype) u0 {
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log.warn(format, args);
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return 0;
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}
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/// Inter-Process Communication
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const Ipc = struct {
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const Sync = IpcSync;
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const Control = IpcFifoCnt;
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_nds7: Impl = .{},
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_nds9: Impl = .{},
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// we need access to the CPUs to handle IPC IRQs
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arm7tdmi: ?*System.Arm7tdmi = null,
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arm946es: ?*System.Arm946es = null,
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// TODO: DS Cartridge I/O Ports
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const Impl = struct {
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/// IPC Synchronize
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/// Read/Write
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sync: Sync = .{ .raw = 0x0000_0000 },
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/// IPC Fifo Control
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/// Read/Write
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cnt: Control = .{ .raw = 0x0000_0101 },
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fifo: Fifo = Fifo{},
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/// Latch containing thel last read value from a FIFO
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last_read: ?u32 = null,
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};
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pub fn configure(self: *@This(), system: System) void {
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self.arm7tdmi = system.arm7tdmi;
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self.arm946es = system.arm946es;
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}
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/// IPCSYNC
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/// Read/Write
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pub fn setIpcSync(self: *@This(), comptime proc: System.Process, value: anytype) void {
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switch (proc) {
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.nds7 => {
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self._nds7.sync.raw = masks.ipcFifoSync(self._nds7.sync.raw, value);
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self._nds9.sync.raw = masks.mask(self._nds9.sync.raw, (self._nds7.sync.raw >> 8) & 0xF, 0xF);
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if (value >> 13 & 1 == 1 and self._nds9.sync.recv_irq.read()) {
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const bus: *System.Bus9 = @ptrCast(@alignCast(self.arm946es.?.bus.ptr));
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bus.io.irq.ipcsync.set();
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handleInterrupt(.nds9, self.arm946es.?);
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}
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if (value >> 3 & 1 == 1) {
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self._nds7.fifo.reset();
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self._nds7.cnt.send_fifo_empty.set();
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self._nds9.cnt.recv_fifo_empty.set();
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self._nds7.cnt.send_fifo_full.unset();
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self._nds9.cnt.recv_fifo_full.unset();
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}
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},
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.nds9 => {
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self._nds9.sync.raw = masks.ipcFifoSync(self._nds9.sync.raw, value);
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self._nds7.sync.raw = masks.mask(self._nds7.sync.raw, (self._nds9.sync.raw >> 8) & 0xF, 0xF);
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if (value >> 13 & 1 == 1 and self._nds7.sync.recv_irq.read()) {
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const bus: *System.Bus7 = @ptrCast(@alignCast(self.arm7tdmi.?.bus.ptr));
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bus.io.irq.ipcsync.set();
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handleInterrupt(.nds7, self.arm7tdmi.?);
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}
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if (value >> 3 & 1 == 1) {
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self._nds9.fifo.reset();
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self._nds9.cnt.send_fifo_empty.set();
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self._nds7.cnt.recv_fifo_empty.set();
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self._nds9.cnt.send_fifo_full.unset();
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self._nds7.cnt.recv_fifo_full.unset();
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}
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},
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}
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}
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/// IPCFIFOCNT
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/// Read/Write
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pub fn setIpcFifoCnt(self: *@This(), comptime proc: System.Process, value: anytype) void {
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switch (proc) {
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.nds7 => self._nds7.cnt.raw = masks.ipcFifoCnt(self._nds7.cnt.raw, value),
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.nds9 => self._nds9.cnt.raw = masks.ipcFifoCnt(self._nds9.cnt.raw, value),
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}
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}
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/// IPC Send FIFO
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/// Write-Only
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pub fn send(self: *@This(), comptime proc: System.Process, value: u32) void {
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switch (proc) {
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.nds7 => {
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if (!self._nds7.cnt.enable_fifos.read()) return;
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self._nds7.fifo.push(value) catch unreachable; // see early return above
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const not_empty_cache = !self._nds9.cnt.recv_fifo_empty.read();
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// update status bits
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self._nds7.cnt.send_fifo_empty.write(self._nds7.fifo._len() == 0);
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self._nds9.cnt.recv_fifo_empty.write(self._nds7.fifo._len() == 0);
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self._nds7.cnt.send_fifo_full.write(self._nds7.fifo._len() == 0x10);
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self._nds9.cnt.recv_fifo_full.write(self._nds7.fifo._len() == 0x10);
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const not_empty = !self._nds9.cnt.recv_fifo_empty.read();
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if (self._nds9.cnt.recv_fifo_irq_enable.read() and !not_empty_cache and not_empty) {
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// NDS7 Send | NDS9 RECV (Handling Not Empty)
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const bus: *System.Bus9 = @ptrCast(@alignCast(self.arm946es.?.bus.ptr));
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bus.io.irq.ipc_recv_not_empty.set();
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handleInterrupt(.nds9, self.arm946es.?);
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}
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},
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.nds9 => {
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if (!self._nds9.cnt.enable_fifos.read()) return;
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self._nds9.fifo.push(value) catch unreachable; // see early return above
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const not_empty_cache = !self._nds7.cnt.recv_fifo_empty.read();
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// update status bits
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self._nds9.cnt.send_fifo_empty.write(self._nds9.fifo._len() == 0);
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self._nds7.cnt.recv_fifo_empty.write(self._nds9.fifo._len() == 0);
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self._nds9.cnt.send_fifo_full.write(self._nds9.fifo._len() == 0x10);
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self._nds7.cnt.recv_fifo_full.write(self._nds9.fifo._len() == 0x10);
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const not_empty = !self._nds7.cnt.recv_fifo_empty.read();
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if (self._nds7.cnt.recv_fifo_irq_enable.read() and !not_empty_cache and not_empty) {
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// NDS9 Send | NDS7 RECV (Handling Not Empty)
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const bus: *System.Bus7 = @ptrCast(@alignCast(self.arm7tdmi.?.bus.ptr));
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bus.io.irq.ipc_recv_not_empty.set();
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handleInterrupt(.nds7, self.arm7tdmi.?);
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}
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},
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}
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}
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/// IPC Receive FIFO
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/// Read-Only
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pub fn recv(self: *@This(), comptime proc: System.Process) u32 {
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switch (proc) {
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.nds7 => {
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const enabled = self._nds7.cnt.enable_fifos.read();
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const val_opt = if (enabled) self._nds9.fifo.pop() else self._nds9.fifo.peek();
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const value = if (val_opt) |val| blk: {
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self._nds9.last_read = val;
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break :blk val;
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} else blk: {
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self._nds7.cnt.fifo_error.set();
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break :blk self._nds7.last_read orelse 0x0000_0000;
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};
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const empty_cache = self._nds9.cnt.send_fifo_empty.read();
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// update status bits
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self._nds7.cnt.recv_fifo_empty.write(self._nds9.fifo._len() == 0);
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self._nds9.cnt.send_fifo_empty.write(self._nds9.fifo._len() == 0);
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self._nds7.cnt.recv_fifo_full.write(self._nds9.fifo._len() == 0x10);
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self._nds9.cnt.send_fifo_full.write(self._nds9.fifo._len() == 0x10);
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const empty = self._nds9.cnt.send_fifo_empty.read();
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if (self._nds9.cnt.send_fifo_irq_enable.read() and (!empty_cache and empty)) {
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const bus: *System.Bus9 = @ptrCast(@alignCast(self.arm946es.?.bus.ptr));
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bus.io.irq.ipc_send_empty.set();
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handleInterrupt(.nds9, self.arm946es.?);
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}
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return value;
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},
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.nds9 => {
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const enabled = self._nds9.cnt.enable_fifos.read();
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const val_opt = if (enabled) self._nds7.fifo.pop() else self._nds7.fifo.peek();
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const value = if (val_opt) |val| blk: {
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self._nds7.last_read = val;
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break :blk val;
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} else blk: {
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self._nds9.cnt.fifo_error.set();
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break :blk self._nds7.last_read orelse 0x0000_0000;
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};
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const empty_cache = self._nds7.cnt.send_fifo_empty.read();
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// update status bits
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self._nds9.cnt.recv_fifo_empty.write(self._nds7.fifo._len() == 0);
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self._nds7.cnt.send_fifo_empty.write(self._nds7.fifo._len() == 0);
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self._nds9.cnt.recv_fifo_full.write(self._nds7.fifo._len() == 0x10);
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self._nds7.cnt.send_fifo_full.write(self._nds7.fifo._len() == 0x10);
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const empty = self._nds7.cnt.send_fifo_empty.read();
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if (self._nds7.cnt.send_fifo_irq_enable.read() and (!empty_cache and empty)) {
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const bus: *System.Bus7 = @ptrCast(@alignCast(self.arm7tdmi.?.bus.ptr));
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bus.io.irq.ipc_send_empty.set();
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handleInterrupt(.nds7, self.arm7tdmi.?);
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}
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return value;
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},
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}
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}
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};
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const IpcSync = extern union {
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/// Data input to IPCSYNC Bit 8->11 of remote CPU
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/// Read-Only
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data_input: Bitfield(u32, 0, 4),
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/// Data output to IPCSYNC Bit 0->3 of remote CPU
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/// Read/Write
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data_output: Bitfield(u32, 8, 4),
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/// Send IRQ to remote CPU
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/// Write-Only
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send_irq: Bit(u32, 13),
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/// Enable IRQ from remote CPU
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/// Read/Write
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recv_irq: Bit(u32, 14),
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raw: u32,
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};
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const IpcFifoCnt = extern union {
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/// Read-Only
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send_fifo_empty: Bit(u32, 0),
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/// Read-Only
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send_fifo_full: Bit(u32, 1),
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/// Read/Write
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send_fifo_irq_enable: Bit(u32, 2),
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/// Write-Only
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send_fifo_clear: Bit(u32, 3),
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/// Read-Only
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recv_fifo_empty: Bit(u32, 8),
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/// Read-Only
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recv_fifo_full: Bit(u32, 9),
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/// IRQ for when the Receive FIFO is **not empty**
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/// Read/Write
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recv_fifo_irq_enable: Bit(u32, 10),
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/// Error, recv FIFO empty or send FIFO full
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/// Read/Write
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fifo_error: Bit(u32, 14),
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/// Read/Write
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enable_fifos: Bit(u32, 15),
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raw: u32,
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};
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pub const WramCnt = extern union {
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mode: Bitfield(u8, 0, 2),
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raw: u8,
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};
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pub const masks = struct {
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const Bus9 = @import("nds9/Bus.zig");
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const Bus7 = @import("nds7/Bus.zig");
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inline fn ipcFifoSync(sync: u32, value: anytype) u32 {
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const _mask: u32 = 0x6F00;
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return (@as(u32, value) & _mask) | (sync & ~_mask);
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}
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inline fn ipcFifoCnt(cnt: u32, value: anytype) u32 {
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const _mask: u32 = 0xC40C;
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const err_mask: u32 = 0x4000; // bit 14
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const err_bit = (cnt & err_mask) & ~(value & err_mask);
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const without_err = (@as(u32, value) & _mask) | (cnt & ~_mask);
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return (without_err & ~err_mask) | err_bit;
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}
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/// General Mask helper
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pub inline fn mask(original: anytype, value: @TypeOf(original), _mask: @TypeOf(original)) @TypeOf(original) {
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return (value & _mask) | (original & ~_mask);
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}
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};
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// FIXME: bitfields depends on NDS9 / NDS7
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pub const IntEnable = extern union {
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vblank: Bit(u32, 0),
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hblank: Bit(u32, 1),
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coincidence: Bit(u32, 2),
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dma0: Bit(u32, 8),
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dma1: Bit(u32, 9),
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dma2: Bit(u32, 10),
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dma3: Bit(u32, 11),
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ipcsync: Bit(u32, 16),
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ipc_send_empty: Bit(u32, 17),
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ipc_recv_not_empty: Bit(u32, 18),
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raw: u32,
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};
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const Fifo = struct {
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const Index = u8;
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const Error = error{full};
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const len = 0x10;
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read_idx: Index = 0,
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write_idx: Index = 0,
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buf: [len]u32 = [_]u32{undefined} ** len,
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comptime {
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const max_capacity = (@as(Index, 1) << @typeInfo(Index).Int.bits - 1) - 1; // half the range of index type
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std.debug.assert(std.math.isPowerOfTwo(len));
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std.debug.assert(len <= max_capacity);
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}
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pub fn reset(self: *@This()) void {
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self.read_idx = 0;
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self.write_idx = 0;
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}
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pub fn push(self: *@This(), value: u32) Error!void {
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if (self.isFull()) return Error.full;
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defer self.write_idx += 1;
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self.buf[self.mask(self.write_idx)] = value;
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}
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pub fn pop(self: *@This()) ?u32 {
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if (self.isEmpty()) return null;
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defer self.read_idx += 1;
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return self.buf[self.mask(self.read_idx)];
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}
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pub fn peek(self: *const @This()) ?u32 {
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if (self.isEmpty()) return null;
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return self.buf[self.mask(self.read_idx)];
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}
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fn _len(self: *const @This()) Index {
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return self.write_idx - self.read_idx;
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}
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fn isFull(self: *const @This()) bool {
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return self._len() == self.buf.len;
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}
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fn isEmpty(self: *const @This()) bool {
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return self.read_idx == self.write_idx;
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}
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inline fn mask(self: *const @This(), idx: Index) Index {
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const _mask: Index = @intCast(self.buf.len - 1);
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return idx & _mask;
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}
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};
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/// Read Only
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/// 0 = Pressed, 1 = Released
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pub const KeyInput = extern union {
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a: Bit(u16, 0),
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b: Bit(u16, 1),
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select: Bit(u16, 2),
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start: Bit(u16, 3),
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right: Bit(u16, 4),
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left: Bit(u16, 5),
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up: Bit(u16, 6),
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down: Bit(u16, 7),
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shoulder_r: Bit(u16, 8),
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shoulder_l: Bit(u16, 9),
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raw: u16,
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};
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const AtomicKeyInput = struct {
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const Self = @This();
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const Ordering = std.atomic.Ordering;
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inner: KeyInput = .{ .raw = 0x03FF },
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pub inline fn load(self: *const Self, comptime ordering: Ordering) u16 {
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return switch (ordering) {
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.AcqRel, .Release => @compileError("not supported for atomic loads"),
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else => @atomicLoad(u16, &self.inner.raw, ordering),
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};
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}
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pub inline fn fetchOr(self: *Self, value: u16, comptime ordering: Ordering) void {
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_ = @atomicRmw(u16, &self.inner.raw, .Or, value, ordering);
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}
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pub inline fn fetchAnd(self: *Self, value: u16, comptime ordering: Ordering) void {
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_ = @atomicRmw(u16, &self.inner.raw, .And, value, ordering);
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}
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};
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