Rekai Musuka
e32d6534c6
some basic ROMs already boot (ARM946E-S only), working on Armwrestler and Rockwrestler next so I can ensure CPU compatability for but ARMv5TE and ARMv4T
218 lines
6.9 KiB
Zig
218 lines
6.9 KiB
Zig
const std = @import("std");
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const Bitfield = @import("bitfield").Bitfield;
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const Bit = @import("bitfield").Bit;
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const Bus = @import("Bus.zig");
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const SharedIo = @import("../io.zig").Io;
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const writeToAddressOffset = @import("../io.zig").writeToAddressOffset;
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const valueAtAddressOffset = @import("../io.zig").valueAtAddressOffset;
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const log = std.log.scoped(.nds9_io);
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pub const Io = struct {
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shared: *SharedIo,
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/// POWCNT1 - Graphics Power Control
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/// Read / Write
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powcnt: PowCnt = .{ .raw = 0x0000_0000 },
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// Read Only
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keyinput: AtomicKeyInput = .{},
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pub fn init(io: *SharedIo) @This() {
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return .{ .shared = io };
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}
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};
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pub fn read(bus: *const Bus, comptime T: type, address: u32) T {
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return switch (T) {
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// zig fmt: off
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u32 =>
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@as(T, read(bus, u8, address + 3)) << 24
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| @as(T, read(bus, u8, address + 2)) << 16
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| @as(T, read(bus, u8, address + 1)) << 8
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| read(bus, u8, address + 0) << 0,
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// zig fmt: on
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u16 => @as(T, read(bus, u8, address + 1)) << 8 | read(bus, u8, address),
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u8 => switch (address) {
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0x0400_0000...0x0400_0003 => valueAtAddressOffset(u32, address, bus.ppu.io.dispcnt_a.raw),
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0x0400_0004...0x0400_0005 => valueAtAddressOffset(u16, address, bus.ppu.io.dispstat.raw),
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0x0400_0130...0x0400_0131 => valueAtAddressOffset(u16, address, bus.io.keyinput.load(.Monotonic)),
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0x0400_0180...0x0400_0183 => valueAtAddressOffset(u32, address, bus.io.shared.ipc_sync.raw),
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0x0400_0184...0x0400_0187 => valueAtAddressOffset(u32, address, bus.io.shared.ipc_fifo_cnt.raw),
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0x0400_0208...0x0400_020B => valueAtAddressOffset(u32, address, @intFromBool(bus.io.shared.ime)),
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0x0400_0304...0x0400_0307 => valueAtAddressOffset(u32, address, bus.io.powcnt.raw),
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else => warn("unexpected read: 0x{X:0>8}", .{address}),
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},
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else => @compileError(T ++ " is an unsupported bus read type"),
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};
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}
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pub fn write(bus: *Bus, comptime T: type, address: u32, value: T) void {
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switch (T) {
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u32 => {
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write(bus, u8, address + 3, @as(u8, @truncate(value >> 24)));
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write(bus, u8, address + 2, @as(u8, @truncate(value >> 16)));
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write(bus, u8, address + 1, @as(u8, @truncate(value >> 8)));
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write(bus, u8, address + 0, @as(u8, @truncate(value >> 0)));
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},
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u16 => {
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write(bus, u8, address + 1, @as(u8, @truncate(value >> 8)));
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write(bus, u8, address + 0, @as(u8, @truncate(value >> 0)));
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},
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u8 => switch (address) {
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0x0400_0000...0x0400_0003 => writeToAddressOffset(&bus.ppu.io.dispcnt_a.raw, address, value),
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0x0400_0180...0x0400_0183 => writeToAddressOffset(&bus.io.shared.ipc_sync.raw, address, value),
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0x0400_0184...0x0400_0187 => writeToAddressOffset(&bus.io.shared.ipc_fifo_cnt.raw, address, value),
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0x0400_0208 => bus.io.shared.ime = value & 1 == 1,
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0x0400_0209...0x0400_020B => {}, // unused bytes from IME
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0x0400_0240 => bus.ppu.io.vramcnt_a.raw = value,
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0x0400_0241 => bus.ppu.io.vramcnt_b.raw = value,
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0x0400_0242 => bus.ppu.io.vramcnt_c.raw = value,
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0x0400_0243 => bus.ppu.io.vramcnt_d.raw = value,
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0x0400_0304...0x0400_0307 => writeToAddressOffset(&bus.io.powcnt.raw, address, value),
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else => log.warn("unexpected write: 0x{X:}u8 -> 0x{X:0>8}", .{ value, address }),
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},
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else => @compileError(T ++ " is an unsupported bus write type"),
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}
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}
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fn warn(comptime format: []const u8, args: anytype) u0 {
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log.warn(format, args);
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return 0;
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}
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const PowCnt = extern union {
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// Enable flag for both LCDs
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lcd: Bit(u32, 0),
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gfx_2da: Bit(u32, 1),
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render_3d: Bit(u32, 2),
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geometry_3d: Bit(u32, 3),
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gfx_2db: Bit(u32, 9),
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display_swap: Bit(u32, 15),
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raw: u32,
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};
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pub const DispcntA = extern union {
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bg_mode: Bitfield(u32, 0, 2),
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/// toggle between 2D and 3D for BG0
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bg0_dimension: Bit(u32, 3),
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tile_obj_mapping: Bit(u32, 4),
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bitmap_obj_2d_dimension: Bit(u32, 5),
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bitmap_obj_mapping: Bit(u32, 6),
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forced_blank: Bit(u32, 7),
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bg_enable: Bitfield(u32, 8, 4),
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obj_enable: Bit(u32, 12),
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win_enable: Bitfield(u32, 13, 2),
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obj_win_enable: Bit(u32, 15),
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display_mode: Bitfield(u32, 16, 2),
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vram_block: Bitfield(u32, 18, 2),
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tile_obj_1d_boundary: Bitfield(u32, 20, 2),
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bitmap_obj_1d_boundary: Bit(u32, 22),
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obj_during_hblank: Bit(u32, 23),
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character_base: Bitfield(u32, 24, 3),
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screen_base: Bitfield(u32, 27, 2),
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bg_ext_pal_enable: Bit(u32, 30),
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obj_ext_pal_enable: Bit(u32, 31),
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raw: u32,
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};
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pub const Vramcnt = struct {
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/// Can be used by VRAM-A and VRAM-B
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pub const A = extern union {
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mst: Bitfield(u8, 0, 2),
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offset: Bitfield(u8, 3, 2),
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enable: Bit(u8, 7),
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raw: u8,
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};
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/// Can be used by VRAM-C, VRAM-D, VRAM-F, VRAM-G
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pub const C = extern union {
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mst: Bitfield(u8, 0, 3),
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offset: Bitfield(u8, 3, 2),
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enable: Bit(u8, 7),
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raw: u8,
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};
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/// Can be used by VRAM-E
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pub const E = extern union {
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mst: Bitfield(u8, 0, 3),
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enable: Bit(u8, 7),
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raw: u8,
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};
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/// can be used by VRAM-H and VRAM-I
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pub const H = extern union {
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mst: Bitfield(u8, 0, 2),
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enable: Bit(u8, 7),
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raw: u8,
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};
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};
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// Compared to the GBA:
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// - LY/LYC values are now 9-bits
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pub const Vcount = extern union {
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scanline: Bitfield(u16, 0, 9),
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raw: u16,
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};
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pub const Dispstat = extern union {
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vblank: Bit(u16, 0),
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hblank: Bit(u16, 1),
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coincidence: Bit(u16, 2),
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vblank_irq: Bit(u16, 3),
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hblank_irq: Bit(u16, 4),
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vcount_irq: Bit(u16, 5),
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/// FIXME: confirm that I'm reading DISPSTAT.7 correctly into LYC
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lyc: Bitfield(u16, 7, 9),
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raw: u16,
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};
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/// Read Only
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/// 0 = Pressed, 1 = Released
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pub const KeyInput = extern union {
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a: Bit(u16, 0),
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b: Bit(u16, 1),
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select: Bit(u16, 2),
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start: Bit(u16, 3),
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right: Bit(u16, 4),
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left: Bit(u16, 5),
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up: Bit(u16, 6),
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down: Bit(u16, 7),
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shoulder_r: Bit(u16, 8),
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shoulder_l: Bit(u16, 9),
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raw: u16,
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};
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const AtomicKeyInput = struct {
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const Self = @This();
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const Ordering = std.atomic.Ordering;
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inner: KeyInput = .{ .raw = 0x03FF },
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pub inline fn load(self: *const Self, comptime ordering: Ordering) u16 {
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return switch (ordering) {
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.AcqRel, .Release => @compileError("not supported for atomic loads"),
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else => @atomicLoad(u16, &self.inner.raw, ordering),
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};
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}
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pub inline fn fetchOr(self: *Self, value: u16, comptime ordering: Ordering) void {
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_ = @atomicRmw(u16, &self.inner.raw, .Or, value, ordering);
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}
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pub inline fn fetchAnd(self: *Self, value: u16, comptime ordering: Ordering) void {
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_ = @atomicRmw(u16, &self.inner.raw, .And, value, ordering);
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}
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};
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