121 lines
4.1 KiB
Zig
121 lines
4.1 KiB
Zig
const std = @import("std");
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const io = @import("io.zig");
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const Ppu = @import("../ppu.zig").Ppu;
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const Scheduler = @import("../Scheduler.zig");
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const SharedCtx = @import("../emu.zig").SharedCtx;
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const Wram = @import("../emu.zig").Wram;
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const Bios = @import("Bios.zig");
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const forceAlign = @import("../emu.zig").forceAlign;
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const Allocator = std.mem.Allocator;
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const Mode = enum { normal, debug };
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const MiB = 0x100000;
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const KiB = 0x400;
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const log = std.log.scoped(.nds9_bus);
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main: *[4 * MiB]u8,
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wram: *Wram,
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makeshift_palram: *[2 * KiB]u8,
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scheduler: *Scheduler,
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io: io.Io,
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ppu: Ppu,
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bios: Bios,
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pub fn init(allocator: Allocator, scheduler: *Scheduler, ctx: SharedCtx) !@This() {
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const dots_per_cycle = 3; // ARM946E-S runs twice as fast as the ARM7TDMI
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scheduler.push(.{ .nds9 = .draw }, 256 * dots_per_cycle);
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return .{
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.main = ctx.main,
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.wram = ctx.wram,
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.makeshift_palram = try allocator.create([2 * KiB]u8),
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.ppu = try Ppu.init(allocator, ctx.vram),
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.scheduler = scheduler,
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.io = io.Io.init(ctx.io),
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.bios = .{},
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};
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}
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pub fn deinit(self: *@This(), allocator: Allocator) void {
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self.ppu.deinit(allocator);
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self.bios.deinit(allocator);
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allocator.destroy(self.makeshift_palram);
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}
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pub fn reset(_: *@This()) void {
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@panic("TODO: PPU Reset");
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}
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pub fn read(self: *@This(), comptime T: type, address: u32) T {
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return self._read(T, .normal, address);
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}
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pub fn dbgRead(self: *@This(), comptime T: type, address: u32) T {
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return self._read(T, .debug, address);
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}
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fn _read(self: *@This(), comptime T: type, comptime mode: Mode, address: u32) T {
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const byte_count = @divExact(@typeInfo(T).Int.bits, 8);
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const readInt = std.mem.readIntLittle;
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const aligned_addr = forceAlign(T, address);
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switch (mode) {
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// .debug => log.debug("read {} from 0x{X:0>8}", .{ T, aligned_addr }),
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.debug => {},
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else => self.scheduler.tick += 1,
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}
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return switch (aligned_addr) {
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0x0200_0000...0x02FF_FFFF => readInt(T, self.main[aligned_addr & 0x003F_FFFF ..][0..byte_count]),
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0x0300_0000...0x03FF_FFFF => self.wram.read(T, .nds9, aligned_addr),
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0x0400_0000...0x04FF_FFFF => io.read(self, T, aligned_addr),
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0x0500_0000...0x05FF_FFFF => readInt(T, self.makeshift_palram[aligned_addr & (2 * KiB - 1) ..][0..@sizeOf(T)]),
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0x0600_0000...0x06FF_FFFF => self.ppu.vram.read(T, .nds9, aligned_addr),
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0xFFFF_0000...0xFFFF_FFFF => self.bios.read(T, address),
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else => warn("unexpected: read(T: {}, addr: 0x{X:0>8}) {} ", .{ T, address, T }),
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};
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}
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pub fn write(self: *@This(), comptime T: type, address: u32, value: T) void {
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return self._write(T, .normal, address, value);
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}
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pub fn dbgWrite(self: *@This(), comptime T: type, address: u32, value: T) void {
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return self._write(T, .debug, address, value);
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}
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fn _write(self: *@This(), comptime T: type, comptime mode: Mode, address: u32, value: T) void {
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const byte_count = @divExact(@typeInfo(T).Int.bits, 8);
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const writeInt = std.mem.writeIntLittle;
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const aligned_addr = forceAlign(T, address);
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switch (mode) {
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// .debug => log.debug("wrote 0x{X:}{} to 0x{X:0>8}", .{ value, T, aligned_addr }),
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.debug => {},
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else => self.scheduler.tick += 1,
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}
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switch (aligned_addr) {
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0x0200_0000...0x02FF_FFFF => writeInt(T, self.main[aligned_addr & 0x003F_FFFF ..][0..byte_count], value),
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0x0300_0000...0x03FF_FFFF => self.wram.write(T, .nds9, aligned_addr, value),
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0x0400_0000...0x04FF_FFFF => io.write(self, T, aligned_addr, value),
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0x0500_0000...0x05FF_FFFF => writeInt(T, self.makeshift_palram[aligned_addr & (2 * KiB - 1) ..][0..@sizeOf(T)], value),
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0x0600_0000...0x06FF_FFFF => self.ppu.vram.write(T, .nds9, aligned_addr, value),
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0xFFFF_0000...0xFFFF_FFFF => self.bios.write(T, address, value),
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else => log.warn("unexpected: write(T: {}, addr: 0x{X:0>8}, value: 0x{X:0>8})", .{ T, address, value }),
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}
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}
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fn warn(comptime format: []const u8, args: anytype) u0 {
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log.warn(format, args);
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return 0;
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}
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