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base: paoda:ac3927333b3ad3ce7e39bb66dcffb87a94d0e40d
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compare: paoda:1a56a1a285c8cd98a7782cbbb27c30930bbbcc63
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paoda:main
paoda:ppu

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5 changed files with 25 additions and 65 deletions
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5
src/core/nds7/Bus.zig
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@ -78,8 +78,7 @@ fn _read(self: *@This(), comptime T: type, comptime mode: Mode, address: u32) T
0x0380_0000...0x03FF_FFFF => readInt(T, self.wram[aligned_addr & 0x0000_FFFF ..][0..byte_count]), 0x0380_0000...0x03FF_FFFF => readInt(T, self.wram[aligned_addr & 0x0000_FFFF ..][0..byte_count]),
0x0400_0000...0x04FF_FFFF => io.read(self, T, aligned_addr), 0x0400_0000...0x04FF_FFFF => io.read(self, T, aligned_addr),
0x0600_0000...0x06FF_FFFF => self.vram.read(T, .nds7, aligned_addr), 0x0600_0000...0x06FF_FFFF => self.vram.read(T, .nds7, aligned_addr),
else => warn("unexpected read: 0x{x:0>8} -> {}", .{ aligned_addr, T }),
else => warn("unexpected: read(T: {}, addr: 0x{X:0>8}) {} ", .{ T, address, T }),
}; };
} }
@ -113,7 +112,7 @@ fn _write(self: *@This(), comptime T: type, comptime mode: Mode, address: u32, v
0x0380_0000...0x0380_FFFF => writeInt(T, self.wram[aligned_addr & 0x0000_FFFF ..][0..byte_count], value), 0x0380_0000...0x0380_FFFF => writeInt(T, self.wram[aligned_addr & 0x0000_FFFF ..][0..byte_count], value),
0x0400_0000...0x04FF_FFFF => io.write(self, T, aligned_addr, value), 0x0400_0000...0x04FF_FFFF => io.write(self, T, aligned_addr, value),
0x0600_0000...0x06FF_FFFF => self.vram.write(T, .nds7, aligned_addr, value), 0x0600_0000...0x06FF_FFFF => self.vram.write(T, .nds7, aligned_addr, value),
else => log.warn("unexpected: write(T: {}, addr: 0x{X:0>8}, value: 0x{X:0>8})", .{ T, address, value }), else => log.warn("unexpected write: 0x{X:}{} -> 0x{X:0>8}", .{ value, T, aligned_addr }),
} }
} }

4
src/core/nds7/io.zig
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@ -113,7 +113,7 @@ pub fn write(bus: *Bus, comptime T: type, address: u32, value: T) void {
0x0400_0180 => bus.io.shr.ipc.setIpcSync(.nds7, value), 0x0400_0180 => bus.io.shr.ipc.setIpcSync(.nds7, value),
0x0400_0184 => bus.io.shr.ipc.setIpcFifoCnt(.nds7, value), 0x0400_0184 => bus.io.shr.ipc.setIpcFifoCnt(.nds7, value),
else => log.warn("unexpected: write(T: {}, addr: 0x{X:0>8}, value: 0x{X:0>4})", .{ T, address, value }), else => log.warn("unexpected: write(T: {}, addr: 0x{X:0>8}, value: 0x{X:0>8})", .{ T, address, value }),
}, },
u8 => switch (address) { u8 => switch (address) {
// DMA Transfers // DMA Transfers
@ -123,7 +123,7 @@ pub fn write(bus: *Bus, comptime T: type, address: u32, value: T) void {
0x0400_0100...0x0400_010F => log.warn("TODO: Implement Timer", .{}), 0x0400_0100...0x0400_010F => log.warn("TODO: Implement Timer", .{}),
0x0400_0208 => bus.io.ime = value & 1 == 1, 0x0400_0208 => bus.io.ime = value & 1 == 1,
else => log.warn("unexpected: write(T: {}, addr: 0x{X:0>8}, value: 0x{X:0>2})", .{ T, address, value }), else => log.warn("unexpected: write(T: {}, addr: 0x{X:0>8}, value: 0x{X:0>8})", .{ T, address, value }),
}, },
else => @compileError(T ++ " is an unsupported bus write type"), else => @compileError(T ++ " is an unsupported bus write type"),
} }

4
src/core/nds9/Bus.zig
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@ -74,7 +74,7 @@ fn _read(self: *@This(), comptime T: type, comptime mode: Mode, address: u32) T
0x0400_0000...0x04FF_FFFF => io.read(self, T, aligned_addr), 0x0400_0000...0x04FF_FFFF => io.read(self, T, aligned_addr),
0x0600_0000...0x06FF_FFFF => self.ppu.vram.read(T, .nds9, aligned_addr), 0x0600_0000...0x06FF_FFFF => self.ppu.vram.read(T, .nds9, aligned_addr),
0xFFFF_0000...0xFFFF_FFFF => self.bios.read(T, address), 0xFFFF_0000...0xFFFF_FFFF => self.bios.read(T, address),
else => warn("unexpected: read(T: {}, addr: 0x{X:0>8}) {} ", .{ T, address, T }), else => warn("unexpected read: 0x{x:0>8} -> {}", .{ aligned_addr, T }),
}; };
} }
@ -104,7 +104,7 @@ fn _write(self: *@This(), comptime T: type, comptime mode: Mode, address: u32, v
0x0400_0000...0x04FF_FFFF => io.write(self, T, aligned_addr, value), 0x0400_0000...0x04FF_FFFF => io.write(self, T, aligned_addr, value),
0x0600_0000...0x06FF_FFFF => self.ppu.vram.write(T, .nds9, aligned_addr, value), 0x0600_0000...0x06FF_FFFF => self.ppu.vram.write(T, .nds9, aligned_addr, value),
0xFFFF_0000...0xFFFF_FFFF => self.bios.write(T, address, value), 0xFFFF_0000...0xFFFF_FFFF => self.bios.write(T, address, value),
else => log.warn("unexpected: write(T: {}, addr: 0x{X:0>8}, value: 0x{X:0>8})", .{ T, address, value }), else => log.warn("unexpected write: 0x{X:}{} -> 0x{X:0>8}", .{ value, T, aligned_addr }),
} }
} }

73
src/core/nds9/Cp15.zig
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@ -2,8 +2,6 @@ const std = @import("std");
const log = std.log.scoped(.cp15); const log = std.log.scoped(.cp15);
const panic_on_unimplemented: bool = true;
control: u32 = 0x0005_2078, control: u32 = 0x0005_2078,
dtcm_size_base: u32 = 0x0300_000A, dtcm_size_base: u32 = 0x0300_000A,
itcm_size_base: u32 = 0x0000_0020, itcm_size_base: u32 = 0x0000_0020,
@ -43,57 +41,22 @@ pub fn write(self: *@This(), op1: u3, cn: u4, cm: u4, op2: u3, value: u32) void
self.control = (value & ~zeroes) | ones; self.control = (value & ~zeroes) | ones;
}, },
0b000_0010_0000_000 => log.err("TODO: write to PU cachability bits (data/unified region)", .{}),
0b000_0010_0000_001 => log.err("TODO: write to PU cachability bits (instruction region)", .{}),
0b000_0011_0000_000 => log.err("TODO: write to PU cache write-bufferability bits (data protection region)", .{}),
0b000_0101_0000_000 => log.err("TODO: write to access permission protection region (data/unified)", .{}),
0b000_0101_0000_001 => log.err("TODO: write to access permission protection region (insruction)", .{}),
0b000_0101_0000_010 => log.err("TODO: write to extended access permission protection region (data/unified)", .{}),
0b000_0101_0000_011 => log.err("TODO: write to extended access permission protection region (insruction)", .{}),
0b000_0110_0000_000,
0b000_0110_0001_000,
0b000_0110_0010_000,
0b000_0110_0011_000,
0b000_0110_0100_000,
0b000_0110_0101_000,
0b000_0110_0110_000,
0b000_0110_0111_000,
=> log.err("TODO: write to PU data/unified region #{}", .{cm}),
0b000_0110_0000_001,
0b000_0110_0001_001,
0b000_0110_0010_001,
0b000_0110_0011_001,
0b000_0110_0100_001,
0b000_0110_0101_001,
0b000_0110_0110_001,
0b000_0110_0111_001,
=> log.err("TODO: write to PU instruction region #{}", .{cm}),
0b000_0111_0000_100 => log.err("TODO: halt ARM946E-S", .{}),
0b000_0111_0101_000 => log.err("TODO: invalidate instruction cache", .{}),
0b000_0111_0110_000 => log.err("TODO: invalidate data cache", .{}),
0b000_0111_1010_100 => log.err("TODO: drain write buffer", .{}),
0b000_1001_0001_000 => { // Data TCM Size / Base 0b000_1001_0001_000 => { // Data TCM Size / Base
const zeroes: u32 = 0b00000000_00000000_00001111_11000001; const zeroes: u32 = 0b00000000_00000000_00001111_11000001;
self.dtcm_size_base = value & ~zeroes; self.dtcm_size_base = value & ~zeroes;
// const size_shamt: u5 = blk: { const size_shamt: u5 = blk: {
// const size = self.dtcm_size_base >> 1 & 0x1F; const size = self.dtcm_size_base >> 1 & 0x1F;
// if (size < 3) break :blk 3; if (size < 3) break :blk 3;
// if (size > 23) break :blk 23; if (size > 23) break :blk 23;
// break :blk @intCast(size); break :blk @intCast(size);
// }; };
// log.debug("DTCM Virtual Size: {}B", .{@as(u32, 0x200) << size_shamt}); log.debug("DTCM Virtual Size: {}B", .{@as(u32, 0x200) << size_shamt});
// log.debug("DTCM Region Base: 0x{X:0>8}", .{self.dtcm_size_base & 0xFFFF_F000}); log.debug("DTCM Region Base: 0x{X:0>8}", .{self.dtcm_size_base & 0xFFFF_F000});
}, },
0b000_1001_0001_001 => { // Instruction TCM Size / Base 0b000_1001_0001_001 => { // Instruction TCM Size / Base
const zeroes: u32 = 0b00000000_00000000_00001111_11000001; const zeroes: u32 = 0b00000000_00000000_00001111_11000001;
@ -101,19 +64,18 @@ pub fn write(self: *@This(), op1: u3, cn: u4, cm: u4, op2: u3, value: u32) void
self.itcm_size_base = value & ~(zeroes | itcm_specific); self.itcm_size_base = value & ~(zeroes | itcm_specific);
// const size_shamt: u5 = blk: { const size_shamt: u5 = blk: {
// const size = self.dtcm_size_base >> 1 & 0x1F; const size = self.dtcm_size_base >> 1 & 0x1F;
// if (size < 3) break :blk 3; if (size < 3) break :blk 3;
// if (size > 23) break :blk 23; if (size > 23) break :blk 23;
// break :blk @intCast(size); break :blk @intCast(size);
// }; };
// log.debug("ICTM Virtual Size: {}B", .{@as(u32, 0x200) << size_shamt}); log.debug("ICTM Virtual Size: {}B", .{@as(u32, 0x200) << size_shamt});
// log.debug("ICTM Region Base: 0x{X:0>8}", .{0x0000_0000}); log.debug("ICTM Region Base: 0x{X:0>8}", .{0x0000_0000});
}, },
else => _ = panic("TODO: implement write to register {}, c{}, c{}, {}", .{ op1, cn, cm, op2 }), else => _ = panic("TODO: implement write to register {}, c{}, c{}, {}", .{ op1, cn, cm, op2 }),
} }
} }
@ -135,7 +97,6 @@ pub fn reset(self: *@This()) void {
fn panic(comptime format: []const u8, args: anytype) u32 { fn panic(comptime format: []const u8, args: anytype) u32 {
log.err(format, args); log.err(format, args);
if (panic_on_unimplemented) @panic("cp15 invariant broken"); // @panic("Coprocessor invariant broken");
return 0; return 0;
} }

4
src/core/nds9/io.zig
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@ -144,7 +144,7 @@ pub fn write(bus: *Bus, comptime T: type, address: u32, value: T) void {
0x0400_0304 => bus.io.powcnt.raw = value, 0x0400_0304 => bus.io.powcnt.raw = value,
else => log.warn("unexpected: write(T: {}, addr: 0x{X:0>8}, value: 0x{X:0>4})", .{ T, address, value }), else => log.warn("unexpected: write(T: {}, addr: 0x{X:0>8}, value: 0x{X:0>8})", .{ T, address, value }),
}, },
u8 => switch (address) { u8 => switch (address) {
0x0400_0240 => { 0x0400_0240 => {
@ -188,7 +188,7 @@ pub fn write(bus: *Bus, comptime T: type, address: u32, value: T) void {
bus.ppu.vram.update(); bus.ppu.vram.update();
}, },
else => log.warn("unexpected: write(T: {}, addr: 0x{X:0>8}, value: 0x{X:0>2})", .{ T, address, value }), else => log.warn("unexpected: write(T: {}, addr: 0x{X:0>8}, value: 0x{X:0>8})", .{ T, address, value }),
}, },
else => @compileError(T ++ " is an unsupported bus write type"), else => @compileError(T ++ " is an unsupported bus write type"),
} }