fix(ci): disable macOS builds

Windows CI should work again

.github/workflows/main.yml

@@ -4,7 +4,8 @@ on:
   push:
     paths:
       - "**.zig"
-      - "**.zig.zon"
+      - "dl_sdl2.ps1"
+      - "build.zig.zon"
     branches:
       - main
   schedule:
@@ -15,12 +16,17 @@ jobs:
   build:
     strategy:
       matrix:
-        os: [ubuntu-latest, windows-latest, macos-latest]
+        os: [ubuntu-latest, windows-latest] # TODO: Figure out Apple Silicon macOS
     runs-on: ${{matrix.os}}
     steps:
       - uses: goto-bus-stop/setup-zig@v2
         with:
-          version: 0.11.0
+          version: 0.13.0
+      - run: |
+            git config --global core.autocrlf false
+      - uses: actions/checkout@v3
+        with:
+          submodules: recursive
       - name: prepare-linux
         if: runner.os == 'Linux'
         run: |
@@ -29,26 +35,19 @@ jobs:
       - name: prepare-windows
         if: runner.os == 'Windows'
         run: |
-            vcpkg integrate install
-            vcpkg install sdl2:x64-windows
-            git config --global core.autocrlf false
+            .\dl_sdl2.ps1
       - name: prepare-macos
         if: runner.os == 'macOS'
         run: |
             brew install sdl2
-      - uses: actions/checkout@v3
-        with:
-          submodules: recursive
       - name: build 
         run: zig build -Doptimize=ReleaseSafe -Dcpu=baseline
-      - name: prepare-executable
-        run: |
-            mv zig-out/lib/* zig-out/bin
       - name: upload
         uses: actions/upload-artifact@v3
         with:
           name: zba-${{matrix.os}}
-          path: zig-out/bin
+          path: zig-out
+
   lint:
     runs-on: ubuntu-latest
     steps: 
@@ -57,6 +56,5 @@ jobs:
           submodules: recursive
       - uses: goto-bus-stop/setup-zig@v2
         with:
-          version: 0.11.0-dev.3395+1e7dcaa3a
-      - run: zig fmt src/**/*.zig
-  
+          version: 0.13.0
+      - run: zig fmt --check {src,lib}/**/*.zig build.zig build.zig.zon

.gitignore

@@ -1,5 +1,8 @@
-zig-cache/
+.zig-cache/
 zig-out/
 bin/
 doc/
-imgui.ini
+imgui.ini
+.build_config/
+
+**/*.log

.gitmodules

@@ -1,9 +1,3 @@
 [submodule "lib/SDL.zig"]
 	path = lib/SDL.zig
-	url = https://github.com/MasterQ32/SDL.zig
-[submodule "lib/zgui"]
-	path = lib/zgui
-	url = https://git.musuka.dev/paoda/zgui
-[submodule "lib/arm32"]
-	path = lib/arm32
-	url = https://git.musuka.dev/paoda/arm32.git
+	url = https://github.com/paoda/SDL.zig

build.zig

@@ -1,8 +1,5 @@
 const std = @import("std");
-
-const Sdk = @import("lib/SDL.zig/Sdk.zig");
-const zgui = @import("lib/zgui/build.zig");
-const arm32 = @import("lib/arm32/build.zig");
+const sdl = @import("lib/SDL.zig/build.zig");
 
 // Although this function looks imperative, note that its job is to
 // declaratively construct a build graph that will be executed by an external
@@ -23,26 +20,27 @@ pub fn build(b: *std.Build) void {
         .name = "turbo",
         // In this case the main source file is merely a path, however, in more
         // complicated build scripts, this could be a generated file.
-        .root_source_file = .{ .path = "src/main.zig" },
+        .root_source_file = b.path("src/main.zig"),
         .target = target,
         .optimize = optimize,
     });
 
-    exe.addModule("arm32", arm32.module(b));
-    exe.addModule("zig-clap", b.dependency("zig-clap", .{}).module("clap"));
+    const sdk = sdl.init(b, null, null);
+    const zgui = b.dependency("zgui", .{ .shared = false, .with_implot = true, .backend = .sdl2_opengl3 });
+    const imgui = zgui.artifact("imgui");
 
-    exe.addAnonymousModule("bitfield", .{ .source_file = .{ .path = "lib/bitfield.zig" } }); // https://github.com/FlorenceOS/
-    exe.addAnonymousModule("gl", .{ .source_file = .{ .path = "lib/gl.zig" } }); // https://github.com/MasterQ32/zig-opengl
+    exe.root_module.addImport("arm32", b.dependency("arm32", .{}).module("arm32")); // https://git.musuka.dev/paoda/arm32
+    exe.root_module.addImport("gdbstub", b.dependency("zba-gdbstub", .{}).module("zba-gdbstub")); // https://git.musuka.dev/paoda/zba-gdbstub
+    exe.root_module.addImport("zig-clap", b.dependency("zig-clap", .{}).module("clap")); // https://github.com/Hejsil/zig-clap
+    exe.root_module.addImport("zgui", zgui.module("root")); // https://git.musuka.dev/paoda/zgui
+    exe.root_module.addImport("sdl2", sdk.getNativeModule()); // https://github.com/MasterQ32/SDL.zig
 
-    // https://github.com/MasterQ32/SDL.zig
-    const sdk = Sdk.init(b, null);
-    sdk.link(exe, .dynamic);
-    exe.addModule("sdl2", sdk.getNativeModule());
+    exe.root_module.addAnonymousImport("bitfield", .{ .root_source_file = b.path("lib/bitfield.zig") }); // https://github.com/FlorenceOS/
+    exe.root_module.addAnonymousImport("gl", .{ .root_source_file = b.path("lib/gl.zig") }); // https://github.com/MasterQ32/zig-opengl
 
-    // https://git.musuka.dev/paoda/zgui
-    // .shared option should stay in sync with SDL.zig call above where true == .dynamic, and false == .static
-    const zgui_pkg = zgui.package(b, target, optimize, .{ .options = .{ .backend = .sdl2_opengl3, .shared = true } });
-    zgui_pkg.link(exe);
+    sdk.link(exe, .dynamic, .SDL2);
+    sdk.link(imgui, .dynamic, .SDL2);
+    exe.linkLibrary(imgui);
 
     // This declares intent for the executable to be installed into the
     // standard location when the user invokes the "install" step (the default
@@ -75,7 +73,7 @@ pub fn build(b: *std.Build) void {
     // Creates a step for unit testing. This only builds the test executable
     // but does not run it.
     const unit_tests = b.addTest(.{
-        .root_source_file = .{ .path = "src/main.zig" },
+        .root_source_file = b.path("src/main.zig"),
         .target = target,
         .optimize = optimize,
     });

build.zig.zon

@@ -1,15 +1,29 @@
 .{
     .name = "turbo",
     .version = "0.1.0",
+    .paths = .{
+        "lib/bitfield.zig",
+        "lib/gl.zig",
+        "src",
+        "build.zig",
+        "build.zig.zon",
+    },
     .dependencies = .{
         .@"zig-clap" = .{
-            .url = "https://github.com/Hejsil/zig-clap/archive/f49b94700e0761b7514abdca0e4f0e7f3f938a93.tar.gz",
-            .hash = "1220f48518ce22882e102255ed3bcdb7aeeb4891f50b2cdd3bd74b5b2e24d3149ba2",
+            .url = "git+https://github.com/Hejsil/zig-clap#c0193e9247335a6c1688b946325060289405de2a",
+            .hash = "12207ee987ce045596cb992cfb15b0d6d9456e50d4721c3061c69dabc2962053644d",
         },
-        .@"zba-util" = .{
-            // Necessary to use paoda/arm32 as a git submodule
-            .url = "https://git.musuka.dev/paoda/zba-util/archive/322c798e384a0d24cc84ffcfa2e4a3ca807798a0.tar.gz",
-            .hash = "12209ce0e729460b997706e47a53a32f1842672cd120189e612f4871731780a30ed0",
+        .@"zba-gdbstub" = .{
+            .url = "git+https://git.musuka.dev/paoda/zba-gdbstub#9a50607d5f48293f950a4e823344f2bc24582a5a",
+            .hash = "1220ac267744ed2a735f03c4620d7c6210fbd36d7bfb2b376ddc3436faebadee0f61",
+        },
+        .arm32 = .{
+            .url = "git+https://git.musuka.dev/paoda/arm32#814d081ea0983bc48841a6baad7158c157b17ad6",
+            .hash = "12203c3dacf3a7aa7aee5fc5763dd7b40399bd1c34d1483330b6bd5a76bffef22d82",
+        },
+        .zgui = .{
+            .url = "git+https://git.musuka.dev/paoda/zgui#7f8d05101e96c64314d7926c80ee157dcb89da4e",
+            .hash = "1220bd81a1c7734892b1d4233ed047710487787873c85dd5fc76d1764a331ed2ff43",
         },
     },
 }

dl_sdl2.ps1

@@ -0,0 +1,36 @@
+$SDL2Version = "2.30.0"
+$ArchiveFile = ".\SDL2-devel-mingw.zip"
+$Json = @"
+{
+	"x86_64-windows-gnu": {
+		"include": ".build_config\\SDL2\\include",
+		"libs": ".build_config\\SDL2\\lib",
+		"bin": ".build_config\\SDL2\\bin"
+	}
+}	
+"@
+
+New-Item -Force -ItemType Directory -Path .\.build_config
+Set-Location -Path .build_config -PassThru
+
+if (!(Test-Path -PathType Leaf $ArchiveFile)) {
+	Invoke-WebRequest "https://github.com/libsdl-org/SDL/releases/download/release-$SDL2Version/SDL2-devel-$SDL2Version-mingw.zip" -OutFile $ArchiveFile
+}
+
+Expand-Archive $ArchiveFile
+
+if (Test-Path -PathType Container .\SDL2) {
+	Remove-Item -Recurse .\SDL2
+}
+
+New-Item -Force -ItemType Directory -Path .\SDL2 
+Get-ChildItem -Path ".\SDL2-devel-mingw\SDL2-$SDL2Version\x86_64-w64-mingw32" | Move-Item -Destination .\SDL2
+
+# #include <SDL.h>
+Move-Item -Force -Path .\SDL2\include\SDL2\* -Destination .\SDL2\include
+Remove-Item -Force .\SDL2\include\SDL2
+
+New-Item -Force .\sdl.json -Value $Json
+
+Remove-Item -Recurse .\SDL2-devel-mingw
+Set-Location -Path .. -PassThru

src/core/Scheduler.zig

@@ -0,0 +1,96 @@
+const std = @import("std");
+
+const System = @import("emu.zig").System;
+
+const PriorityQueue = std.PriorityQueue(Event, void, Event.lessThan);
+const Allocator = std.mem.Allocator;
+
+tick: u64 = 0,
+queue: PriorityQueue,
+
+pub fn init(allocator: Allocator) !@This() {
+    var queue = PriorityQueue.init(allocator, {});
+    try queue.add(.{ .tick = std.math.maxInt(u64), .kind = .heat_death });
+
+    return .{ .queue = queue };
+}
+
+pub fn push(self: *@This(), kind: Event.Kind, offset: u64) void {
+    self.queue.add(.{ .kind = kind, .tick = self.tick + offset }) catch unreachable;
+}
+
+pub fn remove(self: *@This(), needle: Event.Kind) void {
+    for (self.queue.items, 0..) |event, i| {
+        if (!std.meta.eql(event.kind, needle)) continue;
+
+        _ = self.queue.removeIndex(i); // note: invalidates self.queue.items
+        return;
+    }
+}
+
+pub fn deinit(self: @This()) void {
+    self.queue.deinit();
+}
+
+pub fn now(self: @This()) u64 {
+    return self.tick;
+}
+
+pub fn reset(self: *@This()) void {
+    self.tick = 0;
+}
+
+pub inline fn peekTimestamp(self: *const @This()) u64 {
+    return self.queue.items[0].tick;
+}
+
+pub inline fn check(self: *@This()) ?Event {
+    @setRuntimeSafety(false);
+    if (self.tick < self.queue.items[0].tick) return null;
+
+    return self.queue.remove();
+}
+
+pub fn handle(self: *@This(), system: System, event: Event, late: u64) void {
+    switch (event.kind) {
+        .heat_death => unreachable,
+        .nds7 => |ev| {
+            const bus = system.bus7;
+            _ = bus;
+
+            switch (ev) {}
+        },
+        .nds9 => |ev| {
+            const bus = system.bus9;
+
+            switch (ev) {
+                .draw => {
+                    bus.ppu.drawScanline(bus);
+                    bus.ppu.onHdrawEnd(system, self, late);
+                },
+                .hblank => bus.ppu.onHblankEnd(system, self, late),
+                .vblank => bus.ppu.onVblankEnd(system, self, late),
+                .sqrt => bus.io.sqrt.onSqrtCalc(),
+                .div => bus.io.div.onDivCalc(),
+            }
+        },
+    }
+}
+
+pub const Event = struct {
+    tick: u64,
+    kind: Kind,
+
+    const Kind7 = enum {};
+    const Kind9 = enum { draw, hblank, vblank, sqrt, div };
+
+    pub const Kind = union(enum) {
+        nds7: Kind7,
+        nds9: Kind9,
+        heat_death: void,
+    };
+
+    fn lessThan(_: void, left: @This(), right: @This()) std.math.Order {
+        return std.math.order(left.tick, right.tick);
+    }
+};

src/core/emu.zig

@@ -1,23 +1,27 @@
 const std = @import("std");
-const nds9 = @import("nds9.zig");
-const nds7 = @import("nds7.zig");
 
 const Header = @import("cartridge.zig").Header;
-const SharedIo = @import("io.zig").Io;
-const Arm946es = nds9.Arm946es;
+const Scheduler = @import("Scheduler.zig");
+const Ui = @import("../platform.zig").Ui;
 
 const Allocator = std.mem.Allocator;
 
+const dma7 = @import("nds7/dma.zig");
+const dma9 = @import("nds9/dma.zig");
+
 /// Load a NDS Cartridge
 ///
 /// intended to be used immediately after Emulator initialization
-pub fn load(allocator: Allocator, nds7_group: nds7.Group, nds9_group: nds9.Group, rom_file: std.fs.File) ![12]u8 {
+pub fn load(allocator: Allocator, system: System, rom_path: []const u8) ![12]u8 {
     const log = std.log.scoped(.load_rom);
 
-    const rom_buf = try rom_file.readToEndAlloc(allocator, try rom_file.getEndPos());
-    defer allocator.free(rom_buf);
+    const file = try std.fs.cwd().openFile(rom_path, .{});
+    defer file.close();
 
-    var stream = std.io.fixedBufferStream(rom_buf);
+    const buf = try file.readToEndAlloc(allocator, try file.getEndPos());
+    defer allocator.free(buf);
+
+    var stream = std.io.fixedBufferStream(buf);
     const header = try stream.reader().readStruct(Header);
 
     log.info("Title: \"{s}\"", .{std.mem.sliceTo(&header.title, 0)});
@@ -26,117 +30,544 @@ pub fn load(allocator: Allocator, nds7_group: nds7.Group, nds9_group: nds9.Group
 
     // Dealing with the ARM946E-S
     {
-        const arm946es = nds9_group.cpu;
-
         log.debug("ARM9 ROM Offset: 0x{X:0>8}", .{header.arm9_rom_offset});
         log.debug("ARM9 Entry Address: 0x{X:0>8}", .{header.arm9_entry_address});
         log.debug("ARM9 RAM Address: 0x{X:0>8}", .{header.arm9_ram_address});
         log.debug("ARM9 Size: 0x{X:0>8}", .{header.arm9_size});
 
         // Copy ARM9 Code into Main Memory
-        for (rom_buf[header.arm9_rom_offset..][0..header.arm9_size], 0..) |value, i| {
+        for (buf[header.arm9_rom_offset..][0..header.arm9_size], 0..) |value, i| {
             const address = header.arm9_ram_address + @as(u32, @intCast(i));
-            nds9_group.bus.dbgWrite(u8, address, value);
+            system.bus9.dbgWrite(u8, address, value);
         }
 
-        arm946es.r[15] = header.arm9_entry_address;
+        system.arm946es.r[15] = header.arm9_entry_address;
     }
 
     // Dealing with the ARM7TDMI
     {
-        const arm7tdmi = nds7_group.cpu;
-
         log.debug("ARM7 ROM Offset: 0x{X:0>8}", .{header.arm7_rom_offset});
         log.debug("ARM7 Entry Address: 0x{X:0>8}", .{header.arm7_entry_address});
         log.debug("ARM7 RAM Address: 0x{X:0>8}", .{header.arm7_ram_address});
         log.debug("ARM7 Size: 0x{X:0>8}", .{header.arm7_size});
 
         // Copy ARM7 Code into Main Memory
-        for (rom_buf[header.arm7_rom_offset..][0..header.arm7_size], 0..) |value, i| {
+        for (buf[header.arm7_rom_offset..][0..header.arm7_size], 0..) |value, i| {
             const address = header.arm7_ram_address + @as(u32, @intCast(i));
-            nds7_group.bus.dbgWrite(u8, address, value);
+            system.bus7.dbgWrite(u8, address, value);
         }
 
-        arm7tdmi.r[15] = header.arm7_entry_address;
+        system.arm7tdmi.r[15] = header.arm7_entry_address;
     }
 
     return header.title;
 }
 
+/// Load NDS Firmware
+pub fn loadFirm(allocator: Allocator, system: System, firm_path: []const u8) !void {
+    const log = std.log.scoped(.load_firm);
+
+    { // NDS7 BIOS
+        const path = try std.mem.join(allocator, "/", &.{ firm_path, "bios7.bin" });
+        defer allocator.free(path);
+
+        log.debug("bios7 path: {s}", .{path});
+
+        const file = try std.fs.cwd().openFile(path, .{});
+        defer file.close();
+
+        const buf = try file.readToEndAlloc(allocator, try file.getEndPos());
+        defer allocator.free(buf);
+
+        try system.bus7.bios.load(allocator, buf);
+    }
+
+    { // NDS9 BIOS
+        const path = try std.mem.join(allocator, "/", &.{ firm_path, "bios9.bin" });
+        defer allocator.free(path);
+
+        log.debug("bios9 path: {s}", .{path});
+
+        const file = try std.fs.cwd().openFile(path, .{});
+        defer file.close();
+
+        const buf = try file.readToEndAlloc(allocator, try file.getEndPos());
+        defer allocator.free(buf);
+
+        try system.bus9.bios.load(allocator, buf);
+    }
+}
+
 const bus_clock = 33513982; // 33.513982 Hz
 const dot_clock = 5585664; //   5.585664 Hz
 const arm7_clock = bus_clock;
 const arm9_clock = bus_clock * 2;
 
-pub fn runFrame(nds7_group: nds7.Group, nds9_group: nds9.Group) void {
-    // TODO: might be more efficient to run them both in the same loop?
-    {
-        const scheduler = nds9_group.scheduler;
+pub fn runFrame(scheduler: *Scheduler, system: System) void {
+    const cycles_per_dot = arm9_clock / dot_clock + 1;
+    comptime std.debug.assert(cycles_per_dot == 12);
 
-        const cycles_per_dot = arm9_clock / dot_clock + 1;
-        comptime std.debug.assert(cycles_per_dot == 12);
+    const cycles_per_frame = 355 * 263 * cycles_per_dot;
+    const frame_end = scheduler.tick + cycles_per_frame;
 
-        const cycles_per_frame = 355 * 263 * cycles_per_dot;
-        const frame_end = scheduler.tick + cycles_per_frame;
+    while (scheduler.tick < frame_end) {
+        switch (isHalted(system)) {
+            .both => scheduler.tick = scheduler.peekTimestamp(),
+            inline else => |halt| {
+                if (!dma9.step(system.arm946es) and comptime halt != .arm9) {
+                    system.arm946es.step();
+                    system.arm946es.step();
+                }
 
-        const cpu = nds9_group.cpu;
-        const bus = nds9_group.bus;
-
-        while (scheduler.tick < frame_end) {
-            cpu.step();
-
-            if (scheduler.tick >= scheduler.next()) scheduler.handle(bus);
+                if (!dma7.step(system.arm7tdmi) and comptime halt != .arm7) {
+                    system.arm7tdmi.step();
+                }
+            },
         }
-    }
 
-    {
-        const scheduler = nds7_group.scheduler;
-
-        const cycles_per_dot = arm7_clock / dot_clock + 1;
-        comptime std.debug.assert(cycles_per_dot == 6);
-
-        const cycles_per_frame = 355 * 263 * cycles_per_dot;
-        const frame_end = scheduler.tick + cycles_per_frame;
-
-        const cpu = nds7_group.cpu;
-        const bus = nds7_group.bus;
-
-        while (scheduler.tick < frame_end) {
-            cpu.step();
-
-            if (scheduler.tick >= scheduler.next()) scheduler.handle(bus);
+        if (scheduler.check()) |ev| {
+            const late = scheduler.tick - ev.tick;
+            scheduler.handle(system, ev, late);
         }
     }
 }
 
-// FIXME: Perf win to allocating on the stack instead?
-pub const SharedContext = struct {
-    const MiB = 0x100000;
+const Halted = enum { arm7, arm9, both, none };
 
-    io: *SharedIo,
+inline fn isHalted(system: System) Halted {
+    const ret = [_]Halted{ .none, .arm7, .arm9, .both };
+    const nds7_bus: *System.Bus7 = @ptrCast(@alignCast(system.arm7tdmi.bus.ptr));
+
+    const nds9_halt: u2 = @intFromBool(system.cp15.wait_for_interrupt);
+    const nds7_halt: u2 = @intFromBool(nds7_bus.io.haltcnt == .halt);
+
+    return ret[(nds9_halt << 1) | nds7_halt];
+}
+
+// FIXME: Perf win to allocating on the stack instead?
+pub const SharedCtx = struct {
+    const MiB = 0x100000;
+    const KiB = 0x400;
+
+    pub const Io = @import("io.zig").Io;
+    const Vram = @import("ppu/Vram.zig");
+
+    io: *Io,
     main: *[4 * MiB]u8,
+    wram: *Wram,
+    vram: *Vram,
 
     pub fn init(allocator: Allocator) !@This() {
+        const wram = try allocator.create(Wram);
+        errdefer allocator.destroy(wram);
+        try wram.init(allocator);
+
+        const vram = try allocator.create(Vram);
+        errdefer allocator.destroy(vram);
+        try vram.init(allocator);
+
         const ctx = .{
-            .io = try allocator.create(SharedIo),
+            .io = blk: {
+                const io = try allocator.create(Io);
+                io.* = .{};
+
+                break :blk io;
+            },
+            .wram = wram,
+            .vram = vram,
             .main = try allocator.create([4 * MiB]u8),
         };
-        ctx.io.* = .{};
 
         return ctx;
     }
 
     pub fn deinit(self: @This(), allocator: Allocator) void {
+        self.wram.deinit(allocator);
+        allocator.destroy(self.wram);
+
+        self.vram.deinit(allocator);
+        allocator.destroy(self.vram);
+
         allocator.destroy(self.io);
         allocator.destroy(self.main);
     }
 };
 
+// Before I implement Bus-wide Fastmem, Let's play with some more limited (read: less useful)
+// fastmem implementations
+
+// TODO: move somewhere else ideally
+pub const Wram = struct {
+    const page_size = 1 * KiB; // perhaps too big?
+    const addr_space_size = 0x8000;
+    const table_len = addr_space_size / page_size;
+    const buf_len = 32 * KiB;
+
+    const IntFittingRange = std.math.IntFittingRange;
+
+    const io = @import("io.zig");
+    const KiB = 0x400;
+
+    const log = std.log.scoped(.shared_wram);
+
+    _buf: *[buf_len]u8,
+
+    nds9_table: *const [table_len]?[*]u8,
+    nds7_table: *const [table_len]?[*]u8,
+
+    pub fn init(self: *@This(), allocator: Allocator) !void {
+        const buf = try allocator.create([buf_len]u8);
+        errdefer allocator.destroy(buf);
+
+        const tables = try allocator.alloc(?[*]u8, 2 * table_len);
+        @memset(tables, null);
+
+        self.* = .{
+            .nds9_table = tables[0..table_len],
+            .nds7_table = tables[table_len .. 2 * table_len],
+            ._buf = buf,
+        };
+    }
+
+    pub fn deinit(self: @This(), allocator: Allocator) void {
+        allocator.destroy(self._buf);
+
+        const ptr: [*]?[*]const u8 = @ptrCast(@constCast(self.nds9_table));
+        allocator.free(ptr[0 .. 2 * table_len]);
+    }
+
+    pub fn update(self: *@This(), wramcnt: io.WramCnt) void {
+        const mode = wramcnt.mode.read();
+
+        const nds9_tbl = @constCast(self.nds9_table);
+        const nds7_tbl = @constCast(self.nds7_table);
+
+        for (nds9_tbl, nds7_tbl, 0..) |*nds9_ptr, *nds7_ptr, i| {
+            const addr = i * page_size;
+
+            switch (mode) {
+                0b00 => {
+                    nds9_ptr.* = self._buf[addr..].ptr;
+                    nds7_ptr.* = null;
+                },
+                0b01 => {
+                    nds9_ptr.* = self._buf[0x4000 + (addr & 0x3FFF) ..].ptr;
+                    nds7_ptr.* = self._buf[(addr & 0x3FFF)..].ptr;
+                },
+                0b10 => {
+                    nds9_ptr.* = self._buf[(addr & 0x3FFF)..].ptr;
+                    nds7_ptr.* = self._buf[0x4000 + (addr & 0x3FFF) ..].ptr;
+                },
+                0b11 => {
+                    nds9_ptr.* = null;
+                    nds7_ptr.* = self._buf[addr..].ptr;
+                },
+            }
+        }
+    }
+
+    pub fn read(self: @This(), comptime T: type, comptime proc: System.Process, address: u32) T {
+        const bits = @typeInfo(IntFittingRange(0, page_size - 1)).Int.bits;
+        const masked_addr = address & (addr_space_size - 1);
+        const page = masked_addr >> bits;
+        const offset = masked_addr & (page_size - 1);
+        const table = if (proc == .nds9) self.nds9_table else self.nds7_table;
+
+        if (table[page]) |some_ptr| {
+            const ptr: [*]const T = @ptrCast(@alignCast(some_ptr));
+
+            return ptr[offset / @sizeOf(T)];
+        }
+
+        log.err("{s}: read(T: {}, addr: 0x{X:0>8}) was in un-mapped WRAM space", .{ @tagName(proc), T, 0x0300_0000 + address });
+        return 0x00;
+    }
+
+    pub fn write(self: *@This(), comptime T: type, comptime proc: System.Process, address: u32, value: T) void {
+        const bits = @typeInfo(IntFittingRange(0, page_size - 1)).Int.bits;
+        const masked_addr = address & (addr_space_size - 1);
+        const page = masked_addr >> bits;
+        const offset = masked_addr & (page_size - 1);
+        const table = if (proc == .nds9) self.nds9_table else self.nds7_table;
+
+        if (table[page]) |some_ptr| {
+            const ptr: [*]T = @ptrCast(@alignCast(some_ptr));
+            ptr[offset / @sizeOf(T)] = value;
+
+            return;
+        }
+
+        log.err("{s}: write(T: {}, addr: 0x{X:0>8}, value: 0x{X:0>8}) was in un-mapped WRAM space", .{ @tagName(proc), T, 0x0300_0000 + address, value });
+    }
+};
+
 pub inline fn forceAlign(comptime T: type, address: u32) u32 {
-    return switch (T) {
-        u32 => address & ~@as(u32, 3),
-        u16 => address & ~@as(u32, 1),
-        u8 => address,
-        else => @compileError("Bus: Invalid read/write type"),
-    };
+    return address & ~@as(u32, @sizeOf(T) - 1);
 }
+
+pub const System = struct {
+    pub const Bus7 = @import("nds7/Bus.zig");
+    pub const Bus9 = @import("nds9/Bus.zig");
+    pub const Cp15 = @import("nds9/Cp15.zig");
+
+    pub const Arm7tdmi = @import("arm32").Arm7tdmi;
+    pub const Arm946es = @import("arm32").Arm946es;
+
+    pub const Process = enum { nds7, nds9 };
+
+    arm7tdmi: *Arm7tdmi,
+    arm946es: *Arm946es,
+
+    bus7: *Bus7,
+    bus9: *Bus9,
+
+    cp15: *Cp15,
+
+    pub fn deinit(self: @This(), allocator: Allocator) void {
+        self.bus7.deinit(allocator);
+        self.bus9.deinit(allocator);
+    }
+
+    fn Cpu(comptime proc: Process) type {
+        return switch (proc) {
+            .nds7 => Arm7tdmi,
+            .nds9 => Arm946es,
+        };
+    }
+
+    fn Bus(comptime proc: Process) type {
+        return switch (proc) {
+            .nds7 => Bus7,
+            .nds9 => Bus9,
+        };
+    }
+};
+
+pub fn handleInterrupt(comptime proc: System.Process, cpu: *System.Cpu(proc)) void {
+    const bus_ptr: *System.Bus(proc) = @ptrCast(@alignCast(cpu.bus.ptr));
+
+    if (!bus_ptr.io.ime or cpu.cpsr.i.read()) return; // ensure irqs are enabled
+    if ((bus_ptr.io.ie.raw & bus_ptr.io.irq.raw) == 0) return; // ensure there is an irq to handle
+
+    switch (proc) {
+        .nds9 => {
+            const cp15: *System.Cp15 = @ptrCast(@alignCast(cpu.cp15.ptr));
+            cp15.wait_for_interrupt = false;
+        },
+        .nds7 => bus_ptr.io.haltcnt = .execute,
+    }
+
+    const ret_addr = cpu.r[15] - if (cpu.cpsr.t.read()) 0 else @as(u32, 4);
+    const spsr = cpu.cpsr;
+
+    cpu.changeMode(.Irq);
+    cpu.cpsr.t.unset();
+    cpu.cpsr.i.set();
+
+    cpu.r[14] = ret_addr;
+    cpu.spsr.raw = spsr.raw;
+    cpu.r[15] = if (proc == .nds9) 0xFFFF_0018 else 0x0000_0018;
+    cpu.pipe.reload(cpu);
+}
+
+pub fn fastBoot(system: System) void {
+    {
+        const Bank = System.Arm946es.Bank;
+
+        const cpu = system.arm946es;
+
+        // from advanDS
+        cpu.spsr = .{ .raw = 0x0000_000DF };
+
+        @memset(cpu.r[0..12], 0x0000_0000); // r0 -> r11 are zeroed
+        // TODO: r12, r14, and r15 are set to the entrypoint?
+        cpu.r[13] = 0x0300_2F7C; // FIXME: Why is there (!) in GBATEK?
+        cpu.bank.r[Bank.regIdx(.Irq, .R13)] = 0x0300_3F80;
+        cpu.bank.r[Bank.regIdx(.Supervisor, .R13)] = 0x0300_3FC0;
+        cpu.bank.spsr[Bank.spsrIdx(.Irq)] = .{ .raw = 0x0000_0000 };
+        cpu.bank.spsr[Bank.spsrIdx(.Supervisor)] = .{ .raw = 0x0000_0000 };
+    }
+    {
+        const Bank = System.Arm7tdmi.Bank;
+
+        const cpu = system.arm7tdmi;
+
+        // from advanDS
+        cpu.spsr = .{ .raw = 0x0000_000D3 };
+
+        @memset(cpu.r[0..12], 0x0000_0000); // r0 -> r11 are zeroed
+        // TODO: r12, r14, and r15 are set to the entrypoint?
+        cpu.r[13] = 0x0380_FD80;
+        cpu.bank.r[Bank.regIdx(.Irq, .R13)] = 0x0380_FF80;
+        cpu.bank.r[Bank.regIdx(.Supervisor, .R13)] = 0x0380_FFC0;
+        cpu.bank.spsr[Bank.spsrIdx(.Irq)] = .{ .raw = 0x0000_0000 };
+        cpu.bank.spsr[Bank.spsrIdx(.Supervisor)] = .{ .raw = 0x0000_0000 };
+    }
+}
+
+pub const Sync = struct {
+    const Atomic = std.atomic.Value;
+
+    should_quit: Atomic(bool) = Atomic(bool).init(false),
+
+    pub fn init(self: *Sync) void {
+        self.* = .{};
+    }
+};
+
+pub const debug = struct {
+    const Interface = @import("gdbstub").Emulator;
+    const Server = @import("gdbstub").Server;
+    const AtomicBool = std.atomic.Value(bool);
+    const log = std.log.scoped(.gdbstub);
+
+    const nds7 = struct {
+        const target: []const u8 =
+            \\<target version="1.0">
+            \\    <architecture>armv4t</architecture>
+            \\    <feature name="org.gnu.gdb.arm.core">
+            \\        <reg name="r0" bitsize="32" type="uint32"/>
+            \\        <reg name="r1" bitsize="32" type="uint32"/>
+            \\        <reg name="r2" bitsize="32" type="uint32"/>
+            \\        <reg name="r3" bitsize="32" type="uint32"/>
+            \\        <reg name="r4" bitsize="32" type="uint32"/>
+            \\        <reg name="r5" bitsize="32" type="uint32"/>
+            \\        <reg name="r6" bitsize="32" type="uint32"/>
+            \\        <reg name="r7" bitsize="32" type="uint32"/>
+            \\        <reg name="r8" bitsize="32" type="uint32"/>
+            \\        <reg name="r9" bitsize="32" type="uint32"/>
+            \\        <reg name="r10" bitsize="32" type="uint32"/>
+            \\        <reg name="r11" bitsize="32" type="uint32"/>
+            \\        <reg name="r12" bitsize="32" type="uint32"/>
+            \\        <reg name="sp" bitsize="32" type="data_ptr"/>
+            \\        <reg name="lr" bitsize="32"/>
+            \\        <reg name="pc" bitsize="32" type="code_ptr"/>
+            \\
+            \\        <reg name="cpsr" bitsize="32" regnum="25"/>
+            \\    </feature>
+            \\</target>
+        ;
+
+        // Remember that a lot of memory regions are mirrored
+        const memory_map: []const u8 =
+            \\ <memory-map version="1.0">
+            \\     <memory type="rom" start="0x00000000" length="0x00004000"/>
+            \\     <memory type="ram" start="0x02000000" length="0x01000000"/>
+            \\     <memory type="ram" start="0x03000000" length="0x00800000"/>
+            \\     <memory type="ram" start="0x03800000" length="0x00800000"/>
+            \\     <memory type="ram" start="0x04000000" length="0x00100010"/>
+            \\     <memory type="ram" start="0x06000000" length="0x01000000"/>
+            \\     <memory type="rom" start="0x08000000" length="0x02000000"/>
+            \\     <memory type="rom" start="0x0A000000" length="0x01000000"/>
+            \\ </memory-map>
+        ;
+    };
+
+    pub fn Wrapper(comptime proc: System.Process) type {
+        return struct {
+            system: System,
+            scheduler: *Scheduler,
+
+            tick: u64 = 0,
+
+            pub fn init(system: System, scheduler: *Scheduler) @This() {
+                return .{ .system = system, .scheduler = scheduler };
+            }
+
+            pub fn interface(self: *@This(), allocator: Allocator) Interface {
+                return Interface.init(allocator, self);
+            }
+
+            pub fn read(self: *const @This(), addr: u32) u8 {
+                const arm = switch (proc) {
+                    .nds7 => self.system.arm7tdmi,
+                    .nds9 => self.system.arm946es,
+                };
+
+                return arm.dbgRead(u8, addr);
+            }
+
+            pub fn write(self: *@This(), addr: u32, value: u8) void {
+                const arm = switch (proc) {
+                    .nds7 => self.system.arm7tdmi,
+                    .nds9 => self.system.arm946es,
+                };
+
+                return arm.dbgWrite(u8, addr, value);
+            }
+
+            pub fn registers(self: *const @This()) *[16]u32 {
+                const arm = switch (proc) {
+                    .nds7 => self.system.arm7tdmi,
+                    .nds9 => self.system.arm946es,
+                };
+
+                return &arm.r;
+            }
+
+            pub fn cpsr(self: *const @This()) u32 {
+                const arm = switch (proc) {
+                    .nds7 => self.system.arm7tdmi,
+                    .nds9 => self.system.arm946es,
+                };
+
+                return arm.cpsr.raw;
+            }
+
+            pub fn step(self: *@This()) void {
+                const scheduler = self.scheduler;
+                const system = self.system;
+
+                var did_step: bool = false;
+
+                // TODO: keep in lockstep with runFrame
+                while (true) {
+                    if (did_step) break;
+
+                    switch (isHalted(system)) {
+                        .both => scheduler.tick = scheduler.peekTimestamp(),
+                        inline else => |halt| {
+                            if (!dma9.step(system.arm946es) and comptime halt != .arm9) {
+                                system.arm946es.step();
+
+                                switch (proc) {
+                                    .nds9 => did_step = true,
+                                    .nds7 => system.arm946es.step(),
+                                }
+                            }
+
+                            if (!dma7.step(system.arm7tdmi) and comptime halt != .arm7) {
+                                if (proc == .nds7 or self.tick % 2 == 0) system.arm7tdmi.step();
+
+                                if (proc == .nds7) {
+                                    did_step = true;
+                                    self.tick += 1;
+                                }
+                            }
+                        },
+                    }
+
+                    if (scheduler.check()) |ev| {
+                        const late = scheduler.tick - ev.tick;
+                        scheduler.handle(system, ev, late);
+                    }
+                }
+            }
+        };
+    }
+
+    pub fn run(allocator: Allocator, ui: *Ui, scheduler: *Scheduler, system: System, sync: *Sync) !void {
+        var wrapper = Wrapper(.nds9).init(system, scheduler);
+
+        var emu_interface = wrapper.interface(allocator);
+        defer emu_interface.deinit();
+
+        var server = try Server.init(emu_interface, .{ .target = nds7.target, .memory_map = nds7.memory_map });
+        defer server.deinit(allocator);
+
+        const thread = try std.Thread.spawn(.{}, Server.run, .{ &server, allocator, &sync.should_quit });
+        defer thread.join();
+
+        try ui.debug_run(scheduler, system, sync);
+    }
+};

src/core/io.zig

@@ -2,36 +2,19 @@ const std = @import("std");
 
 const Bitfield = @import("bitfield").Bitfield;
 const Bit = @import("bitfield").Bit;
+const System = @import("emu.zig").System;
+const handleInterrupt = @import("emu.zig").handleInterrupt;
 
 const log = std.log.scoped(.shared_io);
 
 pub const Io = struct {
-    /// Interrupt Master Enable
-    /// Read/Write
-    ime: bool = false,
-
-    /// Interrupt Enable
-    /// Read/Write
-    ///
-    /// Caller must cast the `u32` to either `nds7.IntEnable` or `nds9.IntEnable`
-    ie: u32 = 0x0000_0000,
-
-    /// IF - Interrupt Request
-    /// Read/Write
-    ///
-    /// Caller must cast the `u32` to either `nds7.IntRequest` or `nds9.IntRequest`
-    irq: u32 = 0x0000_0000,
-
     /// Inter Process Communication FIFO
-    ipc_fifo: IpcFifo = .{},
+    ipc: Ipc = .{},
 
-    /// Post Boot Flag
-    /// Read/Write
-    ///
-    /// Caller must cast the `u8` to either `nds7.PostFlg` or `nds9.PostFlg`
-    post_flg: u8 = @intFromEnum(nds7.PostFlag.in_progress),
+    wramcnt: WramCnt = .{ .raw = 0x00 },
 
-    // TODO: DS Cartridge I/O Ports
+    // Read Only
+    input: Input = .{},
 };
 
 fn warn(comptime format: []const u8, args: anytype) u0 {
@@ -39,120 +22,222 @@ fn warn(comptime format: []const u8, args: anytype) u0 {
     return 0;
 }
 
-// TODO: Please Rename
-// TODO: Figure out a way to apply masks while calling valueAtAddressOffset
-// TODO: These aren't optimized well. Can we improve that?
-pub inline fn valueAtAddressOffset(comptime T: type, address: u32, value: T) u8 {
-    const L2I = std.math.Log2Int(T);
-
-    return @truncate(switch (T) {
-        u16 => value >> @as(L2I, @truncate((address & 1) << 3)),
-        u32 => value >> @as(L2I, @truncate((address & 3) << 3)),
-        else => @compileError("unsupported for " ++ @typeName(T) ++ "values"),
-    });
-}
-
-fn WriteOption(comptime T: type) type {
-    return struct { mask: ?T = null };
-}
-
-// TODO: also please rename
-// TODO: Figure out a way to apply masks while calling writeToAddressOffset
-// TODO: These aren't optimized well. Can we improve that?
-pub inline fn writeToAddressOffset(
-    register: anytype,
-    address: u32,
-    value: anytype,
-    // mask: WriteOption(@typeInfo(@TypeOf(register)).Pointer.child),
-) void {
-    const Ptr = @TypeOf(register);
-    const ChildT = @typeInfo(Ptr).Pointer.child;
-    const ValueT = @TypeOf(value);
-
-    const left = register.*;
-
-    register.* = switch (ChildT) {
-        u32 => switch (ValueT) {
-            u16 => blk: {
-                // TODO: This probably gets deleted
-                const offset: u1 = @truncate(address >> 1);
-
-                break :blk switch (offset) {
-                    0b0 => (left & 0xFFFF_0000) | value,
-                    0b1 => (left & 0x0000_FFFF) | @as(u32, value) << 16,
-                };
-            },
-            u8 => blk: {
-                // TODO: Remove branching
-                const offset: u2 = @truncate(address);
-
-                break :blk switch (offset) {
-                    0b00 => (left & 0xFFFF_FF00) | value,
-                    0b01 => (left & 0xFFFF_00FF) | @as(u32, value) << 8,
-                    0b10 => (left & 0xFF00_FFFF) | @as(u32, value) << 16,
-                    0b11 => (left & 0x00FF_FFFF) | @as(u32, value) << 24,
-                };
-            },
-            else => @compileError("for " ++ @typeName(Ptr) ++ ", T must be u16 or u8"),
-        },
-        u16 => blk: {
-            if (ValueT != u8) @compileError("for " ++ @typeName(Ptr) ++ ", T must be u8");
-
-            const shamt = @as(u4, @truncate(address & 1)) << 3;
-            const mask: u16 = 0xFF00 >> shamt;
-            const value_shifted = @as(u16, value) << shamt;
-
-            break :blk (left & mask) | value_shifted;
-        },
-        else => @compileError("unsupported for " ++ @typeName(Ptr) ++ " values"),
-    };
-}
-
-const IpcFifo = struct {
+/// Inter-Process Communication
+const Ipc = struct {
     const Sync = IpcSync;
     const Control = IpcFifoCnt;
 
-    /// IPC Synchronize
+    _nds7: Impl = .{},
+    _nds9: Impl = .{},
+
+    // we need access to the CPUs to handle IPC IRQs
+    arm7tdmi: ?*System.Arm7tdmi = null,
+    arm946es: ?*System.Arm946es = null,
+
+    // TODO: DS Cartridge I/O Ports
+
+    const Impl = struct {
+        /// IPC Synchronize
+        /// Read/Write
+        sync: Sync = .{ .raw = 0x0000_0000 },
+
+        /// IPC Fifo Control
+        /// Read/Write
+        cnt: Control = .{ .raw = 0x0000_0101 },
+
+        fifo: Fifo = Fifo{},
+
+        /// Latch containing thel last read value from a FIFO
+        last_read: ?u32 = null,
+    };
+
+    pub fn configure(self: *@This(), system: System) void {
+        self.arm7tdmi = system.arm7tdmi;
+        self.arm946es = system.arm946es;
+    }
+
+    /// IPCSYNC
     /// Read/Write
-    sync: Sync = .{ .raw = 0x0000_0000 },
+    pub fn setIpcSync(self: *@This(), comptime proc: System.Process, value: anytype) void {
+        switch (proc) {
+            .nds7 => {
+                self._nds7.sync.raw = masks.ipcFifoSync(self._nds7.sync.raw, value);
+                self._nds9.sync.raw = masks.mask(self._nds9.sync.raw, (self._nds7.sync.raw >> 8) & 0xF, 0xF);
 
-    /// IPC Fifo Control
+                if (value >> 13 & 1 == 1 and self._nds9.sync.recv_irq.read()) {
+                    const bus: *System.Bus9 = @ptrCast(@alignCast(self.arm946es.?.bus.ptr));
+
+                    bus.io.irq.ipcsync.set();
+                    handleInterrupt(.nds9, self.arm946es.?);
+                }
+
+                if (value >> 3 & 1 == 1) {
+                    self._nds7.fifo.reset();
+
+                    self._nds7.cnt.send_fifo_empty.set();
+                    self._nds9.cnt.recv_fifo_empty.set();
+
+                    self._nds7.cnt.send_fifo_full.unset();
+                    self._nds9.cnt.recv_fifo_full.unset();
+                }
+            },
+            .nds9 => {
+                self._nds9.sync.raw = masks.ipcFifoSync(self._nds9.sync.raw, value);
+                self._nds7.sync.raw = masks.mask(self._nds7.sync.raw, (self._nds9.sync.raw >> 8) & 0xF, 0xF);
+
+                if (value >> 13 & 1 == 1 and self._nds7.sync.recv_irq.read()) {
+                    const bus: *System.Bus7 = @ptrCast(@alignCast(self.arm7tdmi.?.bus.ptr));
+
+                    bus.io.irq.ipcsync.set();
+                    handleInterrupt(.nds7, self.arm7tdmi.?);
+                }
+
+                if (value >> 3 & 1 == 1) {
+                    self._nds9.fifo.reset();
+
+                    self._nds9.cnt.send_fifo_empty.set();
+                    self._nds7.cnt.recv_fifo_empty.set();
+
+                    self._nds9.cnt.send_fifo_full.unset();
+                    self._nds7.cnt.recv_fifo_full.unset();
+                }
+            },
+        }
+    }
+
+    /// IPCFIFOCNT
     /// Read/Write
-    cnt: Control = .{ .raw = 0x0000_0000 },
-
-    fifo: [2]Fifo = .{ Fifo{}, Fifo{} },
-
-    const Source = enum { arm7, arm9 };
+    pub fn setIpcFifoCnt(self: *@This(), comptime proc: System.Process, value: anytype) void {
+        switch (proc) {
+            .nds7 => self._nds7.cnt.raw = masks.ipcFifoCnt(self._nds7.cnt.raw, value),
+            .nds9 => self._nds9.cnt.raw = masks.ipcFifoCnt(self._nds9.cnt.raw, value),
+        }
+    }
 
     /// IPC Send FIFO
     /// Write-Only
-    pub fn send(self: *@This(), comptime src: Source, value: u32) !void {
-        const idx = switch (src) {
-            .arm7 => 0,
-            .arm9 => 1,
-        };
+    pub fn send(self: *@This(), comptime proc: System.Process, value: u32) void {
+        switch (proc) {
+            .nds7 => {
+                if (!self._nds7.cnt.enable_fifos.read()) return;
+                self._nds7.fifo.push(value) catch unreachable; // see early return above
 
-        if (!self.cnt.enable_fifos.read()) return;
+                const not_empty_cache = !self._nds9.cnt.recv_fifo_empty.read();
 
-        try self.fifo[idx].push(value);
+                // update status bits
+                self._nds7.cnt.send_fifo_empty.write(self._nds7.fifo._len() == 0);
+                self._nds9.cnt.recv_fifo_empty.write(self._nds7.fifo._len() == 0);
+
+                self._nds7.cnt.send_fifo_full.write(self._nds7.fifo._len() == 0x10);
+                self._nds9.cnt.recv_fifo_full.write(self._nds7.fifo._len() == 0x10);
+
+                const not_empty = !self._nds9.cnt.recv_fifo_empty.read();
+
+                if (self._nds9.cnt.recv_fifo_irq_enable.read() and !not_empty_cache and not_empty) {
+                    // NDS7 Send | NDS9 RECV (Handling Not Empty)
+
+                    const bus: *System.Bus9 = @ptrCast(@alignCast(self.arm946es.?.bus.ptr));
+                    bus.io.irq.ipc_recv_not_empty.set();
+
+                    handleInterrupt(.nds9, self.arm946es.?);
+                }
+            },
+            .nds9 => {
+                if (!self._nds9.cnt.enable_fifos.read()) return;
+                self._nds9.fifo.push(value) catch unreachable; // see early return above
+
+                const not_empty_cache = !self._nds7.cnt.recv_fifo_empty.read();
+
+                // update status bits
+                self._nds9.cnt.send_fifo_empty.write(self._nds9.fifo._len() == 0);
+                self._nds7.cnt.recv_fifo_empty.write(self._nds9.fifo._len() == 0);
+
+                self._nds9.cnt.send_fifo_full.write(self._nds9.fifo._len() == 0x10);
+                self._nds7.cnt.recv_fifo_full.write(self._nds9.fifo._len() == 0x10);
+
+                const not_empty = !self._nds7.cnt.recv_fifo_empty.read();
+
+                if (self._nds7.cnt.recv_fifo_irq_enable.read() and !not_empty_cache and not_empty) {
+                    // NDS9 Send | NDS7 RECV (Handling Not Empty)
+
+                    const bus: *System.Bus7 = @ptrCast(@alignCast(self.arm7tdmi.?.bus.ptr));
+                    bus.io.irq.ipc_recv_not_empty.set();
+
+                    handleInterrupt(.nds7, self.arm7tdmi.?);
+                }
+            },
+        }
     }
 
     /// IPC Receive FIFO
     /// Read-Only
-    pub fn recv(self: *@This(), comptime src: Source) u32 {
-        const idx = switch (src) {
-            .arm7 => 1, // switched around on purpose
-            .arm9 => 0,
-        };
+    pub fn recv(self: *@This(), comptime proc: System.Process) u32 {
+        switch (proc) {
+            .nds7 => {
+                const enabled = self._nds7.cnt.enable_fifos.read();
+                const val_opt = if (enabled) self._nds9.fifo.pop() else self._nds9.fifo.peek();
 
-        const enabled = self.cnt.enable_fifos.read();
-        const val_opt = if (enabled) self.fifo[idx].pop() else self.fifo[idx].peek();
+                const value = if (val_opt) |val| blk: {
+                    self._nds9.last_read = val;
+                    break :blk val;
+                } else blk: {
+                    self._nds7.cnt.fifo_error.set();
+                    break :blk self._nds7.last_read orelse 0x0000_0000;
+                };
 
-        return val_opt orelse blk: {
-            self.cnt.send_fifo_empty.set();
+                const empty_cache = self._nds9.cnt.send_fifo_empty.read();
 
-            break :blk 0x0000_0000;
-        };
+                // update status bits
+                self._nds7.cnt.recv_fifo_empty.write(self._nds9.fifo._len() == 0);
+                self._nds9.cnt.send_fifo_empty.write(self._nds9.fifo._len() == 0);
+
+                self._nds7.cnt.recv_fifo_full.write(self._nds9.fifo._len() == 0x10);
+                self._nds9.cnt.send_fifo_full.write(self._nds9.fifo._len() == 0x10);
+
+                const empty = self._nds9.cnt.send_fifo_empty.read();
+
+                if (self._nds9.cnt.send_fifo_irq_enable.read() and (!empty_cache and empty)) {
+                    const bus: *System.Bus9 = @ptrCast(@alignCast(self.arm946es.?.bus.ptr));
+                    bus.io.irq.ipc_send_empty.set();
+
+                    handleInterrupt(.nds9, self.arm946es.?);
+                }
+
+                return value;
+            },
+            .nds9 => {
+                const enabled = self._nds9.cnt.enable_fifos.read();
+                const val_opt = if (enabled) self._nds7.fifo.pop() else self._nds7.fifo.peek();
+
+                const value = if (val_opt) |val| blk: {
+                    self._nds7.last_read = val;
+                    break :blk val;
+                } else blk: {
+                    self._nds9.cnt.fifo_error.set();
+                    break :blk self._nds7.last_read orelse 0x0000_0000;
+                };
+
+                const empty_cache = self._nds7.cnt.send_fifo_empty.read();
+
+                // update status bits
+                self._nds9.cnt.recv_fifo_empty.write(self._nds7.fifo._len() == 0);
+                self._nds7.cnt.send_fifo_empty.write(self._nds7.fifo._len() == 0);
+
+                self._nds9.cnt.recv_fifo_full.write(self._nds7.fifo._len() == 0x10);
+                self._nds7.cnt.send_fifo_full.write(self._nds7.fifo._len() == 0x10);
+
+                const empty = self._nds7.cnt.send_fifo_empty.read();
+
+                if (self._nds7.cnt.send_fifo_irq_enable.read() and (!empty_cache and empty)) {
+                    const bus: *System.Bus7 = @ptrCast(@alignCast(self.arm7tdmi.?.bus.ptr));
+                    bus.io.irq.ipc_send_empty.set();
+
+                    handleInterrupt(.nds7, self.arm7tdmi.?);
+                }
+
+                return value;
+            },
+        }
     }
 };
 
@@ -204,23 +289,51 @@ const IpcFifoCnt = extern union {
     raw: u32,
 };
 
-pub const nds7 = struct {
-    pub const IntEnable = extern union {
-        raw: u32,
-    };
-
-    pub const IntRequest = IntEnable;
-    pub const PostFlag = enum(u8) { in_progress = 0, completed };
+pub const WramCnt = extern union {
+    mode: Bitfield(u8, 0, 2),
+    raw: u8,
 };
 
-pub const nds9 = struct {
-    pub const IntEnable = extern union {
-        raw: u32,
-    };
+pub const masks = struct {
+    const Bus9 = @import("nds9/Bus.zig");
+    const Bus7 = @import("nds7/Bus.zig");
 
-    pub const IntRequest = IntEnable;
+    inline fn ipcFifoSync(sync: u32, value: anytype) u32 {
+        const _mask: u32 = 0x6F00;
+        return (@as(u32, value) & _mask) | (sync & ~_mask);
+    }
 
-    pub const PostFlag = enum(u8) { in_progress = 0, completed };
+    inline fn ipcFifoCnt(cnt: u32, value: anytype) u32 {
+        const _mask: u32 = 0xC40C;
+        const err_mask: u32 = 0x4000; // bit 14
+
+        const err_bit = (cnt & err_mask) & ~(value & err_mask);
+
+        const without_err = (@as(u32, value) & _mask) | (cnt & ~_mask);
+        return (without_err & ~err_mask) | err_bit;
+    }
+
+    /// General Mask helper
+    pub inline fn mask(original: anytype, value: @TypeOf(original), _mask: @TypeOf(original)) @TypeOf(original) {
+        return (value & _mask) | (original & ~_mask);
+    }
+};
+
+// FIXME: bitfields depends on NDS9 / NDS7
+pub const IntEnable = extern union {
+    vblank: Bit(u32, 0),
+    hblank: Bit(u32, 1),
+    coincidence: Bit(u32, 2),
+
+    dma0: Bit(u32, 8),
+    dma1: Bit(u32, 9),
+    dma2: Bit(u32, 10),
+    dma3: Bit(u32, 11),
+
+    ipcsync: Bit(u32, 16),
+    ipc_send_empty: Bit(u32, 17),
+    ipc_recv_not_empty: Bit(u32, 18),
+    raw: u32,
 };
 
 const Fifo = struct {
@@ -283,3 +396,71 @@ const Fifo = struct {
         return idx & _mask;
     }
 };
+
+/// Read Only
+/// 0 = Pressed, 1 = Released
+pub const KeyInput = extern union {
+    a: Bit(u16, 0),
+    b: Bit(u16, 1),
+    select: Bit(u16, 2),
+    start: Bit(u16, 3),
+    right: Bit(u16, 4),
+    left: Bit(u16, 5),
+    up: Bit(u16, 6),
+    down: Bit(u16, 7),
+    shoulder_r: Bit(u16, 8),
+    shoulder_l: Bit(u16, 9),
+    raw: u16,
+};
+
+pub const ExtKeyIn = extern union {
+    x: Bit(u16, 0),
+    y: Bit(u16, 1),
+    debug: Bit(u16, 3),
+    stylus: Bit(u16, 6),
+    hinge: Bit(u16, 7),
+    raw: u16,
+};
+
+const Input = struct {
+    const AtomicOrder = std.builtin.AtomicOrder;
+    const AtomicRmwOp = std.builtin.AtomicRmwOp;
+
+    inner: u32 = 0x007F_03FF,
+
+    pub inline fn keyinput(self: *const Input) KeyInput {
+        const value = @atomicLoad(u32, &self.inner, .monotonic);
+        return .{ .raw = @truncate(value) };
+    }
+
+    pub inline fn set_keyinput(self: *Input, comptime op: AtomicRmwOp, input: KeyInput) void {
+        const msked = switch (op) {
+            .And => 0xFFFF_FFFF & @as(u32, input.raw),
+            .Or => 0x0000_0000 | @as(u32, input.raw),
+            else => @compileError("not supported"),
+        };
+
+        _ = @atomicRmw(u32, &self.inner, op, msked, .monotonic);
+    }
+
+    pub inline fn extkeyin(self: *const Input) ExtKeyIn {
+        const value = @atomicLoad(u32, &self.inner, .monotonic);
+        const shifted: u16 = @truncate(value >> 16);
+
+        return .{ .raw = shifted | 0b00110100 }; // bits 2, 4, 5 are always set
+    }
+
+    pub inline fn set_extkeyin(self: *Input, comptime op: AtomicRmwOp, input: ExtKeyIn) void {
+        const msked = switch (op) {
+            .And => 0xFFFF_FFFF & (@as(u32, ~input.raw) << 16),
+            .Or => 0x0000_0000 | (@as(u32, input.raw) << 16),
+            else => @compileError("not supported"),
+        };
+
+        _ = @atomicRmw(u32, &self.inner, op, msked, .monotonic);
+    }
+
+    pub inline fn set(self: *Input, comptime op: AtomicRmwOp, value: u32) void {
+        _ = @atomicRmw(u32, &self.inner, op, value, .monotonic);
+    }
+};

src/core/nds7.zig

@@ -1,21 +0,0 @@
-const std = @import("std");
-
-pub const Bus = @import("nds7/Bus.zig");
-pub const io = @import("nds7/io.zig");
-pub const Scheduler = @import("nds7/Scheduler.zig");
-pub const Arm7tdmi = @import("arm32").Arm7tdmi;
-
-const Allocator = std.mem.Allocator;
-
-// TODO: Rename (maybe Devices?)
-pub const Group = struct {
-    cpu: *Arm7tdmi,
-    bus: *Bus,
-    scheduler: *Scheduler,
-
-    /// Responsible for deallocated the ARM7 CPU, Bus and Scheduler
-    pub fn deinit(self: @This(), allocator: Allocator) void {
-        self.bus.deinit(allocator);
-        self.scheduler.deinit();
-    }
-};

src/core/nds7/Bios.zig

@@ -0,0 +1,46 @@
+const std = @import("std");
+
+const Allocator = std.mem.Allocator;
+
+const log = std.log.scoped(.nds7_bios);
+
+const KiB = 0x400;
+const len = 16 * KiB;
+
+buf: ?*align(4) [len]u8 = null,
+
+// FIXME: Currently we dupe here, should we just take ownership?
+pub fn load(self: *@This(), allocator: Allocator, data: []u8) !void {
+    if (data.len != len) {
+        const acutal_size = @as(f32, @floatFromInt(data.len)) / KiB;
+        log.warn("BIOS was {d:.2} KiB (should be {} KiB)", .{ acutal_size, len });
+    }
+
+    const buf = try allocator.alignedAlloc(u8, 4, len);
+    @memset(buf, 0);
+    @memcpy(buf[0..data.len], data);
+
+    self.* = .{ .buf = buf[0..len] };
+}
+
+pub fn deinit(self: @This(), allocator: Allocator) void {
+    if (self.buf) |ptr| allocator.destroy(ptr);
+}
+
+// Note: Parts of 16MiB addrspace that aren't mapped to BIOS are typically undefined
+pub fn read(self: *const @This(), comptime T: type, address: u32) T {
+    const byte_count = @divExact(@typeInfo(T).Int.bits, 8);
+
+    // if (address >= len) return 0x0000_0000; // TODO: What is undefined actually?
+
+    const ptr = self.buf orelse {
+        log.err("read(T: {}, address: 0x{X:0>8}) from BIOS but none was found!", .{ T, address });
+        @panic("TODO: ability to load in NDS7 BIOS just-in-time");
+    };
+
+    return std.mem.readInt(T, ptr[address & (len - 1) ..][0..byte_count], .little);
+}
+
+pub fn write(_: *const @This(), comptime T: type, address: u32, value: T) void {
+    log.err("write(T: {}, address: 0x{X:0>8}, value: 0x{X:}) but we're in the BIOS!", .{ T, address, value });
+}

src/core/nds7/Bus.zig

@@ -1,11 +1,15 @@
 const std = @import("std");
 const io = @import("io.zig");
 
-const Scheduler = @import("Scheduler.zig");
-const SharedIo = @import("../io.zig").Io;
-const SharedContext = @import("../emu.zig").SharedContext;
+const Scheduler = @import("../Scheduler.zig");
+const SharedCtx = @import("../emu.zig").SharedCtx;
+const Wram = @import("../emu.zig").Wram;
+const Vram = @import("../ppu/Vram.zig");
+const Bios = @import("Bios.zig");
 const forceAlign = @import("../emu.zig").forceAlign;
 
+const Controllers = @import("dma.zig").Controllers;
+
 const Allocator = std.mem.Allocator;
 
 const Mode = enum { normal, debug };
@@ -16,24 +20,34 @@ const log = std.log.scoped(.nds7_bus);
 
 scheduler: *Scheduler,
 main: *[4 * MiB]u8,
+shr_wram: *Wram,
 wram: *[64 * KiB]u8,
-io: io.Io,
+vram: *Vram,
 
-pub fn init(allocator: Allocator, scheduler: *Scheduler, shared_ctx: SharedContext) !@This() {
+dma: Controllers = .{},
+
+io: io.Io,
+bios: Bios,
+
+pub fn init(allocator: Allocator, scheduler: *Scheduler, ctx: SharedCtx) !@This() {
     const wram = try allocator.create([64 * KiB]u8);
-    errdefer allocator.destroy(wram);
     @memset(wram, 0);
 
     return .{
-        .main = shared_ctx.main,
+        .main = ctx.main,
+        .shr_wram = ctx.wram,
+        .vram = ctx.vram,
         .wram = wram,
         .scheduler = scheduler,
-        .io = io.Io.init(shared_ctx.io),
+        .io = io.Io.init(ctx.io),
+
+        .bios = .{},
     };
 }
 
 pub fn deinit(self: *@This(), allocator: Allocator) void {
     allocator.destroy(self.wram);
+    self.bios.deinit(allocator);
 }
 
 pub fn reset(_: *@This()) void {}
@@ -48,8 +62,6 @@ pub fn dbgRead(self: *@This(), comptime T: type, address: u32) T {
 
 fn _read(self: *@This(), comptime T: type, comptime mode: Mode, address: u32) T {
     const byte_count = @divExact(@typeInfo(T).Int.bits, 8);
-    const readInt = std.mem.readIntLittle;
-
     const aligned_addr = forceAlign(T, address);
 
     switch (mode) {
@@ -59,10 +71,17 @@ fn _read(self: *@This(), comptime T: type, comptime mode: Mode, address: u32) T
     }
 
     return switch (aligned_addr) {
-        0x0200_0000...0x02FF_FFFF => readInt(T, self.main[aligned_addr & 0x003F_FFFF ..][0..byte_count]),
-        0x0380_0000...0x0380_FFFF => readInt(T, self.wram[aligned_addr & 0x0000_FFFF ..][0..byte_count]),
+        0x0000_0000...0x01FF_FFFF => self.bios.read(T, aligned_addr),
+        0x0200_0000...0x02FF_FFFF => std.mem.readInt(T, self.main[aligned_addr & 0x003F_FFFF ..][0..byte_count], .little),
+        0x0300_0000...0x037F_FFFF => switch (self.io.shr.wramcnt.mode.read()) {
+            0b00 => std.mem.readInt(T, self.wram[aligned_addr & 0x0000_FFFF ..][0..byte_count], .little),
+            else => self.shr_wram.read(T, .nds7, aligned_addr),
+        },
+        0x0380_0000...0x03FF_FFFF => std.mem.readInt(T, self.wram[aligned_addr & 0x0000_FFFF ..][0..byte_count], .little),
         0x0400_0000...0x04FF_FFFF => io.read(self, T, aligned_addr),
-        else => warn("unexpected read: 0x{x:0>8} -> {}", .{ aligned_addr, T }),
+        0x0600_0000...0x06FF_FFFF => self.vram.read(T, .nds7, aligned_addr),
+
+        else => warn("unexpected: read(T: {}, addr: 0x{X:0>8}) {} ", .{ T, address, T }),
     };
 }
 
@@ -76,7 +95,6 @@ pub fn dbgWrite(self: *@This(), comptime T: type, address: u32, value: T) void {
 
 fn _write(self: *@This(), comptime T: type, comptime mode: Mode, address: u32, value: T) void {
     const byte_count = @divExact(@typeInfo(T).Int.bits, 8);
-    const writeInt = std.mem.writeIntLittle;
 
     const aligned_addr = forceAlign(T, address);
 
@@ -87,10 +105,16 @@ fn _write(self: *@This(), comptime T: type, comptime mode: Mode, address: u32, v
     }
 
     switch (aligned_addr) {
-        0x0200_0000...0x02FF_FFFF => writeInt(T, self.main[aligned_addr & 0x003F_FFFF ..][0..byte_count], value),
-        0x0380_0000...0x0380_FFFF => writeInt(T, self.wram[aligned_addr & 0x0000_FFFF ..][0..byte_count], value),
+        0x0000_0000...0x01FF_FFFF => self.bios.write(T, aligned_addr, value),
+        0x0200_0000...0x02FF_FFFF => std.mem.writeInt(T, self.main[aligned_addr & 0x003F_FFFF ..][0..byte_count], value, .little),
+        0x0300_0000...0x037F_FFFF => switch (self.io.shr.wramcnt.mode.read()) {
+            0b00 => std.mem.writeInt(T, self.wram[aligned_addr & 0x0000_FFFF ..][0..byte_count], value, .little),
+            else => self.shr_wram.write(T, .nds7, aligned_addr, value),
+        },
+        0x0380_0000...0x03FF_FFFF => std.mem.writeInt(T, self.wram[aligned_addr & 0x0000_FFFF ..][0..byte_count], value, .little),
         0x0400_0000...0x04FF_FFFF => io.write(self, T, aligned_addr, value),
-        else => log.warn("unexpected write: 0x{X:}{} -> 0x{X:0>8}", .{ value, T, aligned_addr }),
+        0x0600_0000...0x06FF_FFFF => self.vram.write(T, .nds7, aligned_addr, value),
+        else => log.warn("unexpected: write(T: {}, addr: 0x{X:0>8}, value: 0x{X:0>8})", .{ T, address, value }),
     }
 }
 

src/core/nds7/Scheduler.zig

@@ -1,59 +0,0 @@
-const std = @import("std");
-
-const Bus = @import("Bus.zig");
-
-const PriorityQueue = std.PriorityQueue(Event, void, Event.lessThan);
-const Allocator = std.mem.Allocator;
-
-tick: u64 = 0,
-queue: PriorityQueue,
-
-pub fn init(allocator: Allocator) !@This() {
-    var queue = PriorityQueue.init(allocator, {});
-    try queue.add(.{ .tick = std.math.maxInt(u64), .kind = .heat_death });
-
-    return .{ .queue = queue };
-}
-
-pub fn push(self: *@This(), kind: Event.Kind, offset: u64) void {
-    self.queue.add(.{ .kind = kind, .tick = self.tick + offset }) catch unreachable;
-}
-
-pub fn deinit(self: @This()) void {
-    self.queue.deinit();
-}
-
-pub fn now(self: @This()) u64 {
-    return self.tick;
-}
-
-pub fn next(self: @This()) u64 {
-    @setRuntimeSafety(false);
-    return self.queue.items[0].tick;
-}
-
-pub fn reset(self: *@This()) void {
-    self.tick = 0;
-}
-
-pub fn handle(self: *@This(), bus: *Bus) void {
-    _ = bus;
-    const event = self.queue.remove();
-    const late = self.tick - event.tick;
-    _ = late;
-
-    switch (event.kind) {
-        .heat_death => unreachable,
-    }
-}
-
-pub const Event = struct {
-    tick: u64,
-    kind: Kind,
-
-    pub const Kind = enum { heat_death };
-
-    fn lessThan(_: void, left: @This(), right: @This()) std.math.Order {
-        return std.math.order(left.tick, right.tick);
-    }
-};

src/core/nds7/dma.zig

@@ -0,0 +1,401 @@
+const std = @import("std");
+
+const System = @import("../emu.zig").System;
+const DmaCnt = @import("io.zig").DmaCnt;
+
+const rotr = std.math.rotr;
+const shift = @import("../../util.zig").shift;
+const subset = @import("../../util.zig").subset;
+
+const handleInterrupt = @import("../emu.zig").handleInterrupt;
+
+const log = std.log.scoped(.nds7_dma_transfer);
+
+pub const Controllers = struct {
+    Controller(0) = Controller(0){},
+    Controller(1) = Controller(1){},
+    Controller(2) = Controller(2){},
+    Controller(3) = Controller(3){},
+};
+
+pub fn read(comptime T: type, dma: *const Controllers, addr: u32) ?T {
+    const byte_addr: u8 = @truncate(addr);
+
+    return switch (T) {
+        u32 => switch (byte_addr) {
+            0xB0, 0xB4 => null, // DMA0SAD, DMA0DAD,
+            0xB8 => @as(T, dma.*[0].dmacntH()) << 16, // DMA0CNT_L is write-only
+            0xBC, 0xC0 => null, // DMA1SAD, DMA1DAD
+            0xC4 => @as(T, dma.*[1].dmacntH()) << 16, // DMA1CNT_L is write-only
+            0xC8, 0xCC => null, // DMA2SAD, DMA2DAD
+            0xD0 => @as(T, dma.*[2].dmacntH()) << 16, // DMA2CNT_L is write-only
+            0xD4, 0xD8 => null, // DMA3SAD, DMA3DAD
+            0xDC => @as(T, dma.*[3].dmacntH()) << 16, // DMA3CNT_L is write-only
+            else => warn("unaligned {} read from 0x{X:0>8}", .{ T, addr }),
+        },
+        u16 => switch (byte_addr) {
+            0xB0, 0xB2, 0xB4, 0xB6 => null, // DMA0SAD, DMA0DAD
+            0xB8 => 0x0000, // DMA0CNT_L, suite.gba expects 0x0000 instead of 0xDEAD
+            0xBA => dma.*[0].dmacntH(),
+
+            0xBC, 0xBE, 0xC0, 0xC2 => null, // DMA1SAD, DMA1DAD
+            0xC4 => 0x0000, // DMA1CNT_L
+            0xC6 => dma.*[1].dmacntH(),
+
+            0xC8, 0xCA, 0xCC, 0xCE => null, // DMA2SAD, DMA2DAD
+            0xD0 => 0x0000, // DMA2CNT_L
+            0xD2 => dma.*[2].dmacntH(),
+
+            0xD4, 0xD6, 0xD8, 0xDA => null, // DMA3SAD, DMA3DAD
+            0xDC => 0x0000, // DMA3CNT_L
+            0xDE => dma.*[3].dmacntH(),
+            else => warn("unaligned {} read from 0x{X:0>8}", .{ T, addr }),
+        },
+        u8 => switch (byte_addr) {
+            0xB0...0xB7 => null, // DMA0SAD, DMA0DAD
+            0xB8, 0xB9 => 0x00, // DMA0CNT_L
+            0xBA, 0xBB => @truncate(dma.*[0].dmacntH() >> shift(u16, byte_addr)),
+
+            0xBC...0xC3 => null, // DMA1SAD, DMA1DAD
+            0xC4, 0xC5 => 0x00, // DMA1CNT_L
+            0xC6, 0xC7 => @truncate(dma.*[1].dmacntH() >> shift(u16, byte_addr)),
+
+            0xC8...0xCF => null, // DMA2SAD, DMA2DAD
+            0xD0, 0xD1 => 0x00, // DMA2CNT_L
+            0xD2, 0xD3 => @truncate(dma.*[2].dmacntH() >> shift(u16, byte_addr)),
+
+            0xD4...0xDB => null, // DMA3SAD, DMA3DAD
+            0xDC, 0xDD => 0x00, // DMA3CNT_L
+            0xDE, 0xDF => @truncate(dma.*[3].dmacntH() >> shift(u16, byte_addr)),
+            else => warn("unexpected {} read from 0x{X:0>8}", .{ T, addr }),
+        },
+        else => @compileError("DMA: Unsupported read width"),
+    };
+}
+
+pub fn write(comptime T: type, dma: *Controllers, addr: u32, value: T) void {
+    const byte_addr: u8 = @truncate(addr);
+
+    switch (T) {
+        u32 => switch (byte_addr) {
+            0xB0 => dma.*[0].setDmasad(value),
+            0xB4 => dma.*[0].setDmadad(value),
+            0xB8 => dma.*[0].setDmacnt(value),
+
+            0xBC => dma.*[1].setDmasad(value),
+            0xC0 => dma.*[1].setDmadad(value),
+            0xC4 => dma.*[1].setDmacnt(value),
+
+            0xC8 => dma.*[2].setDmasad(value),
+            0xCC => dma.*[2].setDmadad(value),
+            0xD0 => dma.*[2].setDmacnt(value),
+
+            0xD4 => dma.*[3].setDmasad(value),
+            0xD8 => dma.*[3].setDmadad(value),
+            0xDC => dma.*[3].setDmacnt(value),
+            else => log.warn("Tried to write 0x{X:0>8}{} to 0x{X:0>8}", .{ value, T, addr }),
+        },
+        u16 => switch (byte_addr) {
+            0xB0, 0xB2 => dma.*[0].setDmasad(subset(u32, u16, byte_addr, dma.*[0].sad, value)),
+            0xB4, 0xB6 => dma.*[0].setDmadad(subset(u32, u16, byte_addr, dma.*[0].dad, value)),
+            0xB8 => dma.*[0].setDmacntL(value),
+            0xBA => dma.*[0].setDmacntH(value),
+
+            0xBC, 0xBE => dma.*[1].setDmasad(subset(u32, u16, byte_addr, dma.*[1].sad, value)),
+            0xC0, 0xC2 => dma.*[1].setDmadad(subset(u32, u16, byte_addr, dma.*[1].dad, value)),
+            0xC4 => dma.*[1].setDmacntL(value),
+            0xC6 => dma.*[1].setDmacntH(value),
+
+            0xC8, 0xCA => dma.*[2].setDmasad(subset(u32, u16, byte_addr, dma.*[2].sad, value)),
+            0xCC, 0xCE => dma.*[2].setDmadad(subset(u32, u16, byte_addr, dma.*[2].dad, value)),
+            0xD0 => dma.*[2].setDmacntL(value),
+            0xD2 => dma.*[2].setDmacntH(value),
+
+            0xD4, 0xD6 => dma.*[3].setDmasad(subset(u32, u16, byte_addr, dma.*[3].sad, value)),
+            0xD8, 0xDA => dma.*[3].setDmadad(subset(u32, u16, byte_addr, dma.*[3].dad, value)),
+            0xDC => dma.*[3].setDmacntL(value),
+            0xDE => dma.*[3].setDmacntH(value),
+            else => log.warn("Tried to write 0x{X:0>4}{} to 0x{X:0>8}", .{ value, T, addr }),
+        },
+        u8 => switch (byte_addr) {
+            0xB0, 0xB1, 0xB2, 0xB3 => dma.*[0].setDmasad(subset(u32, u8, byte_addr, dma.*[0].sad, value)),
+            0xB4, 0xB5, 0xB6, 0xB7 => dma.*[0].setDmadad(subset(u32, u8, byte_addr, dma.*[0].dad, value)),
+            0xB8, 0xB9 => dma.*[0].setDmacntL(subset(u16, u8, byte_addr, dma.*[0].word_count, value)),
+            0xBA, 0xBB => dma.*[0].setDmacntH(subset(u16, u8, byte_addr, dma.*[0].cnt.raw, value)),
+
+            0xBC, 0xBD, 0xBE, 0xBF => dma.*[1].setDmasad(subset(u32, u8, byte_addr, dma.*[1].sad, value)),
+            0xC0, 0xC1, 0xC2, 0xC3 => dma.*[1].setDmadad(subset(u32, u8, byte_addr, dma.*[1].dad, value)),
+            0xC4, 0xC5 => dma.*[1].setDmacntL(subset(u16, u8, byte_addr, dma.*[1].word_count, value)),
+            0xC6, 0xC7 => dma.*[1].setDmacntH(subset(u16, u8, byte_addr, dma.*[1].cnt.raw, value)),
+
+            0xC8, 0xC9, 0xCA, 0xCB => dma.*[2].setDmasad(subset(u32, u8, byte_addr, dma.*[2].sad, value)),
+            0xCC, 0xCD, 0xCE, 0xCF => dma.*[2].setDmadad(subset(u32, u8, byte_addr, dma.*[2].dad, value)),
+            0xD0, 0xD1 => dma.*[2].setDmacntL(subset(u16, u8, byte_addr, dma.*[2].word_count, value)),
+            0xD2, 0xD3 => dma.*[2].setDmacntH(subset(u16, u8, byte_addr, dma.*[2].cnt.raw, value)),
+
+            0xD4, 0xD5, 0xD6, 0xD7 => dma.*[3].setDmasad(subset(u32, u8, byte_addr, dma.*[3].sad, value)),
+            0xD8, 0xD9, 0xDA, 0xDB => dma.*[3].setDmadad(subset(u32, u8, byte_addr, dma.*[3].dad, value)),
+            0xDC, 0xDD => dma.*[3].setDmacntL(subset(u16, u8, byte_addr, dma.*[3].word_count, value)),
+            0xDE, 0xDF => dma.*[3].setDmacntH(subset(u16, u8, byte_addr, dma.*[3].cnt.raw, value)),
+            else => log.warn("Tried to write 0x{X:0>2}{} to 0x{X:0>8}", .{ value, T, addr }),
+        },
+        else => @compileError("DMA: Unsupported write width"),
+    }
+}
+
+fn warn(comptime format: []const u8, args: anytype) u0 {
+    log.warn(format, args);
+    return 0;
+}
+
+/// Function that creates a DMAController. Determines unique DMA Controller behaiour at compile-time
+fn Controller(comptime id: u2) type {
+    return struct {
+        const Self = @This();
+
+        const sad_mask: u32 = if (id == 0) 0x07FF_FFFF else 0x0FFF_FFFF;
+        const dad_mask: u32 = if (id != 3) 0x07FF_FFFF else 0x0FFF_FFFF;
+        const WordCount = if (id == 3) u16 else u14;
+
+        /// Write-only. The first address in a DMA transfer. (DMASAD)
+        /// Note: use writeSrc instead of manipulating src_addr directly
+        sad: u32 = 0x0000_0000,
+        /// Write-only. The final address in a DMA transffer. (DMADAD)
+        /// Note: Use writeDst instead of manipulatig dst_addr directly
+        dad: u32 = 0x0000_0000,
+        /// Write-only. The Word Count for the DMA Transfer (DMACNT_L)
+        word_count: WordCount = 0,
+        /// Read / Write. DMACNT_H
+        /// Note: Use writeControl instead of manipulating cnt directly.
+        cnt: DmaCnt = .{ .raw = 0x0000 },
+
+        /// Internal. The last successfully read value
+        data_latch: u32 = 0x0000_0000,
+        /// Internal. Currrent Source Address
+        sad_latch: u32 = 0x0000_0000,
+        /// Internal. Current Destination Address
+        dad_latch: u32 = 0x0000_0000,
+        /// Internal. Word Count
+        _word_count: WordCount = 0,
+
+        /// Some DMA Transfers are enabled during Hblank / VBlank and / or
+        /// have delays. Thefore bit 15 of DMACNT isn't actually something
+        /// we can use to control when we do or do not execute a step in a DMA Transfer
+        in_progress: bool = false,
+
+        pub fn reset(self: *Self) void {
+            self.* = Self.init();
+        }
+
+        pub fn setDmasad(self: *Self, addr: u32) void {
+            self.sad = addr & sad_mask;
+        }
+
+        pub fn setDmadad(self: *Self, addr: u32) void {
+            self.dad = addr & dad_mask;
+        }
+
+        pub fn setDmacntL(self: *Self, halfword: u16) void {
+            self.word_count = @truncate(halfword);
+        }
+
+        pub fn dmacntH(self: *const Self) u16 {
+            return self.cnt.raw & if (id == 3) 0xFFE0 else 0xF7E0;
+        }
+
+        pub fn setDmacntH(self: *Self, halfword: u16) void {
+            const new = DmaCnt{ .raw = halfword };
+
+            if (!self.cnt.enabled.read() and new.enabled.read()) {
+                // Reload Internals on Rising Edge.
+                self.sad_latch = self.sad;
+                self.dad_latch = self.dad;
+                self._word_count = if (self.word_count == 0) std.math.maxInt(WordCount) else self.word_count;
+
+                // Only a Start Timing of 00 has a DMA Transfer immediately begin
+                self.in_progress = new.start_timing.read() == 0b00;
+
+                // this is just for debug purposes
+                const start_timing: Kind = @enumFromInt(new.start_timing.read());
+
+                switch (start_timing) {
+                    .immediate, .vblank => {},
+                    else => log.err("TODO: Implement DMA({}) {s} mode", .{ id, @tagName(start_timing) }),
+                }
+
+                // Debug stuff
+                {
+                    const sad_adj: Adjustment = @enumFromInt(new.sad_adj.read());
+                    const dad_adj: Adjustment = @enumFromInt(new.dad_adj.read());
+                    const byte_count = @as(u32, @sizeOf(u16)) << @intFromBool(new.transfer_type.read());
+
+                    const sad_final = switch (sad_adj) {
+                        .Increment, .IncrementReload => self.sad_latch +% self._word_count * byte_count,
+                        .Decrement => self.sad_latch -% self._word_count * byte_count,
+                        .Fixed => self.sad_latch,
+                    };
+
+                    const dad_final = switch (dad_adj) {
+                        .Increment, .IncrementReload => self.dad_latch +% self._word_count * byte_count,
+                        .Decrement => self.dad_latch -% self._word_count * byte_count,
+                        .Fixed => self.dad_latch,
+                    };
+
+                    log.debug("configured {s} transfer from 0x{X:0>8} -> 0x{X:0>8} to 0x{X:0>8} -> 0x{X:0>8} ({} words) for DMA{}", .{
+                        @tagName(start_timing),
+                        self.sad_latch,
+                        sad_final,
+                        self.dad_latch,
+                        dad_final,
+                        self._word_count,
+                        id,
+                    });
+                }
+            }
+
+            self.cnt.raw = halfword;
+        }
+
+        pub fn setDmacnt(self: *Self, word: u32) void {
+            self.setDmacntL(@truncate(word));
+            self.setDmacntH(@truncate(word >> 16));
+        }
+
+        pub fn step(self: *Self, cpu: *System.Arm7tdmi) void {
+            const bus_ptr: *System.Bus7 = @ptrCast(@alignCast(cpu.bus.ptr));
+
+            const is_fifo = (id == 1 or id == 2) and self.cnt.start_timing.read() == 0b11;
+            const sad_adj: Adjustment = @enumFromInt(self.cnt.sad_adj.read());
+            const dad_adj: Adjustment = if (is_fifo) .Fixed else @enumFromInt(self.cnt.dad_adj.read());
+
+            const transfer_type = is_fifo or self.cnt.transfer_type.read();
+            const offset: u32 = if (transfer_type) @sizeOf(u32) else @sizeOf(u16);
+
+            const mask = if (transfer_type) ~@as(u32, 3) else ~@as(u32, 1);
+            const sad_addr = self.sad_latch & mask;
+            const dad_addr = self.dad_latch & mask;
+
+            if (transfer_type) {
+                if (sad_addr >= 0x0200_0000) self.data_latch = cpu.bus.read(u32, sad_addr);
+                cpu.bus.write(u32, dad_addr, self.data_latch);
+            } else {
+                if (sad_addr >= 0x0200_0000) {
+                    const value: u32 = cpu.bus.read(u16, sad_addr);
+                    self.data_latch = value << 16 | value;
+                }
+
+                cpu.bus.write(u16, dad_addr, @as(u16, @truncate(rotr(u32, self.data_latch, 8 * (dad_addr & 3)))));
+            }
+
+            switch (@as(u8, @truncate(sad_addr >> 24))) {
+                // according to fleroviux, DMAs with a source address in ROM misbehave
+                // the resultant behaviour is that the source address will increment despite what DMAXCNT says
+                0x08...0x0D => self.sad_latch +%= offset, // obscure behaviour
+                else => switch (sad_adj) {
+                    .Increment => self.sad_latch +%= offset,
+                    .Decrement => self.sad_latch -%= offset,
+                    .IncrementReload => log.err("{} is a prohibited adjustment on SAD", .{sad_adj}),
+                    .Fixed => {},
+                },
+            }
+
+            switch (dad_adj) {
+                .Increment, .IncrementReload => self.dad_latch +%= offset,
+                .Decrement => self.dad_latch -%= offset,
+                .Fixed => {},
+            }
+
+            self._word_count -= 1;
+
+            if (self._word_count == 0) {
+                if (self.cnt.irq.read()) {
+                    switch (id) {
+                        0 => bus_ptr.io.irq.dma0.set(),
+                        1 => bus_ptr.io.irq.dma1.set(),
+                        2 => bus_ptr.io.irq.dma2.set(),
+                        3 => bus_ptr.io.irq.dma3.set(),
+                    }
+
+                    handleInterrupt(.nds7, cpu);
+                }
+
+                // If we're not repeating, Fire the IRQs and disable the DMA
+                if (!self.cnt.repeat.read()) self.cnt.enabled.unset();
+
+                // We want to disable our internal enabled flag regardless of repeat
+                // because we only want to step A DMA that repeats during it's specific
+                // timing window
+                self.in_progress = false;
+            }
+        }
+
+        fn poll(self: *Self, comptime kind: Kind) void {
+            if (self.in_progress) return; // If there's an ongoing DMA Transfer, exit early
+
+            // No ongoing DMA Transfer, We want to check if we should repeat an existing one
+            // Determined by the repeat bit and whether the DMA is in the right start_timing
+
+            switch (kind) {
+                .vblank => self.in_progress = self.cnt.enabled.read() and self.cnt.start_timing.read() == 0b01,
+                .cartridge_slot, .immediate, .special => {},
+            }
+
+            // If we determined that the repeat bit is set (and now the Hblank / Vblank DMA is now in progress)
+            // Reload internal word count latch
+            // Reload internal DAD latch if we are in IncrementRelaod
+            if (self.in_progress) {
+                self._word_count = if (self.word_count == 0) std.math.maxInt(@TypeOf(self._word_count)) else self.word_count;
+                if (@as(Adjustment, @enumFromInt(self.cnt.dad_adj.read())) == .IncrementReload) self.dad_latch = self.dad;
+            }
+        }
+
+        pub fn requestAudio(self: *Self, _: u32) void {
+            comptime std.debug.assert(id == 1 or id == 2);
+            if (self.in_progress) return; // APU must wait their turn
+
+            // DMA May not be configured for handling DMAs
+            if (self.cnt.start_timing.read() != 0b11) return;
+
+            // We Assume the Repeat Bit is Set
+            // We Assume that DAD is set to 0x0400_00A0 or 0x0400_00A4 (fifo_addr)
+            // We Assume DMACNT_L is set to 4
+
+            // FIXME: Safe to just assume whatever DAD is set to is the FIFO Address?
+            // self.dad_latch = fifo_addr;
+            self.cnt.repeat.set();
+            self._word_count = 4;
+            self.in_progress = true;
+        }
+    };
+}
+
+pub fn onVblank(bus: *System.Bus7) void {
+    inline for (0..4) |i| bus.dma[i].poll(.vblank);
+}
+
+pub fn step(cpu: *System.Arm7tdmi) bool {
+    const bus: *System.Bus7 = @ptrCast(@alignCast(cpu.bus.ptr));
+
+    inline for (0..4) |i| {
+        if (bus.dma[i].in_progress) {
+            bus.dma[i].step(cpu);
+            return true;
+        }
+    }
+
+    return false;
+}
+
+const Adjustment = enum(u2) {
+    Increment = 0,
+    Decrement = 1,
+    Fixed = 2,
+    IncrementReload = 3,
+};
+
+const Kind = enum(u2) {
+    immediate = 0,
+    vblank,
+    cartridge_slot,
+    special,
+};

src/core/nds7/io.zig

@@ -3,37 +3,99 @@ const std = @import("std");
 const Bitfield = @import("bitfield").Bitfield;
 const Bit = @import("bitfield").Bit;
 
+const Ppu = @import("../ppu.zig").Ppu;
+
 const Bus = @import("Bus.zig");
-const SharedIo = @import("../io.zig").Io;
-const writeToAddressOffset = @import("../io.zig").writeToAddressOffset;
-const valueAtAddressOffset = @import("../io.zig").valueAtAddressOffset;
+const SharedCtx = @import("../emu.zig").SharedCtx;
+const masks = @import("../io.zig").masks;
+
+const IntEnable = @import("../io.zig").IntEnable;
+const IntRequest = @import("../io.zig").IntEnable;
+
+const dma = @import("dma.zig");
 
 const log = std.log.scoped(.nds7_io);
 
 pub const Io = struct {
-    shared: *SharedIo,
+    shr: *SharedCtx.Io,
 
-    pub fn init(io: *SharedIo) @This() {
-        return .{ .shared = io };
+    /// IME - Interrupt Master Enable
+    /// Read/Write
+    ime: bool = false,
+
+    /// IE -  Interrupt Enable
+    /// Read/Write
+    ie: IntEnable = .{ .raw = 0x0000_0000 },
+
+    /// IF - Interrupt Request
+    /// Read/Write
+    irq: IntRequest = .{ .raw = 0x0000_0000 },
+
+    /// POSTFLG - Post Boot Flag
+    /// Read/Write
+    postflg: PostFlag = .in_progress,
+
+    /// HALTCNT - Low Power Mode Control
+    /// Read/Write
+    haltcnt: Haltcnt = .execute,
+
+    ppu: ?*Ppu.Io = null,
+
+    pub fn init(io: *SharedCtx.Io) @This() {
+        return .{ .shr = io };
+    }
+
+    pub fn configure(self: *@This(), ppu: *Ppu) void {
+        self.ppu = &ppu.io;
     }
 };
 
 pub fn read(bus: *const Bus, comptime T: type, address: u32) T {
     return switch (T) {
         u32 => switch (address) {
-            0x0400_0208 => @intFromBool(bus.io.shared.ime),
-            0x0400_0210 => bus.io.shared.ie,
-            0x0400_0214 => bus.io.shared.irq,
+            // DMA Transfers
+            0x0400_00B0...0x0400_00DC => dma.read(T, &bus.dma, address) orelse 0x000_0000,
 
-            0x0410_0000 => bus.io.shared.ipc_fifo.recv(.arm7),
+            // Timers
+            0x0400_0100...0x0400_010C => warn("TODO(timer): read(T: {}, addr: 0x{X:0>8}) {}", .{ T, address, T }),
+
+            0x0400_0180 => bus.io.shr.ipc._nds7.sync.raw,
+            0x0400_0208 => @intFromBool(bus.io.ime),
+            0x0400_0210 => bus.io.ie.raw,
+            0x0400_0214 => bus.io.irq.raw,
+
+            0x0410_0000 => bus.io.shr.ipc.recv(.nds7),
             else => warn("unexpected: read(T: {}, addr: 0x{X:0>8}) {} ", .{ T, address, T }),
         },
         u16 => switch (address) {
-            0x0400_0180 => @truncate(bus.io.shared.ipc_fifo.sync.raw),
-            0x0400_0184 => @truncate(bus.io.shared.ipc_fifo.cnt.raw),
+            0x0400_0004 => bus.io.ppu.?.nds7.dispstat.raw,
+            // DMA Transfers
+            0x0400_00B0...0x0400_00DE => dma.read(T, &bus.dma, address) orelse 0x0000,
+
+            // Timers
+            0x0400_0100...0x0400_010E => warn("TODO(timer): read(T: {}, addr: 0x{X:0>8}) {}", .{ T, address, T }),
+
+            0x0400_0130 => bus.io.shr.input.keyinput().raw,
+            0x0400_0136 => bus.io.shr.input.extkeyin().raw,
+
+            0x0400_0180 => @truncate(bus.io.shr.ipc._nds7.sync.raw),
+            0x0400_0184 => @truncate(bus.io.shr.ipc._nds7.cnt.raw),
             else => warn("unexpected: read(T: {}, addr: 0x{X:0>8}) {} ", .{ T, address, T }),
         },
         u8 => switch (address) {
+            // DMA Transfers
+            0x0400_00B0...0x0400_00DF => dma.read(T, &bus.dma, address) orelse 0x00,
+
+            // Timers
+            0x0400_0100...0x0400_010F => warn("TODO(timer): read(T: {}, addr: 0x{X:0>8}) {}", .{ T, address, T }),
+
+            // RTC
+            0x0400_0138 => warn("TODO(rtc): read(T: {}, addr: 0x{X:0>8}) {}", .{ T, address, T }),
+
+            0x0400_0240 => bus.vram.stat().raw,
+            0x0400_0241 => bus.io.shr.wramcnt.raw,
+
+            0x0400_0300 => @intFromEnum(bus.io.postflg),
             else => warn("unexpected: read(T: {}, addr: 0x{X:0>8}) {} ", .{ T, address, T }),
         },
         else => @compileError(T ++ " is an unsupported bus read type"),
@@ -43,25 +105,56 @@ pub fn read(bus: *const Bus, comptime T: type, address: u32) T {
 pub fn write(bus: *Bus, comptime T: type, address: u32, value: T) void {
     switch (T) {
         u32 => switch (address) {
-            0x0400_0208 => bus.io.shared.ime = value & 1 == 1,
-            0x0400_0210 => bus.io.shared.ie = value,
-            0x0400_0214 => bus.io.shared.irq = value,
+            // DMA Transfers
+            0x0400_00B0...0x0400_00DC => dma.write(T, &bus.dma, address, value),
 
-            0x0400_0188 => bus.io.shared.ipc_fifo.send(.arm7, value) catch |e| std.debug.panic("FIFO error: {}", .{e}),
+            // Timers
+            0x0400_0100...0x0400_010C => log.warn("TODO(timer): write(T: {}, addr: 0x{X:0>8}, value: 0x{X:0>8})", .{ T, address, value }),
+
+            0x0400_0180 => bus.io.shr.ipc.setIpcSync(.nds7, value),
+            0x0400_0208 => bus.io.ime = value & 1 == 1,
+            0x0400_0210 => bus.io.ie.raw = value,
+            0x0400_0214 => bus.io.irq.raw &= ~value,
+
+            0x0400_0188 => bus.io.shr.ipc.send(.nds7, value),
             else => log.warn("unexpected: write(T: {}, addr: 0x{X:0>8}, value: 0x{X:0>8})", .{ T, address, value }),
         },
         u16 => switch (address) {
-            0x0400_0180 => bus.io.shared.ipc_fifo.sync.raw = blk: {
-                const ret = value & ~@as(u16, 0xF) | (bus.io.shared.ipc_fifo.sync.raw & 0xF);
-                log.debug("IPCFIFOSYNC <- 0x{X:0>8}", .{ret});
+            0x0400_0004 => bus.io.ppu.?.nds7.dispstat.raw = value,
 
-                break :blk ret;
-            },
-            0x0400_0184 => bus.io.shared.ipc_fifo.cnt.raw = value,
-            else => log.warn("unexpected: write(T: {}, addr: 0x{X:0>8}, value: 0x{X:0>8})", .{ T, address, value }),
+            // DMA Transfers
+            0x0400_00B0...0x0400_00DE => dma.write(T, &bus.dma, address, value),
+
+            // Timers
+            0x0400_0100...0x0400_010E => log.warn("TODO(timer): write(T: {}, addr: 0x{X:0>8}, value: 0x{X:0>8})", .{ T, address, value }),
+
+            0x0400_0180 => bus.io.shr.ipc.setIpcSync(.nds7, value),
+            0x0400_0184 => bus.io.shr.ipc.setIpcFifoCnt(.nds7, value),
+
+            0x0400_0208 => bus.io.ime = value & 1 == 1,
+            else => log.warn("unexpected: write(T: {}, addr: 0x{X:0>8}, value: 0x{X:0>4})", .{ T, address, value }),
         },
         u8 => switch (address) {
-            else => log.warn("unexpected: write(T: {}, addr: 0x{X:0>8}, value: 0x{X:0>8})", .{ T, address, value }),
+            // DMA Transfers
+            0x0400_00B0...0x0400_00DF => dma.write(T, &bus.dma, address, value),
+
+            // Timers
+            0x0400_0100...0x0400_010F => log.warn("TODO(timer): write(T: {}, addr: 0x{X:0>8}, value: 0x{X:0>8})", .{ T, address, value }),
+
+            // RTC
+            0x0400_0138 => log.warn("TODO(rtc): write(T: {}, addr: 0x{X:0>8}, value: 0x{X:0>8})", .{ T, address, value }),
+
+            0x0400_0208 => bus.io.ime = value & 1 == 1,
+
+            0x0400_0301 => switch ((value >> 6) & 0b11) {
+                0b00 => bus.io.haltcnt = .execute,
+                0b10 => bus.io.haltcnt = .halt,
+                else => |val| {
+                    const tag: Haltcnt = @enumFromInt(val);
+                    log.err("TODO: Implement {}", .{tag});
+                },
+            },
+            else => log.warn("unexpected: write(T: {}, addr: 0x{X:0>8}, value: 0x{X:0>2})", .{ T, address, value }),
         },
         else => @compileError(T ++ " is an unsupported bus write type"),
     }
@@ -71,3 +164,29 @@ fn warn(comptime format: []const u8, args: anytype) u0 {
     log.warn(format, args);
     return 0;
 }
+
+pub const Vramstat = extern union {
+    vramc_enabled: Bit(u8, 0),
+    vramd_enabled: Bit(u8, 1),
+    raw: u8,
+};
+
+const Haltcnt = enum(u2) {
+    execute = 0,
+    gba_mode,
+    halt,
+    sleep,
+};
+
+const PostFlag = enum(u8) { in_progress = 0, completed };
+
+pub const DmaCnt = extern union {
+    dad_adj: Bitfield(u16, 5, 2),
+    sad_adj: Bitfield(u16, 7, 2),
+    repeat: Bit(u16, 9),
+    transfer_type: Bit(u16, 10),
+    start_timing: Bitfield(u16, 12, 2),
+    irq: Bit(u16, 14),
+    enabled: Bit(u16, 15),
+    raw: u16,
+};

src/core/nds9.zig

@@ -1,22 +0,0 @@
-const std = @import("std");
-
-pub const Bus = @import("nds9/Bus.zig");
-pub const Cp15 = @import("nds9/Cp15.zig");
-pub const io = @import("nds9/io.zig");
-pub const Scheduler = @import("nds9/Scheduler.zig");
-pub const Arm946es = @import("arm32").Arm946es;
-
-const Allocator = std.mem.Allocator;
-
-// TODO: Rename
-pub const Group = struct {
-    cpu: *Arm946es,
-    bus: *Bus,
-    scheduler: *Scheduler,
-
-    /// Responsible for deallocating the ARM9 CPU, Bus and Scheduler
-    pub fn deinit(self: @This(), allocator: Allocator) void {
-        self.bus.deinit(allocator);
-        self.scheduler.deinit();
-    }
-};

src/core/nds9/Bios.zig

@@ -0,0 +1,48 @@
+const std = @import("std");
+
+const Allocator = std.mem.Allocator;
+
+const log = std.log.scoped(.nds7_bios);
+
+const KiB = 0x400;
+
+const _len = 4 * KiB; // real size of the NDS9 BIOS
+const len = 32 * KiB; // size allocated to NDS9 BIOS
+
+buf: ?*align(4) [len]u8 = null,
+
+// FIXME: Currently we dupe here, should we just take ownership?
+pub fn load(self: *@This(), allocator: Allocator, data: []u8) !void {
+    if (data.len != _len) {
+        const acutal_size = @as(f32, @floatFromInt(data.len)) / KiB;
+        log.warn("BIOS was {d:.2} KiB (should be {} KiB)", .{ acutal_size, len });
+    }
+
+    const buf = try allocator.alignedAlloc(u8, 4, len);
+    @memcpy(buf[0..data.len], data);
+    @memset(buf[data.len..], 0);
+
+    self.* = .{ .buf = buf[0..len] };
+}
+
+pub fn deinit(self: @This(), allocator: Allocator) void {
+    if (self.buf) |ptr| allocator.destroy(ptr);
+}
+
+// Note: Parts of 16MiB addrspace that aren't mapped to BIOS are typically undefined
+pub fn read(self: *const @This(), comptime T: type, address: u32) T {
+    const byte_count = @divExact(@typeInfo(T).Int.bits, 8);
+
+    // if (address >= len) return 0x0000_0000; // TODO: What is undefined actually?
+
+    const ptr = self.buf orelse {
+        log.err("read(T: {}, address: 0x{X:0>8}) from BIOS but none was found!", .{ T, address });
+        @panic("TODO: ability to load in NDS9 BIOS just-in-time");
+    };
+
+    return std.mem.readInt(T, ptr[address & (len - 1) ..][0..byte_count], .little);
+}
+
+pub fn write(_: *const @This(), comptime T: type, address: u32, value: T) void {
+    log.err("write(T: {}, address: 0x{X:0>8}, value: 0x{X:}) but we're in the BIOS!", .{ T, address, value });
+}

src/core/nds9/Bus.zig

@@ -2,10 +2,14 @@ const std = @import("std");
 const io = @import("io.zig");
 
 const Ppu = @import("../ppu.zig").Ppu;
-const Scheduler = @import("Scheduler.zig");
-const SharedContext = @import("../emu.zig").SharedContext;
+const Scheduler = @import("../Scheduler.zig");
+const SharedCtx = @import("../emu.zig").SharedCtx;
+const Wram = @import("../emu.zig").Wram;
+const Bios = @import("Bios.zig");
 const forceAlign = @import("../emu.zig").forceAlign;
 
+const Controllers = @import("dma.zig").Controllers;
+
 const Allocator = std.mem.Allocator;
 
 const Mode = enum { normal, debug };
@@ -15,38 +19,41 @@ const KiB = 0x400;
 const log = std.log.scoped(.nds9_bus);
 
 main: *[4 * MiB]u8,
-vram1: *[512 * KiB]u8, // TODO: Rename
-io: io.Io,
-ppu: Ppu,
-
+wram: *Wram,
+makeshift_palram: *[2 * KiB]u8,
 scheduler: *Scheduler,
 
-pub fn init(allocator: Allocator, scheduler: *Scheduler, shared_ctx: SharedContext) !@This() {
-    const vram1_mem = try allocator.create([512 * KiB]u8);
-    errdefer allocator.destroy(vram1_mem);
-    @memset(vram1_mem, 0);
+dma: Controllers = .{},
 
+io: io.Io,
+ppu: Ppu,
+bios: Bios,
+
+pub fn init(allocator: Allocator, scheduler: *Scheduler, ctx: SharedCtx) !@This() {
     const dots_per_cycle = 3; // ARM946E-S runs twice as fast as the ARM7TDMI
-    scheduler.push(.draw, 256 * dots_per_cycle);
+    scheduler.push(.{ .nds9 = .draw }, 256 * dots_per_cycle);
 
     return .{
-        .main = shared_ctx.main,
-        .vram1 = vram1_mem,
-        .ppu = try Ppu.init(allocator),
+        .main = ctx.main,
+        .wram = ctx.wram,
+        .makeshift_palram = try allocator.create([2 * KiB]u8),
+        .ppu = try Ppu.init(allocator, ctx.vram),
         .scheduler = scheduler,
-        .io = io.Io.init(shared_ctx.io),
+        .io = io.Io.init(ctx.io),
+
+        .bios = .{},
     };
 }
 
 pub fn deinit(self: *@This(), allocator: Allocator) void {
     self.ppu.deinit(allocator);
+    self.bios.deinit(allocator);
 
-    allocator.destroy(self.vram1);
+    allocator.destroy(self.makeshift_palram);
 }
 
-pub fn reset(self: *@This()) void {
-    @memset(self.main, 0);
-    @memset(self.vram1, 0);
+pub fn reset(_: *@This()) void {
+    @panic("TODO: PPU Reset");
 }
 
 pub fn read(self: *@This(), comptime T: type, address: u32) T {
@@ -59,8 +66,6 @@ pub fn dbgRead(self: *@This(), comptime T: type, address: u32) T {
 
 fn _read(self: *@This(), comptime T: type, comptime mode: Mode, address: u32) T {
     const byte_count = @divExact(@typeInfo(T).Int.bits, 8);
-    const readInt = std.mem.readIntLittle;
-
     const aligned_addr = forceAlign(T, address);
 
     switch (mode) {
@@ -70,10 +75,14 @@ fn _read(self: *@This(), comptime T: type, comptime mode: Mode, address: u32) T
     }
 
     return switch (aligned_addr) {
-        0x0200_0000...0x02FF_FFFF => readInt(T, self.main[aligned_addr & 0x003F_FFFF ..][0..byte_count]),
+        0x0200_0000...0x02FF_FFFF => std.mem.readInt(T, self.main[aligned_addr & (4 * MiB - 1) ..][0..byte_count], .little),
+        0x0300_0000...0x03FF_FFFF => self.wram.read(T, .nds9, aligned_addr),
         0x0400_0000...0x04FF_FFFF => io.read(self, T, aligned_addr),
-        0x0600_0000...0x06FF_FFFF => readInt(T, self.vram1[aligned_addr & 0x0007_FFFF ..][0..byte_count]),
-        else => warn("unexpected read: 0x{x:0>8} -> {}", .{ aligned_addr, T }),
+        0x0500_0000...0x05FF_FFFF => std.mem.readInt(T, self.makeshift_palram[aligned_addr & (2 * KiB - 1) ..][0..@sizeOf(T)], .little),
+        0x0600_0000...0x06FF_FFFF => self.ppu.vram.read(T, .nds9, aligned_addr),
+        0x0700_0000...0x07FF_FFFF => std.mem.readInt(T, self.ppu.oam.buf[aligned_addr & (2 * KiB - 1) ..][0..byte_count], .little),
+        0xFFFF_0000...0xFFFF_FFFF => self.bios.read(T, aligned_addr),
+        else => warn("unexpected: read(T: {}, addr: 0x{X:0>8}) {} ", .{ T, address, T }),
     };
 }
 
@@ -87,8 +96,6 @@ pub fn dbgWrite(self: *@This(), comptime T: type, address: u32, value: T) void {
 
 fn _write(self: *@This(), comptime T: type, comptime mode: Mode, address: u32, value: T) void {
     const byte_count = @divExact(@typeInfo(T).Int.bits, 8);
-    const writeInt = std.mem.writeIntLittle;
-
     const aligned_addr = forceAlign(T, address);
 
     switch (mode) {
@@ -98,10 +105,14 @@ fn _write(self: *@This(), comptime T: type, comptime mode: Mode, address: u32, v
     }
 
     switch (aligned_addr) {
-        0x0200_0000...0x02FF_FFFF => writeInt(T, self.main[aligned_addr & 0x003F_FFFF ..][0..byte_count], value),
+        0x0200_0000...0x02FF_FFFF => std.mem.writeInt(T, self.main[aligned_addr & (4 * MiB - 1) ..][0..byte_count], value, .little),
+        0x0300_0000...0x03FF_FFFF => self.wram.write(T, .nds9, aligned_addr, value),
         0x0400_0000...0x04FF_FFFF => io.write(self, T, aligned_addr, value),
-        0x0600_0000...0x06FF_FFFF => writeInt(T, self.vram1[aligned_addr & 0x0007_FFFF ..][0..byte_count], value),
-        else => log.warn("unexpected write: 0x{X:}{} -> 0x{X:0>8}", .{ value, T, aligned_addr }),
+        0x0500_0000...0x05FF_FFFF => std.mem.writeInt(T, self.makeshift_palram[aligned_addr & (2 * KiB - 1) ..][0..@sizeOf(T)], value, .little),
+        0x0600_0000...0x06FF_FFFF => self.ppu.vram.write(T, .nds9, aligned_addr, value),
+        0x0700_0000...0x07FF_FFFF => std.mem.writeInt(T, self.ppu.oam.buf[aligned_addr & (2 * KiB - 1) ..][0..@sizeOf(T)], value, .little),
+        0xFFFF_0000...0xFFFF_FFFF => self.bios.write(T, aligned_addr, value),
+        else => log.warn("unexpected: write(T: {}, addr: 0x{X:0>8}, value: 0x{X:0>8})", .{ T, address, value }),
     }
 }
 

src/core/nds9/Cp15.zig

@@ -2,10 +2,14 @@ const std = @import("std");
 
 const log = std.log.scoped(.cp15);
 
-control: u32 = 0x0005_2078,
+const panic_on_unimplemented: bool = false;
+
+control: u32 = 0x0001_2078,
 dtcm_size_base: u32 = 0x0300_000A,
 itcm_size_base: u32 = 0x0000_0020,
 
+wait_for_interrupt: bool = false,
+
 // Protection Unit
 // cache_bits_data_unified: u32 = 0x0000_0000,
 // cache_write_bufability: u32 = 0x0000_0000, // For Data Protection Regions
@@ -41,22 +45,57 @@ pub fn write(self: *@This(), op1: u3, cn: u4, cm: u4, op2: u3, value: u32) void
 
             self.control = (value & ~zeroes) | ones;
         },
+
+        0b000_0010_0000_000 => log.err("TODO: write to PU cachability bits (data/unified region)", .{}),
+        0b000_0010_0000_001 => log.err("TODO: write to PU cachability bits (instruction region)", .{}),
+        0b000_0011_0000_000 => log.err("TODO: write to PU cache write-bufferability bits (data protection region)", .{}),
+
+        0b000_0101_0000_000 => log.err("TODO: write to access permission protection region (data/unified)", .{}),
+        0b000_0101_0000_001 => log.err("TODO: write to access permission protection region (insruction)", .{}),
+        0b000_0101_0000_010 => log.err("TODO: write to extended access permission protection region (data/unified)", .{}),
+        0b000_0101_0000_011 => log.err("TODO: write to extended access permission protection region (insruction)", .{}),
+
+        0b000_0110_0000_000,
+        0b000_0110_0001_000,
+        0b000_0110_0010_000,
+        0b000_0110_0011_000,
+        0b000_0110_0100_000,
+        0b000_0110_0101_000,
+        0b000_0110_0110_000,
+        0b000_0110_0111_000,
+        => log.err("TODO: write to PU data/unified region #{}", .{cm}),
+
+        0b000_0110_0000_001,
+        0b000_0110_0001_001,
+        0b000_0110_0010_001,
+        0b000_0110_0011_001,
+        0b000_0110_0100_001,
+        0b000_0110_0101_001,
+        0b000_0110_0110_001,
+        0b000_0110_0111_001,
+        => log.err("TODO: write to PU instruction region #{}", .{cm}),
+
+        0b000_0111_0000_100 => self.wait_for_interrupt = true, // NDS9 Halt
+        0b000_0111_0101_000 => log.err("TODO: invalidate instruction cache", .{}),
+        0b000_0111_0110_000 => log.err("TODO: invalidate data cache", .{}),
+        0b000_0111_1010_100 => log.err("TODO: drain write buffer", .{}),
+
         0b000_1001_0001_000 => { // Data TCM Size / Base
             const zeroes: u32 = 0b00000000_00000000_00001111_11000001;
 
             self.dtcm_size_base = value & ~zeroes;
 
-            const size_shamt: u5 = blk: {
-                const size = self.dtcm_size_base >> 1 & 0x1F;
+            // const size_shamt: u5 = blk: {
+            //     const size = self.dtcm_size_base >> 1 & 0x1F;
 
-                if (size < 3) break :blk 3;
-                if (size > 23) break :blk 23;
+            //     if (size < 3) break :blk 3;
+            //     if (size > 23) break :blk 23;
 
-                break :blk @intCast(size);
-            };
+            //     break :blk @intCast(size);
+            // };
 
-            log.debug("DTCM Virtual Size: {}B", .{@as(u32, 0x200) << size_shamt});
-            log.debug("DTCM Region Base: 0x{X:0>8}", .{self.dtcm_size_base & 0xFFFF_F000});
+            // log.debug("DTCM Virtual Size: {}B", .{@as(u32, 0x200) << size_shamt});
+            // log.debug("DTCM Region Base: 0x{X:0>8}", .{self.dtcm_size_base & 0xFFFF_F000});
         },
         0b000_1001_0001_001 => { // Instruction TCM Size / Base
             const zeroes: u32 = 0b00000000_00000000_00001111_11000001;
@@ -64,18 +103,19 @@ pub fn write(self: *@This(), op1: u3, cn: u4, cm: u4, op2: u3, value: u32) void
 
             self.itcm_size_base = value & ~(zeroes | itcm_specific);
 
-            const size_shamt: u5 = blk: {
-                const size = self.dtcm_size_base >> 1 & 0x1F;
+            // const size_shamt: u5 = blk: {
+            //     const size = self.dtcm_size_base >> 1 & 0x1F;
 
-                if (size < 3) break :blk 3;
-                if (size > 23) break :blk 23;
+            //     if (size < 3) break :blk 3;
+            //     if (size > 23) break :blk 23;
 
-                break :blk @intCast(size);
-            };
+            //     break :blk @intCast(size);
+            // };
 
-            log.debug("ICTM Virtual Size: {}B", .{@as(u32, 0x200) << size_shamt});
-            log.debug("ICTM Region Base: 0x{X:0>8}", .{0x0000_0000});
+            // log.debug("ICTM Virtual Size: {}B", .{@as(u32, 0x200) << size_shamt});
+            // log.debug("ICTM Region Base: 0x{X:0>8}", .{0x0000_0000});
         },
+
         else => _ = panic("TODO: implement write to register {}, c{}, c{}, {}", .{ op1, cn, cm, op2 }),
     }
 }
@@ -97,6 +137,7 @@ pub fn reset(self: *@This()) void {
 
 fn panic(comptime format: []const u8, args: anytype) u32 {
     log.err(format, args);
-    // @panic("Coprocessor invariant broken");
+    if (panic_on_unimplemented) @panic("cp15 invariant broken");
+
     return 0;
 }

src/core/nds9/Scheduler.zig

@@ -1,69 +0,0 @@
-const std = @import("std");
-
-const Bus = @import("Bus.zig");
-
-const PriorityQueue = std.PriorityQueue(Event, void, Event.lessThan);
-const Allocator = std.mem.Allocator;
-
-tick: u64 = 0,
-queue: PriorityQueue,
-
-pub fn init(allocator: Allocator) !@This() {
-    var queue = PriorityQueue.init(allocator, {});
-    try queue.add(.{ .tick = std.math.maxInt(u64), .kind = .heat_death });
-
-    return .{ .queue = queue };
-}
-
-pub fn push(self: *@This(), kind: Event.Kind, offset: u64) void {
-    self.queue.add(.{ .kind = kind, .tick = self.tick + offset }) catch unreachable;
-}
-
-pub fn deinit(self: @This()) void {
-    self.queue.deinit();
-}
-
-pub fn now(self: @This()) u64 {
-    return self.tick;
-}
-
-pub fn next(self: @This()) u64 {
-    @setRuntimeSafety(false);
-
-    return self.queue.items[0].tick;
-}
-
-pub fn reset(self: *@This()) void {
-    self.tick = 0;
-}
-
-pub fn handle(self: *@This(), bus: *Bus) void {
-    const event = self.queue.remove();
-    const late = self.tick - event.tick;
-
-    switch (event.kind) {
-        .heat_death => unreachable,
-        .draw => {
-            bus.ppu.drawScanline(bus);
-            bus.ppu.onHdrawEnd(self, late);
-        },
-        .hblank => bus.ppu.onHblankEnd(self, late),
-        .vblank => bus.ppu.onHblankEnd(self, late),
-    }
-}
-
-pub const Event = struct {
-    tick: u64,
-    kind: Kind,
-
-    pub const Kind = enum {
-        heat_death,
-        draw,
-        hblank,
-        vblank,
-    };
-
-    fn lessThan(_: void, left: @This(), right: @This()) std.math.Order {
-        return std.math.order(left.tick, right.tick);
-    }
-};

src/core/nds9/dma.zig

@@ -0,0 +1,411 @@
+const std = @import("std");
+
+const System = @import("../emu.zig").System;
+const DmaCnt = @import("io.zig").DmaCnt;
+
+const rotr = std.math.rotr;
+const shift = @import("../../util.zig").shift;
+const subset = @import("../../util.zig").subset;
+
+const handleInterrupt = @import("../emu.zig").handleInterrupt;
+
+const log = std.log.scoped(.nds9_dma_transfer);
+
+pub const Controllers = struct {
+    Controller(0) = Controller(0){},
+    Controller(1) = Controller(1){},
+    Controller(2) = Controller(2){},
+    Controller(3) = Controller(3){},
+};
+
+pub fn read(comptime T: type, dma: *const Controllers, addr: u32) ?T {
+    const byte_addr: u8 = @truncate(addr);
+
+    return switch (T) {
+        u32 => switch (byte_addr) {
+            0xB0, 0xB4 => null, // DMA0SAD, DMA0DAD,
+            0xB8 => @as(T, dma.*[0].dmacntH()) << 16, // DMA0CNT_L is write-only
+            0xBC, 0xC0 => null, // DMA1SAD, DMA1DAD
+            0xC4 => @as(T, dma.*[1].dmacntH()) << 16, // DMA1CNT_L is write-only
+            0xC8, 0xCC => null, // DMA2SAD, DMA2DAD
+            0xD0 => @as(T, dma.*[2].dmacntH()) << 16, // DMA2CNT_L is write-only
+            0xD4, 0xD8 => null, // DMA3SAD, DMA3DAD
+            0xDC => @as(T, dma.*[3].dmacntH()) << 16, // DMA3CNT_L is write-only
+            else => warn("unaligned {} read from 0x{X:0>8}", .{ T, addr }),
+        },
+        u16 => switch (byte_addr) {
+            0xB0, 0xB2, 0xB4, 0xB6 => null, // DMA0SAD, DMA0DAD
+            0xB8 => 0x0000, // DMA0CNT_L, suite.gba expects 0x0000 instead of 0xDEAD
+            0xBA => dma.*[0].dmacntH(),
+
+            0xBC, 0xBE, 0xC0, 0xC2 => null, // DMA1SAD, DMA1DAD
+            0xC4 => 0x0000, // DMA1CNT_L
+            0xC6 => dma.*[1].dmacntH(),
+
+            0xC8, 0xCA, 0xCC, 0xCE => null, // DMA2SAD, DMA2DAD
+            0xD0 => 0x0000, // DMA2CNT_L
+            0xD2 => dma.*[2].dmacntH(),
+
+            0xD4, 0xD6, 0xD8, 0xDA => null, // DMA3SAD, DMA3DAD
+            0xDC => 0x0000, // DMA3CNT_L
+            0xDE => dma.*[3].dmacntH(),
+            else => warn("unaligned {} read from 0x{X:0>8}", .{ T, addr }),
+        },
+        u8 => switch (byte_addr) {
+            0xB0...0xB7 => null, // DMA0SAD, DMA0DAD
+            0xB8, 0xB9 => 0x00, // DMA0CNT_L
+            0xBA, 0xBB => @truncate(dma.*[0].dmacntH() >> shift(u16, byte_addr)),
+
+            0xBC...0xC3 => null, // DMA1SAD, DMA1DAD
+            0xC4, 0xC5 => 0x00, // DMA1CNT_L
+            0xC6, 0xC7 => @truncate(dma.*[1].dmacntH() >> shift(u16, byte_addr)),
+
+            0xC8...0xCF => null, // DMA2SAD, DMA2DAD
+            0xD0, 0xD1 => 0x00, // DMA2CNT_L
+            0xD2, 0xD3 => @truncate(dma.*[2].dmacntH() >> shift(u16, byte_addr)),
+
+            0xD4...0xDB => null, // DMA3SAD, DMA3DAD
+            0xDC, 0xDD => 0x00, // DMA3CNT_L
+            0xDE, 0xDF => @truncate(dma.*[3].dmacntH() >> shift(u16, byte_addr)),
+            else => warn("unexpected {} read from 0x{X:0>8}", .{ T, addr }),
+        },
+        else => @compileError("DMA: Unsupported read width"),
+    };
+}
+
+pub fn write(comptime T: type, dma: *Controllers, addr: u32, value: T) void {
+    const byte_addr: u8 = @truncate(addr);
+
+    switch (T) {
+        u32 => switch (byte_addr) {
+            0xB0 => dma.*[0].setDmasad(value),
+            0xB4 => dma.*[0].setDmadad(value),
+            0xB8 => dma.*[0].setDmacnt(value),
+
+            0xBC => dma.*[1].setDmasad(value),
+            0xC0 => dma.*[1].setDmadad(value),
+            0xC4 => dma.*[1].setDmacnt(value),
+
+            0xC8 => dma.*[2].setDmasad(value),
+            0xCC => dma.*[2].setDmadad(value),
+            0xD0 => dma.*[2].setDmacnt(value),
+
+            0xD4 => dma.*[3].setDmasad(value),
+            0xD8 => dma.*[3].setDmadad(value),
+            0xDC => dma.*[3].setDmacnt(value),
+            else => log.warn("Tried to write 0x{X:0>8}{} to 0x{X:0>8}", .{ value, T, addr }),
+        },
+        u16 => switch (byte_addr) {
+            0xB0, 0xB2 => dma.*[0].setDmasad(subset(u32, u16, byte_addr, dma.*[0].sad, value)),
+            0xB4, 0xB6 => dma.*[0].setDmadad(subset(u32, u16, byte_addr, dma.*[0].dad, value)),
+            0xB8 => dma.*[0].setDmacntL(value),
+            0xBA => dma.*[0].setDmacntH(value),
+
+            0xBC, 0xBE => dma.*[1].setDmasad(subset(u32, u16, byte_addr, dma.*[1].sad, value)),
+            0xC0, 0xC2 => dma.*[1].setDmadad(subset(u32, u16, byte_addr, dma.*[1].dad, value)),
+            0xC4 => dma.*[1].setDmacntL(value),
+            0xC6 => dma.*[1].setDmacntH(value),
+
+            0xC8, 0xCA => dma.*[2].setDmasad(subset(u32, u16, byte_addr, dma.*[2].sad, value)),
+            0xCC, 0xCE => dma.*[2].setDmadad(subset(u32, u16, byte_addr, dma.*[2].dad, value)),
+            0xD0 => dma.*[2].setDmacntL(value),
+            0xD2 => dma.*[2].setDmacntH(value),
+
+            0xD4, 0xD6 => dma.*[3].setDmasad(subset(u32, u16, byte_addr, dma.*[3].sad, value)),
+            0xD8, 0xDA => dma.*[3].setDmadad(subset(u32, u16, byte_addr, dma.*[3].dad, value)),
+            0xDC => dma.*[3].setDmacntL(value),
+            0xDE => dma.*[3].setDmacntH(value),
+            else => log.warn("Tried to write 0x{X:0>4}{} to 0x{X:0>8}", .{ value, T, addr }),
+        },
+        u8 => switch (byte_addr) {
+            0xB0, 0xB1, 0xB2, 0xB3 => dma.*[0].setDmasad(subset(u32, u8, byte_addr, dma.*[0].sad, value)),
+            0xB4, 0xB5, 0xB6, 0xB7 => dma.*[0].setDmadad(subset(u32, u8, byte_addr, dma.*[0].dad, value)),
+            0xB8, 0xB9 => dma.*[0].setDmacntL(subset(u16, u8, byte_addr, @as(u16, @truncate(dma.*[0].word_count)), value)), // FIXME: How wrong is this? lol
+            0xBA, 0xBB => dma.*[0].setDmacntH(subset(u16, u8, byte_addr, dma.*[0].cnt.raw, value)),
+
+            0xBC, 0xBD, 0xBE, 0xBF => dma.*[1].setDmasad(subset(u32, u8, byte_addr, dma.*[1].sad, value)),
+            0xC0, 0xC1, 0xC2, 0xC3 => dma.*[1].setDmadad(subset(u32, u8, byte_addr, dma.*[1].dad, value)),
+            0xC4, 0xC5 => dma.*[1].setDmacntL(subset(u16, u8, byte_addr, @as(u16, @truncate(dma.*[1].word_count)), value)),
+            0xC6, 0xC7 => dma.*[1].setDmacntH(subset(u16, u8, byte_addr, dma.*[1].cnt.raw, value)),
+
+            0xC8, 0xC9, 0xCA, 0xCB => dma.*[2].setDmasad(subset(u32, u8, byte_addr, dma.*[2].sad, value)),
+            0xCC, 0xCD, 0xCE, 0xCF => dma.*[2].setDmadad(subset(u32, u8, byte_addr, dma.*[2].dad, value)),
+            0xD0, 0xD1 => dma.*[2].setDmacntL(subset(u16, u8, byte_addr, @as(u16, @truncate(dma.*[2].word_count)), value)),
+            0xD2, 0xD3 => dma.*[2].setDmacntH(subset(u16, u8, byte_addr, dma.*[2].cnt.raw, value)),
+
+            0xD4, 0xD5, 0xD6, 0xD7 => dma.*[3].setDmasad(subset(u32, u8, byte_addr, dma.*[3].sad, value)),
+            0xD8, 0xD9, 0xDA, 0xDB => dma.*[3].setDmadad(subset(u32, u8, byte_addr, dma.*[3].dad, value)),
+            0xDC, 0xDD => dma.*[3].setDmacntL(subset(u16, u8, byte_addr, @as(u16, @truncate(dma.*[3].word_count)), value)),
+            0xDE, 0xDF => dma.*[3].setDmacntH(subset(u16, u8, byte_addr, dma.*[3].cnt.raw, value)),
+            else => log.warn("Tried to write 0x{X:0>2}{} to 0x{X:0>8}", .{ value, T, addr }),
+        },
+        else => @compileError("DMA: Unsupported write width"),
+    }
+}
+
+fn warn(comptime format: []const u8, args: anytype) u0 {
+    log.warn(format, args);
+    return 0;
+}
+
+/// Function that creates a DMAController. Determines unique DMA Controller behaiour at compile-time
+fn Controller(comptime id: u2) type {
+    return struct {
+        const Self = @This();
+
+        const sad_mask: u32 = 0x0FFF_FFFE;
+        const dad_mask: u32 = 0x0FFF_FFFE;
+        const WordCount = u21;
+
+        /// Write-only. The first address in a DMA transfer. (DMASAD)
+        /// Note: use writeSrc instead of manipulating src_addr directly
+        sad: u32 = 0x0000_0000,
+        /// Write-only. The final address in a DMA transffer. (DMADAD)
+        /// Note: Use writeDst instead of manipulatig dst_addr directly
+        dad: u32 = 0x0000_0000,
+        /// Write-only. The Word Count for the DMA Transfer (DMACNT_L)
+        word_count: WordCount = 0,
+        /// Read / Write. DMACNT_H
+        /// Note: Use writeControl instead of manipulating cnt directly.
+        cnt: DmaCnt = .{ .raw = 0x0000 },
+
+        /// Internal. The last successfully read value
+        data_latch: u32 = 0x0000_0000,
+        /// Internal. Currrent Source Address
+        sad_latch: u32 = 0x0000_0000,
+        /// Internal. Current Destination Address
+        dad_latch: u32 = 0x0000_0000,
+        /// Internal. Word Count
+        _word_count: WordCount = 0,
+
+        /// Some DMA Transfers are enabled during Hblank / VBlank and / or
+        /// have delays. Thefore bit 15 of DMACNT isn't actually something
+        /// we can use to control when we do or do not execute a step in a DMA Transfer
+        in_progress: bool = false,
+
+        pub fn reset(self: *Self) void {
+            self.* = Self.init();
+        }
+
+        pub fn setDmasad(self: *Self, addr: u32) void {
+            self.sad = addr & sad_mask;
+        }
+
+        pub fn setDmadad(self: *Self, addr: u32) void {
+            self.dad = addr & dad_mask;
+        }
+
+        pub fn setDmacntL(self: *Self, halfword: u16) void {
+            self.word_count = halfword;
+        }
+
+        pub fn dmacntH(self: *const Self) u16 {
+            return self.cnt.raw & if (id == 3) 0xFFE0 else 0xF7E0;
+        }
+
+        pub fn setDmacntH(self: *Self, halfword: u16) void {
+            const new = DmaCnt{ .raw = halfword };
+
+            if (!self.cnt.enabled.read() and new.enabled.read()) {
+                // Reload Internals on Rising Edge.
+                self.sad_latch = self.sad;
+                self.dad_latch = self.dad;
+                self._word_count = if (self.word_count == 0) std.math.maxInt(WordCount) else self.word_count;
+
+                // Only a Start Timing of 00 has a DMA Transfer immediately begin
+                self.in_progress = new.start_timing.read() == 0b00;
+
+                // this is just for debug purposes
+                const start_timing: Kind = @enumFromInt(new.start_timing.read());
+
+                switch (start_timing) {
+                    .immediate, .vblank, .hblank => {},
+                    else => log.err("TODO: Implement DMA({}) {s} mode", .{ id, @tagName(start_timing) }),
+                }
+
+                // Debug stuff
+                {
+                    const sad_adj: Adjustment = @enumFromInt(new.sad_adj.read());
+                    const dad_adj: Adjustment = @enumFromInt(new.dad_adj.read());
+                    const byte_count = @as(u32, @sizeOf(u16)) << @intFromBool(new.transfer_type.read());
+
+                    const sad_final = switch (sad_adj) {
+                        .Increment, .IncrementReload => self.sad_latch +% self._word_count * byte_count,
+                        .Decrement => self.sad_latch -% self._word_count * byte_count,
+                        .Fixed => self.sad_latch,
+                    };
+
+                    const dad_final = switch (dad_adj) {
+                        .Increment, .IncrementReload => self.dad_latch +% self._word_count * byte_count,
+                        .Decrement => self.dad_latch -% self._word_count * byte_count,
+                        .Fixed => self.dad_latch,
+                    };
+
+                    log.debug("configured {s} transfer from 0x{X:0>8} -> 0x{X:0>8} to 0x{X:0>8} -> 0x{X:0>8} ({} words) for DMA{}", .{
+                        @tagName(start_timing),
+                        self.sad_latch,
+                        sad_final,
+                        self.dad_latch,
+                        dad_final,
+                        self._word_count,
+                        id,
+                    });
+                }
+            }
+
+            self.cnt.raw = halfword;
+        }
+
+        pub fn setDmacnt(self: *Self, word: u32) void {
+            self.setDmacntL(@truncate(word));
+            self.setDmacntH(@truncate(word >> 16));
+        }
+
+        pub fn step(self: *Self, cpu: *System.Arm946es) void {
+            const bus_ptr: *System.Bus9 = @ptrCast(@alignCast(cpu.bus.ptr));
+
+            const is_fifo = (id == 1 or id == 2) and self.cnt.start_timing.read() == 0b11;
+            const sad_adj: Adjustment = @enumFromInt(self.cnt.sad_adj.read());
+            const dad_adj: Adjustment = if (is_fifo) .Fixed else @enumFromInt(self.cnt.dad_adj.read());
+
+            const transfer_type = is_fifo or self.cnt.transfer_type.read();
+            const offset: u32 = if (transfer_type) @sizeOf(u32) else @sizeOf(u16);
+
+            const mask = if (transfer_type) ~@as(u32, 3) else ~@as(u32, 1);
+            const sad_addr = self.sad_latch & mask;
+            const dad_addr = self.dad_latch & mask;
+
+            if (transfer_type) {
+                if (sad_addr >= 0x0200_0000) self.data_latch = cpu.bus.read(u32, sad_addr);
+                cpu.bus.write(u32, dad_addr, self.data_latch);
+            } else {
+                if (sad_addr >= 0x0200_0000) {
+                    const value: u32 = cpu.bus.read(u16, sad_addr);
+                    self.data_latch = value << 16 | value;
+                }
+
+                cpu.bus.write(u16, dad_addr, @as(u16, @truncate(rotr(u32, self.data_latch, 8 * (dad_addr & 3)))));
+            }
+
+            switch (@as(u8, @truncate(sad_addr >> 24))) {
+                // according to fleroviux, DMAs with a source address in ROM misbehave
+                // the resultant behaviour is that the source address will increment despite what DMAXCNT says
+                0x08...0x0D => self.sad_latch +%= offset, // obscure behaviour
+                else => switch (sad_adj) {
+                    .Increment => self.sad_latch +%= offset,
+                    .Decrement => self.sad_latch -%= offset,
+                    .IncrementReload => log.err("{} is a prohibited adjustment on SAD", .{sad_adj}),
+                    .Fixed => {},
+                },
+            }
+
+            switch (dad_adj) {
+                .Increment, .IncrementReload => self.dad_latch +%= offset,
+                .Decrement => self.dad_latch -%= offset,
+                .Fixed => {},
+            }
+
+            self._word_count -= 1;
+
+            if (self._word_count == 0) {
+                if (self.cnt.irq.read()) {
+                    switch (id) {
+                        0 => bus_ptr.io.irq.dma0.set(),
+                        1 => bus_ptr.io.irq.dma1.set(),
+                        2 => bus_ptr.io.irq.dma2.set(),
+                        3 => bus_ptr.io.irq.dma3.set(),
+                    }
+
+                    handleInterrupt(.nds9, cpu);
+                }
+
+                // If we're not repeating, Fire the IRQs and disable the DMA
+                if (!self.cnt.repeat.read()) self.cnt.enabled.unset();
+
+                // We want to disable our internal enabled flag regardless of repeat
+                // because we only want to step A DMA that repeats during it's specific
+                // timing window
+                self.in_progress = false;
+            }
+        }
+
+        fn poll(self: *Self, comptime kind: Kind) void {
+            if (self.in_progress) return; // If there's an ongoing DMA Transfer, exit early
+
+            // No ongoing DMA Transfer, We want to check if we should repeat an existing one
+            // Determined by the repeat bit and whether the DMA is in the right start_timing
+
+            switch (kind) {
+                .vblank => self.in_progress = self.cnt.enabled.read() and self.cnt.start_timing.read() == 0b01,
+                .hblank => self.in_progress = self.cnt.enabled.read() and self.cnt.start_timing.read() == 0b10,
+                else => {},
+            }
+
+            // If we determined that the repeat bit is set (and now the Hblank / Vblank DMA is now in progress)
+            // Reload internal word count latch
+            // Reload internal DAD latch if we are in IncrementRelaod
+            if (self.in_progress) {
+                self._word_count = if (self.word_count == 0) std.math.maxInt(@TypeOf(self._word_count)) else self.word_count;
+                if (@as(Adjustment, @enumFromInt(self.cnt.dad_adj.read())) == .IncrementReload) self.dad_latch = self.dad;
+            }
+        }
+
+        pub fn requestAudio(self: *Self, _: u32) void {
+            comptime std.debug.assert(id == 1 or id == 2);
+            if (self.in_progress) return; // APU must wait their turn
+
+            // DMA May not be configured for handling DMAs
+            if (self.cnt.start_timing.read() != 0b11) return;
+
+            // We Assume the Repeat Bit is Set
+            // We Assume that DAD is set to 0x0400_00A0 or 0x0400_00A4 (fifo_addr)
+            // We Assume DMACNT_L is set to 4
+
+            // FIXME: Safe to just assume whatever DAD is set to is the FIFO Address?
+            // self.dad_latch = fifo_addr;
+            self.cnt.repeat.set();
+            self._word_count = 4;
+            self.in_progress = true;
+        }
+    };
+}
+
+pub fn onVblank(bus: *System.Bus9) void {
+    inline for (0..4) |i| bus.dma[i].poll(.vblank);
+}
+
+pub fn onHblank(bus: *System.Bus9) void {
+    inline for (0..4) |i| bus.dma[i].poll(.hblank);
+}
+
+pub fn step(cpu: *System.Arm946es) bool {
+    const bus: *System.Bus9 = @ptrCast(@alignCast(cpu.bus.ptr));
+
+    inline for (0..4) |i| {
+        if (bus.dma[i].in_progress) {
+            bus.dma[i].step(cpu);
+            return true;
+        }
+    }
+
+    return false;
+}
+
+const Adjustment = enum(u2) {
+    Increment = 0,
+    Decrement = 1,
+    Fixed = 2,
+    IncrementReload = 3,
+};
+
+const Kind = enum(u3) {
+    immediate = 0,
+    vblank,
+    hblank,
+
+    display_start_sync,
+    main_mem_display,
+    cartridge_slot,
+    pak_slot,
+    geo_cmd_fifo,
+};

src/core/nds9/io.zig

@@ -4,99 +4,353 @@ const Bitfield = @import("bitfield").Bitfield;
 const Bit = @import("bitfield").Bit;
 
 const Bus = @import("Bus.zig");
-const SharedIo = @import("../io.zig").Io;
-const writeToAddressOffset = @import("../io.zig").writeToAddressOffset;
-const valueAtAddressOffset = @import("../io.zig").valueAtAddressOffset;
+const SharedCtx = @import("../emu.zig").SharedCtx;
+const masks = @import("../io.zig").masks;
+
+const IntEnable = @import("../io.zig").IntEnable;
+const IntRequest = @import("../io.zig").IntEnable;
+
+const dma = @import("dma.zig");
+
+const sext = @import("../../util.zig").sext;
+const shift = @import("../../util.zig").shift;
 
 const log = std.log.scoped(.nds9_io);
 
 pub const Io = struct {
-    shared: *SharedIo,
+    const fill_len = 0x10 * @sizeOf(u32);
 
-    /// POWCNT1 - Graphics Power Control
-    /// Read / Write
-    powcnt: PowCnt = .{ .raw = 0x0000_0000 },
+    shr: *SharedCtx.Io,
 
-    // Read Only
-    keyinput: AtomicKeyInput = .{},
+    /// Interrupt Master Enable
+    /// Read/Write
+    ime: bool = false,
 
-    pub fn init(io: *SharedIo) @This() {
-        return .{ .shared = io };
+    /// Interrupt Enable
+    /// Read/Write
+    ///
+    /// Caller must cast the `u32` to either `nds7.IntEnable` or `nds9.IntEnable`
+    ie: IntEnable = .{ .raw = 0x0000_0000 },
+
+    /// IF - Interrupt Request
+    /// Read/Write
+    ///
+    /// Caller must cast the `u32` to either `nds7.IntRequest` or `nds9.IntRequest`
+    irq: IntRequest = .{ .raw = 0x0000_0000 },
+
+    /// DS Maths
+    div: Divisor = .{},
+    sqrt: SquareRootUnit = .{},
+
+    // TODO: move somewhere else?
+    dma_fill: [fill_len]u8 = [_]u8{0} ** fill_len,
+
+    pub fn init(io: *SharedCtx.Io) @This() {
+        return .{ .shr = io };
     }
 };
 
 pub fn read(bus: *const Bus, comptime T: type, address: u32) T {
     return switch (T) {
         u32 => switch (address) {
-            0x0400_0208 => @intFromBool(bus.io.shared.ime),
-            0x0400_0210 => bus.io.shared.ie,
-            0x0400_0214 => bus.io.shared.irq,
+            // DMA Transfers
+            0x0400_00B0...0x0400_00DC => dma.read(T, &bus.dma, address) orelse 0x0000_0000,
+            0x0400_00E0...0x0400_00EC => std.mem.readInt(T, bus.io.dma_fill[address & 0xF ..][0..@sizeOf(T)], .little),
 
-            0x0410_0000 => bus.io.shared.ipc_fifo.recv(.arm9),
+            // Timers
+            0x0400_0100...0x0400_010C => warn("TODO(timer): read(T: {}, addr: 0x{X:0>8}) {} ", .{ T, address, T }),
+
+            0x0400_0180 => bus.io.shr.ipc._nds9.sync.raw,
+            0x0400_0208 => @intFromBool(bus.io.ime),
+            0x0400_0210 => bus.io.ie.raw,
+            0x0400_0214 => bus.io.irq.raw,
+
+            // zig fmt: off
+            0x0400_0240 => @as(u32, bus.ppu.vram.io.cnt_d.raw) << 24
+                | @as(u32, bus.ppu.vram.io.cnt_c.raw) << 16
+                | @as(u32, bus.ppu.vram.io.cnt_b.raw) << 8
+                | bus.ppu.vram.io.cnt_a.raw << 0,
+            // zig fmt: on
+
+            0x0400_0280 => bus.io.div.cnt.raw,
+            0x0400_02A0, 0x0400_02A4 => @truncate(bus.io.div.result >> shift(u64, address)),
+            0x0400_02A8, 0x0400_02AC => @truncate(bus.io.div.remainder >> shift(u64, address)),
+            0x0400_02B4 => @truncate(bus.io.sqrt.result),
+
+            0x0400_1000 => bus.ppu.engines[1].dispcnt.raw,
+
+            0x0410_0000 => bus.io.shr.ipc.recv(.nds9),
+
+            0x0400_4000, 0x0400_4008 => 0x0000_0000, // Lets software know this is NOT a DSi
             else => warn("unexpected: read(T: {}, addr: 0x{X:0>8}) {} ", .{ T, address, T }),
         },
         u16 => switch (address) {
-            0x0400_0004 => bus.ppu.io.dispstat.raw,
-            0x0400_0130 => bus.io.keyinput.load(.Monotonic),
+            0x0400_0006 => bus.ppu.io.nds9.vcount.raw,
+
+            // DMA Transfers
+            0x0400_00B0...0x0400_00DE => dma.read(T, &bus.dma, address) orelse 0x0000,
+            0x0400_00E0...0x0400_00EE => std.mem.readInt(T, bus.io.dma_fill[address & 0xF ..][0..@sizeOf(T)], .little),
+
+            // Timers
+            0x0400_0100...0x0400_010E => warn("TODO(timer): read(T: {}, addr: 0x{X:0>8}) {} ", .{ T, address, T }),
+
+            0x0400_0004 => bus.ppu.io.nds9.dispstat.raw,
+            0x0400_0130 => bus.io.shr.input.keyinput().raw,
+
+            0x0400_0180 => @truncate(bus.io.shr.ipc._nds9.sync.raw),
+            0x0400_0184 => @truncate(bus.io.shr.ipc._nds9.cnt.raw),
+
+            0x0400_0280 => @truncate(bus.io.div.cnt.raw),
+            0x0400_02B0 => @truncate(bus.io.sqrt.cnt.raw),
+
+            0x0400_1008 => bus.ppu.engines[1].bg[0].cnt.raw,
+            0x0400_100A => bus.ppu.engines[1].bg[1].cnt.raw,
+            0x0400_100C => bus.ppu.engines[1].bg[2].cnt.raw,
+            0x0400_100E => bus.ppu.engines[1].bg[3].cnt.raw,
+
+            0x0400_1010 => bus.ppu.engines[1].bg[0].hofs.raw,
+            0x0400_1012 => bus.ppu.engines[1].bg[0].vofs.raw,
+            0x0400_1014 => bus.ppu.engines[1].bg[1].hofs.raw,
+            0x0400_1016 => bus.ppu.engines[1].bg[1].vofs.raw,
+            0x0400_1018 => bus.ppu.engines[1].bg[2].hofs.raw,
+            0x0400_101A => bus.ppu.engines[1].bg[2].vofs.raw,
+            0x0400_101C => bus.ppu.engines[1].bg[3].hofs.raw,
+            0x0400_101E => bus.ppu.engines[1].bg[3].vofs.raw,
 
-            0x0400_0180 => @truncate(bus.io.shared.ipc_fifo.sync.raw),
-            0x0400_0184 => @truncate(bus.io.shared.ipc_fifo.cnt.raw),
             else => warn("unexpected: read(T: {}, addr: 0x{X:0>8}) {} ", .{ T, address, T }),
         },
         u8 => switch (address) {
+            // DMA Transfers
+            0x0400_00B0...0x0400_00DF => dma.read(T, &bus.dma, address) orelse 0x00,
+            0x0400_00E0...0x0400_00EF => std.mem.readInt(T, bus.io.dma_fill[address & 0xF ..][0..@sizeOf(T)], .little),
+
+            // Timers
+            0x0400_0100...0x0400_010F => warn("TODO(timer): read(T: {}, addr: 0x{X:0>8}) {} ", .{ T, address, T }),
+
+            0x0400_0208 => @intFromBool(bus.io.ime),
+
+            0x0400_4000 => 0x00, // Lets software know this is NOT a DSi
             else => warn("unexpected: read(T: {}, addr: 0x{X:0>8}) {} ", .{ T, address, T }),
         },
         else => @compileError(T ++ " is an unsupported bus read type"),
     };
 }
 
+const subset = @import("../../util.zig").subset;
+
 pub fn write(bus: *Bus, comptime T: type, address: u32, value: T) void {
     switch (T) {
         u32 => switch (address) {
-            0x0400_0000 => bus.ppu.io.dispcnt_a.raw = value,
-            0x0400_0180 => bus.io.shared.ipc_fifo.sync.raw = blk: {
-                const ret = value & ~@as(u32, 0xF) | (bus.io.shared.ipc_fifo.sync.raw & 0xF);
-                log.debug("IPCFIFOSYNC <- 0x{X:0>8}", .{ret});
-
-                break :blk ret;
+            0x0400_0000 => bus.ppu.engines[0].dispcnt.raw = value,
+            0x0400_0004 => bus.ppu.io.nds9.dispstat.raw = @truncate(value),
+            0x0400_0008 => {
+                bus.ppu.engines[0].bg[0].cnt.raw = @truncate(value >> 0); // 0x0400_0008
+                bus.ppu.engines[0].bg[1].cnt.raw = @truncate(value >> 16); // 0x0400_000A
             },
-            0x0400_0184 => bus.io.shared.ipc_fifo.cnt.raw = value,
-            0x0400_0188 => bus.io.shared.ipc_fifo.send(.arm9, value) catch |e| std.debug.panic("IPC FIFO Error: {}", .{e}),
+            0x0400_000C => {
+                bus.ppu.engines[0].bg[2].cnt.raw = @truncate(value >> 0); // 0x0400_000A
+                bus.ppu.engines[0].bg[3].cnt.raw = @truncate(value >> 16); // 0x0400_000C
+            },
+            0x00400_0010 => {
+                bus.ppu.engines[0].bg[0].hofs.raw = @truncate(value >> 0); // 0x0400_0010
+                bus.ppu.engines[0].bg[0].vofs.raw = @truncate(value >> 16); // 0x0400_0012
+            },
+            0x00400_0014 => {
+                bus.ppu.engines[0].bg[1].hofs.raw = @truncate(value >> 0); // 0x0400_0014
+                bus.ppu.engines[0].bg[1].vofs.raw = @truncate(value >> 16); // 0x0400_0016
+            },
+            0x00400_0018 => {
+                bus.ppu.engines[0].bg[2].hofs.raw = @truncate(value >> 0); // 0x0400_0018
+                bus.ppu.engines[0].bg[2].vofs.raw = @truncate(value >> 16); // 0x0400_001A
+            },
+            0x00400_001C => {
+                bus.ppu.engines[0].bg[3].hofs.raw = @truncate(value >> 0); // 0x0400_001C
+                bus.ppu.engines[0].bg[3].vofs.raw = @truncate(value >> 16); // 0x0400_001E
+            },
+
+            // DMA Transfers
+            0x0400_00B0...0x0400_00DC => dma.write(T, &bus.dma, address, value),
+            0x0400_00E0...0x0400_00EC => std.mem.writeInt(T, bus.io.dma_fill[address & 0xF ..][0..@sizeOf(T)], value, .little),
+
+            // Timers
+            0x0400_0100...0x0400_010C => log.warn("TODO(timer): write(T: {}, addr: 0x{X:0>8}, value: 0x{X:0>8})", .{ T, address, value }),
+
+            0x0400_0180 => bus.io.shr.ipc.setIpcSync(.nds9, value),
+            0x0400_0184 => bus.io.shr.ipc.setIpcFifoCnt(.nds9, value),
+            0x0400_0188 => bus.io.shr.ipc.send(.nds9, value),
+
+            0x0400_0208 => bus.io.ime = value & 1 == 1,
+            0x0400_0210 => bus.io.ie.raw = value,
+            0x0400_0214 => bus.io.irq.raw &= ~value,
 
             0x0400_0240 => {
-                bus.ppu.io.vramcnt_a.raw = @truncate(value >> 0); // 0x0400_0240
-                bus.ppu.io.vramcnt_b.raw = @truncate(value >> 8); // 0x0400_0241
-                bus.ppu.io.vramcnt_c.raw = @truncate(value >> 16); // 0x0400_0242
-                bus.ppu.io.vramcnt_d.raw = @truncate(value >> 24); // 0x0400_0243
+                bus.ppu.vram.io.cnt_a.raw = @truncate(value >> 0); // 0x0400_0240
+                bus.ppu.vram.io.cnt_b.raw = @truncate(value >> 8); // 0x0400_0241
+                bus.ppu.vram.io.cnt_c.raw = @truncate(value >> 16); // 0x0400_0242
+                bus.ppu.vram.io.cnt_d.raw = @truncate(value >> 24); // 0x0400_0243
+
+                bus.ppu.vram.update();
+            },
+            0x0400_0244 => {
+                bus.ppu.vram.io.cnt_e.raw = @truncate(value >> 0); // 0x0400_0244
+                bus.ppu.vram.io.cnt_f.raw = @truncate(value >> 8); // 0x0400_0245
+                bus.ppu.vram.io.cnt_g.raw = @truncate(value >> 16); // 0x0400_0246
+                bus.io.shr.wramcnt.raw = @truncate(value >> 24); // 0x0400_0247
+
+                bus.ppu.vram.update();
+                bus.wram.update(bus.io.shr.wramcnt);
             },
 
-            0x0400_0208 => bus.io.shared.ime = value & 1 == 1,
-            0x0400_0210 => bus.io.shared.ie = value,
-            0x0400_0214 => bus.io.shared.irq = value,
+            0x0400_0280 => {
+                bus.io.div.cnt.raw = value;
+                bus.io.div.schedule(bus.scheduler);
+            },
 
-            0x0400_0304 => bus.io.powcnt.raw = value,
+            0x0400_0290, 0x0400_0294 => {
+                bus.io.div.numerator = subset(u64, u32, address, bus.io.div.numerator, value);
+                bus.io.div.schedule(bus.scheduler);
+            },
+
+            0x0400_0298, 0x0400_029C => {
+                bus.io.div.denominator = subset(u64, u32, address, bus.io.div.denominator, value);
+                bus.io.div.schedule(bus.scheduler);
+            },
+
+            0x0400_02B0 => {
+                bus.io.sqrt.cnt.raw = value;
+                bus.io.sqrt.schedule(bus.scheduler);
+            },
+
+            0x0400_02B8, 0x0400_02BC => {
+                bus.io.sqrt.param = subset(u64, u32, address, bus.io.sqrt.param, value);
+                bus.io.sqrt.schedule(bus.scheduler);
+            },
+
+            // Engine B
+            0x0400_0304 => bus.ppu.io.powcnt.raw = value,
+
+            0x0400_1000 => bus.ppu.engines[1].dispcnt.raw = value,
+            0x0400_1008 => {
+                bus.ppu.engines[1].bg[0].cnt.raw = @truncate(value >> 0); // 0x0400_1008
+                bus.ppu.engines[1].bg[1].cnt.raw = @truncate(value >> 16); // 0x0400_100A
+            },
+            0x0400_100C => {
+                bus.ppu.engines[1].bg[2].cnt.raw = @truncate(value >> 0); // 0x0400_100A
+                bus.ppu.engines[1].bg[3].cnt.raw = @truncate(value >> 16); // 0x0400_100C
+            },
+            0x00400_1010 => {
+                bus.ppu.engines[1].bg[0].hofs.raw = @truncate(value >> 0); // 0x0400_1010
+                bus.ppu.engines[1].bg[0].vofs.raw = @truncate(value >> 16); // 0x0400_1012
+            },
+            0x00400_1014 => {
+                bus.ppu.engines[1].bg[1].hofs.raw = @truncate(value >> 0); // 0x0400_1014
+                bus.ppu.engines[1].bg[1].vofs.raw = @truncate(value >> 16); // 0x0400_1016
+            },
+            0x00400_1018 => {
+                bus.ppu.engines[1].bg[2].hofs.raw = @truncate(value >> 0); // 0x0400_1018
+                bus.ppu.engines[1].bg[2].vofs.raw = @truncate(value >> 16); // 0x0400_101A
+            },
+            0x00400_101C => {
+                bus.ppu.engines[1].bg[3].hofs.raw = @truncate(value >> 0); // 0x0400_101C
+                bus.ppu.engines[1].bg[3].vofs.raw = @truncate(value >> 16); // 0x0400_101E
+            },
 
             else => log.warn("unexpected: write(T: {}, addr: 0x{X:0>8}, value: 0x{X:0>8})", .{ T, address, value }),
         },
         u16 => switch (address) {
-            0x0400_0180 => bus.io.shared.ipc_fifo.sync.raw = blk: {
-                const ret = value & ~@as(u16, 0xF) | (bus.io.shared.ipc_fifo.sync.raw & 0xF);
-                log.debug("IPCFIFOSYNC <- 0x{X:0>8}", .{ret});
+            0x0400_0004 => bus.ppu.io.nds9.dispstat.raw = value,
 
-                break :blk ret;
+            // DMA Transfers
+            0x0400_00B0...0x0400_00DE => dma.write(T, &bus.dma, address, value),
+            0x0400_00E0...0x0400_00EE => std.mem.writeInt(T, bus.io.dma_fill[address & 0xF ..][0..@sizeOf(T)], value, .little),
+
+            // Timers
+            0x0400_0100...0x0400_010E => log.warn("TODO(timer): write(T: {}, addr: 0x{X:0>8}, value: 0x{X:0>8})", .{ T, address, value }),
+
+            0x0400_0180 => bus.io.shr.ipc.setIpcSync(.nds9, value),
+            0x0400_0184 => bus.io.shr.ipc.setIpcFifoCnt(.nds9, value),
+            0x0400_0208 => bus.io.ime = value & 1 == 1,
+
+            0x0400_0280 => {
+                bus.io.div.cnt.raw = value;
+                bus.io.div.schedule(bus.scheduler);
             },
-            0x0400_0184 => bus.io.shared.ipc_fifo.cnt.raw = value,
-            0x0400_0208 => bus.io.shared.ime = value & 1 == 1,
 
-            else => log.warn("unexpected: write(T: {}, addr: 0x{X:0>8}, value: 0x{X:0>8})", .{ T, address, value }),
+            0x0400_02B0 => {
+                bus.io.sqrt.cnt.raw = value;
+                bus.io.sqrt.schedule(bus.scheduler);
+            },
+
+            0x0400_0304 => bus.ppu.io.powcnt.raw = value,
+
+            0x0400_1008 => bus.ppu.engines[1].bg[0].cnt.raw = value,
+            0x0400_100A => bus.ppu.engines[1].bg[1].cnt.raw = value,
+            0x0400_100C => bus.ppu.engines[1].bg[2].cnt.raw = value,
+            0x0400_100E => bus.ppu.engines[1].bg[3].cnt.raw = value,
+
+            0x0400_1010 => bus.ppu.engines[1].bg[0].hofs.raw = value,
+            0x0400_1012 => bus.ppu.engines[1].bg[0].vofs.raw = value,
+            0x0400_1014 => bus.ppu.engines[1].bg[1].hofs.raw = value,
+            0x0400_1016 => bus.ppu.engines[1].bg[1].vofs.raw = value,
+            0x0400_1018 => bus.ppu.engines[1].bg[2].hofs.raw = value,
+            0x0400_101A => bus.ppu.engines[1].bg[2].vofs.raw = value,
+            0x0400_101C => bus.ppu.engines[1].bg[3].hofs.raw = value,
+            0x0400_101E => bus.ppu.engines[1].bg[3].vofs.raw = value,
+
+            else => log.warn("unexpected: write(T: {}, addr: 0x{X:0>8}, value: 0x{X:0>4})", .{ T, address, value }),
         },
         u8 => switch (address) {
-            0x0400_0240 => bus.ppu.io.vramcnt_a.raw = value,
-            0x0400_0241 => bus.ppu.io.vramcnt_b.raw = value,
-            0x0400_0242 => bus.ppu.io.vramcnt_c.raw = value,
-            0x0400_0243 => bus.ppu.io.vramcnt_d.raw = value,
+            // DMA Transfers
+            0x0400_00B0...0x0400_00DF => dma.write(T, &bus.dma, address, value),
+            0x0400_00E0...0x0400_00EF => std.mem.writeInt(T, bus.io.dma_fill[address & 0xF ..][0..@sizeOf(T)], value, .little),
 
-            else => log.warn("unexpected: write(T: {}, addr: 0x{X:0>8}, value: 0x{X:0>8})", .{ T, address, value }),
+            // Timers
+            0x0400_0100...0x0400_010F => log.warn("TODO(timer): write(T: {}, addr: 0x{X:0>8}, value: 0x{X:0>8})", .{ T, address, value }),
+
+            0x0400_0208 => bus.io.ime = value & 1 == 1,
+
+            0x0400_0240 => {
+                bus.ppu.vram.io.cnt_a.raw = value;
+                bus.ppu.vram.update();
+            },
+            0x0400_0241 => {
+                bus.ppu.vram.io.cnt_b.raw = value;
+                bus.ppu.vram.update();
+            },
+            0x0400_0242 => {
+                bus.ppu.vram.io.cnt_c.raw = value;
+                bus.ppu.vram.update();
+            },
+            0x0400_0243 => {
+                bus.ppu.vram.io.cnt_d.raw = value;
+                bus.ppu.vram.update();
+            },
+            0x0400_0244 => {
+                bus.ppu.vram.io.cnt_e.raw = value;
+                bus.ppu.vram.update();
+            },
+            0x0400_0245 => {
+                bus.ppu.vram.io.cnt_f.raw = value;
+                bus.ppu.vram.update();
+            },
+            0x0400_0246 => {
+                bus.ppu.vram.io.cnt_g.raw = value;
+                bus.ppu.vram.update();
+            },
+            0x0400_0247 => {
+                bus.io.shr.wramcnt.raw = value;
+                bus.wram.update(bus.io.shr.wramcnt);
+            },
+            0x0400_0248 => {
+                bus.ppu.vram.io.cnt_h.raw = value;
+                bus.ppu.vram.update();
+            },
+            0x0400_0249 => {
+                bus.ppu.vram.io.cnt_i.raw = value;
+                bus.ppu.vram.update();
+            },
+
+            else => log.warn("unexpected: write(T: {}, addr: 0x{X:0>8}, value: 0x{X:0>2})", .{ T, address, value }),
         },
         else => @compileError(T ++ " is an unsupported bus write type"),
     }
@@ -107,20 +361,148 @@ fn warn(comptime format: []const u8, args: anytype) u0 {
     return 0;
 }
 
-const PowCnt = extern union {
+pub const PowCnt = extern union {
     // Enable flag for both LCDs
     lcd: Bit(u32, 0),
-    gfx_2da: Bit(u32, 1),
-    render_3d: Bit(u32, 2),
-    geometry_3d: Bit(u32, 3),
-    gfx_2db: Bit(u32, 9),
+    engine2d_a: Bit(u32, 1),
+    render3d: Bit(u32, 2),
+    geometry3d: Bit(u32, 3),
+    engine2d_b: Bit(u32, 9),
     display_swap: Bit(u32, 15),
     raw: u32,
 };
 
-pub const DispcntA = extern union {
-    bg_mode: Bitfield(u32, 0, 2),
+/// Divisor
+const Divisor = struct {
+    const Scheduler = @import("../Scheduler.zig");
 
+    /// DIVCNT - Division Control (R/W)
+    cnt: Cnt = .{ .raw = 0x0000_0000 },
+    /// DIV_NUMER - division numerator (R/W)
+    numerator: u64 = 0x0000_0000_0000_0000,
+    /// DIV_DENOM - division denominator (R/W)
+    denominator: u64 = 0x0000_0000_0000_0000,
+
+    /// DIV_RESULT - division quotient (R)
+    result: u64 = 0x0000_0000_0000_0000,
+    /// DIVREM_RESULT - remainder
+    remainder: u64 = 0x0000_0000_0000_0000,
+
+    const Cnt = extern union {
+        mode: Bitfield(u32, 0, 2),
+        div_by_zero: Bit(u32, 14),
+        busy: Bit(u32, 15),
+        raw: u32,
+    };
+
+    pub fn schedule(self: *@This(), scheduler: *Scheduler) void {
+        defer self.cnt.busy.set();
+
+        const cycle_count: u64 = switch (self.cnt.mode.read()) {
+            0b00 => 18,
+            0b01, 0b10, 0b11 => 34,
+        };
+
+        scheduler.remove(.{ .nds9 = .div });
+        scheduler.push(.{ .nds9 = .div }, cycle_count);
+    }
+
+    pub fn onDivCalc(self: *@This()) void {
+        defer self.cnt.busy.unset();
+        self.cnt.div_by_zero.write(self.denominator == 0);
+
+        switch (self.cnt.mode.read()) {
+            0b00 => {
+                // 32bit / 32bit = 32bit , 32bit
+                const left = sext(i64, i32, self.numerator);
+                const right = sext(i64, i32, self.denominator);
+
+                if (right == 0) {
+                    self.remainder = @bitCast(left);
+                    self.result = if (left >> 63 & 1 == 1) @as(u64, 1) else @bitCast(@as(i64, -1));
+
+                    // FIXME(chore): replace `>> 32 ) << 32` with mask
+                    self.result = masks.mask(self.result, (~self.result >> 32) << 32, 0xFFFF_FFFF << 32);
+
+                    return;
+                }
+
+                self.result = @bitCast(@divTrunc(left, right));
+                self.remainder = @bitCast(@rem(left, right));
+            },
+            0b01, 0b11 => {
+                // 64bit / 32bit = 64bit , 32bit
+                const left = sext(i128, i64, self.numerator);
+                const right = sext(i128, i32, self.denominator);
+
+                if (right == 0) {
+                    self.remainder = @bitCast(@as(i64, @truncate(left)));
+                    self.result = if (left >> 63 & 1 == 1) @as(u64, 1) else @bitCast(@as(i64, -1));
+
+                    return;
+                }
+
+                self.result = @bitCast(@as(i64, @truncate(@divTrunc(left, right))));
+                self.remainder = @bitCast(@as(i64, @truncate(@rem(left, right))));
+            },
+            0b10 => {
+                // 64bit / 64bit = 64bit , 64bit
+                const left = sext(i128, i64, self.numerator);
+                const right = sext(i128, i64, self.denominator);
+
+                if (right == 0) {
+                    self.remainder = @bitCast(@as(i64, @truncate(left)));
+                    self.result = if (left >> 63 & 1 == 1) @as(u64, 1) else @bitCast(@as(i64, -1));
+
+                    return;
+                }
+
+                self.result = @bitCast(@as(i64, @truncate(@divTrunc(left, right))));
+                self.remainder = @bitCast(@as(i64, @truncate(@rem(left, right))));
+            },
+        }
+    }
+};
+
+/// Square Root Unit
+const SquareRootUnit = struct {
+    const Scheduler = @import("../Scheduler.zig");
+
+    /// SQRTCNT - Division Control (R/W)
+    cnt: Cnt = .{ .raw = 0x0000_0000 },
+
+    /// SQRT_RESULT - square root result (R)
+    result: u32 = 0x0000_0000,
+    /// SQRT_PARAM - square root paramater input (R/W)
+    param: u64 = 0x0000_0000_0000_0000,
+
+    const Cnt = extern union {
+        mode: Bit(u32, 0),
+        busy: Bit(u32, 15),
+        raw: u32,
+    };
+
+    pub fn schedule(self: *@This(), scheduler: *Scheduler) void {
+        defer self.cnt.busy.set();
+
+        scheduler.remove(.{ .nds9 = .sqrt });
+        scheduler.push(.{ .nds9 = .sqrt }, 13); // always takes 13 cycles
+    }
+
+    pub fn onSqrtCalc(self: *@This()) void {
+        defer self.cnt.busy.unset();
+
+        const mask: u64 = blk: {
+            const value: u64 = @intFromBool(!self.cnt.mode.read());
+            break :blk (value << 32) -% 1;
+        };
+
+        self.result = @truncate(std.math.sqrt(self.param & mask));
+    }
+};
+
+pub const DispcntA = extern union {
+    bg_mode: Bitfield(u32, 0, 3),
     /// toggle between 2D and 3D for BG0
     bg0_dimension: Bit(u32, 3),
     tile_obj_mapping: Bit(u32, 4),
@@ -136,8 +518,26 @@ pub const DispcntA = extern union {
     tile_obj_1d_boundary: Bitfield(u32, 20, 2),
     bitmap_obj_1d_boundary: Bit(u32, 22),
     obj_during_hblank: Bit(u32, 23),
-    character_base: Bitfield(u32, 24, 3),
-    screen_base: Bitfield(u32, 27, 2),
+    char_base: Bitfield(u32, 24, 3),
+    screen_base: Bitfield(u32, 27, 3),
+    bg_ext_pal_enable: Bit(u32, 30),
+    obj_ext_pal_enable: Bit(u32, 31),
+    raw: u32,
+};
+
+pub const DispcntB = extern union {
+    bg_mode: Bitfield(u32, 0, 3),
+    tile_obj_mapping: Bit(u32, 4),
+    bitmap_obj_2d_dimension: Bit(u32, 5),
+    bitmap_obj_mapping: Bit(u32, 6),
+    forced_blank: Bit(u32, 7),
+    bg_enable: Bitfield(u32, 8, 4),
+    obj_enable: Bit(u32, 12),
+    win_enable: Bitfield(u32, 13, 2),
+    obj_win_enable: Bit(u32, 15),
+    display_mode: Bitfield(u32, 16, 2),
+    tile_obj_1d_boundary: Bitfield(u32, 20, 2),
+    obj_during_hblank: Bit(u32, 23),
     bg_ext_pal_enable: Bit(u32, 30),
     obj_ext_pal_enable: Bit(u32, 31),
     raw: u32,
@@ -195,40 +595,33 @@ pub const Dispstat = extern union {
     raw: u16,
 };
 
-/// Read Only
-/// 0 = Pressed, 1 = Released
-pub const KeyInput = extern union {
-    a: Bit(u16, 0),
-    b: Bit(u16, 1),
-    select: Bit(u16, 2),
-    start: Bit(u16, 3),
-    right: Bit(u16, 4),
-    left: Bit(u16, 5),
-    up: Bit(u16, 6),
-    down: Bit(u16, 7),
-    shoulder_r: Bit(u16, 8),
-    shoulder_l: Bit(u16, 9),
+pub const Bgcnt = extern union {
+    priority: Bitfield(u16, 0, 2),
+    char_base: Bitfield(u16, 2, 4),
+    mosaic_enable: Bit(u16, 6),
+    colour_mode: Bit(u16, 7),
+    screen_base: Bitfield(u16, 8, 5),
+    display_overflow: Bit(u16, 13),
+    size: Bitfield(u16, 14, 2),
     raw: u16,
 };
 
-const AtomicKeyInput = struct {
-    const Self = @This();
-    const Ordering = std.atomic.Ordering;
-
-    inner: KeyInput = .{ .raw = 0x03FF },
-
-    pub inline fn load(self: *const Self, comptime ordering: Ordering) u16 {
-        return switch (ordering) {
-            .AcqRel, .Release => @compileError("not supported for atomic loads"),
-            else => @atomicLoad(u16, &self.inner.raw, ordering),
-        };
-    }
-
-    pub inline fn fetchOr(self: *Self, value: u16, comptime ordering: Ordering) void {
-        _ = @atomicRmw(u16, &self.inner.raw, .Or, value, ordering);
-    }
-
-    pub inline fn fetchAnd(self: *Self, value: u16, comptime ordering: Ordering) void {
-        _ = @atomicRmw(u16, &self.inner.raw, .And, value, ordering);
-    }
+/// Write Only
+const BackgroundOffset = extern union {
+    offset: Bitfield(u16, 0, 9),
+    raw: u16,
+};
+
+pub const Hofs = BackgroundOffset;
+pub const Vofs = BackgroundOffset;
+
+pub const DmaCnt = extern union {
+    dad_adj: Bitfield(u16, 5, 2),
+    sad_adj: Bitfield(u16, 7, 2),
+    repeat: Bit(u16, 9),
+    transfer_type: Bit(u16, 10),
+    start_timing: Bitfield(u16, 11, 3),
+    irq: Bit(u16, 14),
+    enabled: Bit(u16, 15),
+    raw: u16,
 };

src/core/ppu.zig

@@ -1,106 +1,197 @@
 const std = @import("std");
 const Allocator = std.mem.Allocator;
 
-const nds9 = @import("nds9.zig");
+const Scheduler = @import("Scheduler.zig");
+const System = @import("emu.zig").System;
+
+const Vram = @import("ppu/Vram.zig");
+const Oam = @import("ppu/Oam.zig");
+
+const EngineA = @import("ppu/engine.zig").EngineA;
+const EngineB = @import("ppu/engine.zig").EngineB;
+
+const dma7 = @import("nds7/dma.zig");
+const dma9 = @import("nds9/dma.zig");
+
+const handleInterrupt = @import("emu.zig").handleInterrupt;
 
 pub const screen_width = 256;
 pub const screen_height = 192;
+const KiB = 0x400;
 
 const cycles_per_dot = 6;
 
 pub const Ppu = struct {
     fb: FrameBuffer,
 
-    io: io = .{},
+    vram: *Vram,
 
-    pub fn init(allocator: Allocator) !@This() {
+    // FIXME: do I need a pointer here?
+    oam: *Oam,
+
+    engines: struct { EngineA, EngineB },
+
+    io: Io = .{},
+
+    pub const Io = struct {
+        const ty = @import("nds9/io.zig");
+
+        nds9: struct {
+            dispstat: ty.Dispstat = .{ .raw = 0x00000 },
+            vcount: ty.Vcount = .{ .raw = 0x0000 },
+        } = .{},
+
+        nds7: struct {
+            dispstat: ty.Dispstat = .{ .raw = 0x0000 },
+            vcount: ty.Vcount = .{ .raw = 0x00000 },
+        } = .{},
+
+        powcnt: ty.PowCnt = .{ .raw = 0x0000_0000 },
+    };
+
+    pub fn init(allocator: Allocator, vram: *Vram) !@This() {
         return .{
             .fb = try FrameBuffer.init(allocator),
+            .engines = .{ try EngineA.init(allocator), try EngineB.init(allocator) },
+            .vram = vram,
+            .oam = blk: {
+                var oam = try allocator.create(Oam);
+                oam.init();
+
+                break :blk oam;
+            },
         };
     }
 
     pub fn deinit(self: @This(), allocator: Allocator) void {
         self.fb.deinit(allocator);
+        inline for (self.engines) |eng| eng.deinit(allocator);
+        allocator.destroy(self.oam);
     }
 
-    pub fn drawScanline(self: *@This(), nds9_bus: *nds9.Bus) void {
-        const bg_mode = self.io.dispcnt_a.display_mode.read();
-        const scanline = self.io.vcount.scanline.read();
+    pub fn drawScanline(self: *@This(), bus: *System.Bus9) void {
+        if (self.io.powcnt.engine2d_a.read())
+            self.engines[0].drawScanline(bus, &self.fb);
 
-        switch (bg_mode) {
-            0x0 => {},
-            0x1 => {},
-            0x2 => {
-                // Draw Top Screen
-                {
-                    const buf = self.fb.top(.back);
-
-                    const ptr: *[screen_width * screen_height]u32 = @ptrCast(@alignCast(buf.ptr));
-                    const scanline_ptr = ptr[screen_width * @as(u32, scanline) ..][0..screen_width];
-
-                    const base_addr: u32 = 0x0680_0000 + (screen_width * @sizeOf(u16)) * @as(u32, scanline);
-
-                    // FIXME: I don't think it's okay to be accessing the ARM9 Bus instead of just working with
-                    // memory directly. However, I do understand that VRAM-A, VRAM-B might change things
-
-                    for (scanline_ptr, 0..) |*rgba, i| {
-                        const addr = base_addr + @as(u32, @intCast(i)) * @sizeOf(u16);
-                        rgba.* = rgba888(nds9_bus.dbgRead(u16, addr));
-                    }
-                }
-            },
-            0x3 => {},
-        }
+        if (self.io.powcnt.engine2d_b.read())
+            self.engines[1].drawScanline(bus, &self.fb);
     }
 
     /// HDraw -> HBlank
-    pub fn onHdrawEnd(self: *@This(), nds9_scheduler: *nds9.Scheduler, late: u64) void {
+    pub fn onHdrawEnd(self: *@This(), system: System, scheduler: *Scheduler, late: u64) void {
+        if (self.io.nds9.dispstat.hblank_irq.read()) {
+            system.bus9.io.irq.hblank.set();
+            handleInterrupt(.nds9, system.arm946es);
+        }
+
+        if (self.io.nds7.dispstat.hblank_irq.read()) {
+            system.bus7.io.irq.hblank.set();
+            handleInterrupt(.nds7, system.arm7tdmi);
+        }
+
+        if (!self.io.nds9.dispstat.vblank.read()) { // ensure we aren't in VBlank
+            dma9.onHblank(system.bus9);
+        }
+
+        self.io.nds9.dispstat.hblank.set();
+        self.io.nds7.dispstat.hblank.set();
+
         const dots_in_hblank = 99;
-        std.debug.assert(self.io.dispstat.hblank.read() == false);
-        std.debug.assert(self.io.dispstat.vblank.read() == false);
-
-        // TODO: Signal HBlank IRQ
-
-        self.io.dispstat.hblank.set();
-        nds9_scheduler.push(.hblank, dots_in_hblank * cycles_per_dot -| late);
+        scheduler.push(.{ .nds9 = .hblank }, dots_in_hblank * cycles_per_dot -| late);
     }
 
-    pub fn onHblankEnd(self: *@This(), nds9_scheduler: *nds9.Scheduler, late: u64) void {
-        const scanline_count = 192 + 71;
+    /// VBlank -> HBlank (Still VBlank)
+    pub fn onVblankEnd(self: *@This(), system: System, scheduler: *Scheduler, late: u64) void {
+        if (self.io.nds9.dispstat.hblank_irq.read()) {
+            system.bus9.io.irq.hblank.set();
+            handleInterrupt(.nds9, system.arm946es);
+        }
 
-        const prev_scanline = self.io.vcount.scanline.read();
-        const scanline = (prev_scanline + 1) % scanline_count;
+        if (self.io.nds7.dispstat.hblank_irq.read()) {
+            system.bus7.io.irq.hblank.set();
+            handleInterrupt(.nds7, system.arm7tdmi);
+        }
 
-        self.io.vcount.scanline.write(scanline);
-        self.io.dispstat.hblank.unset();
+        self.io.nds9.dispstat.hblank.set();
+        self.io.nds7.dispstat.hblank.set();
 
-        const coincidence = scanline == self.io.dispstat.lyc.read();
-        self.io.dispstat.coincidence.write(coincidence);
+        // TODO: Run DMAs on HBlank
 
-        // TODO: LYC == LY IRQ
+        const dots_in_hblank = 99;
+        scheduler.push(.{ .nds9 = .hblank }, dots_in_hblank * cycles_per_dot -| late);
+    }
+
+    /// HBlank -> HDraw / VBlank
+    pub fn onHblankEnd(self: *@This(), system: System, scheduler: *Scheduler, late: u64) void {
+        const scanline_total = 263; // 192 visible, 71 blanking
+
+        const prev_scanline = self.io.nds9.vcount.scanline.read();
+        const scanline = (prev_scanline + 1) % scanline_total;
+
+        self.io.nds9.vcount.scanline.write(scanline);
+        self.io.nds7.vcount.scanline.write(scanline);
+
+        self.io.nds9.dispstat.hblank.unset();
+        self.io.nds7.dispstat.hblank.unset();
+
+        {
+            const coincidence = scanline == self.io.nds9.dispstat.lyc.read();
+            self.io.nds9.dispstat.coincidence.write(coincidence);
+
+            if (coincidence and self.io.nds9.dispstat.vcount_irq.read()) {
+                system.bus9.io.irq.coincidence.set();
+                handleInterrupt(.nds9, system.arm946es);
+            }
+        }
+
+        {
+            const coincidence = scanline == self.io.nds7.dispstat.lyc.read();
+            self.io.nds7.dispstat.coincidence.write(coincidence);
+
+            if (coincidence and self.io.nds7.dispstat.vcount_irq.read()) {
+                system.bus7.io.irq.coincidence.set();
+                handleInterrupt(.nds7, system.arm7tdmi);
+            }
+        }
 
         if (scanline < 192) {
-            std.debug.assert(self.io.dispstat.vblank.read() == false);
-            std.debug.assert(self.io.dispstat.hblank.read() == false);
-
             // Draw Another Scanline
             const dots_in_hdraw = 256;
-            return nds9_scheduler.push(.draw, dots_in_hdraw * cycles_per_dot -| late);
+            return scheduler.push(.{ .nds9 = .draw }, dots_in_hdraw * cycles_per_dot -| late);
         }
 
         if (scanline == 192) {
             // Transition from Hblank to Vblank
             self.fb.swap();
-            self.io.dispstat.vblank.set();
 
-            // TODO: Signal VBlank IRQ
+            if (self.io.nds9.dispstat.vblank_irq.read()) {
+                system.bus9.io.irq.vblank.set();
+                handleInterrupt(.nds9, system.arm946es);
+            }
+
+            if (self.io.nds7.dispstat.vblank_irq.read()) {
+                system.bus7.io.irq.vblank.set();
+                handleInterrupt(.nds7, system.arm7tdmi);
+            }
+
+            self.io.nds9.dispstat.vblank.set();
+            self.io.nds7.dispstat.vblank.set();
+
+            // TODO: Affine BG Latches
+
+            dma7.onVblank(system.bus7);
+            dma9.onVblank(system.bus9);
+
+            // TODO: VBlank DMA9 Transfers
         }
 
-        if (scanline == 262) self.io.dispstat.vblank.unset();
-        std.debug.assert(self.io.dispstat.vblank.read() == (scanline != 262));
+        if (scanline == 262) {
+            self.io.nds9.dispstat.vblank.unset();
+            self.io.nds7.dispstat.vblank.unset();
+        }
 
-        const dots_in_scanline = 256 + 99;
-        nds9_scheduler.push(.hblank, dots_in_scanline * cycles_per_dot -| late);
+        const dots_in_vblank = 256;
+        scheduler.push(.{ .nds9 = .vblank }, dots_in_vblank * cycles_per_dot -| late);
     }
 };
 
@@ -109,15 +200,15 @@ pub const FrameBuffer = struct {
 
     current: u1 = 0,
 
-    ptr: *[len * 4]u8,
+    ptr: *align(@sizeOf(u32)) [len * 4]u8,
 
     const Position = enum { top, bottom };
     const Layer = enum { front, back };
 
     pub fn init(allocator: Allocator) !@This() {
-        const ptr = try allocator.create([len * 4]u8);
+        const buf = try allocator.alignedAlloc(u8, @sizeOf(u32), len * 4);
 
-        return .{ .ptr = ptr };
+        return .{ .ptr = buf[0 .. len * 4] };
     }
 
     pub fn deinit(self: @This(), allocator: Allocator) void {
@@ -145,34 +236,3 @@ pub const FrameBuffer = struct {
         return self.get(.bottom, layer);
     }
 };
-
-inline fn rgba888(bgr555: u16) u32 {
-    const b: u32 = bgr555 >> 10 & 0x1F;
-    const g: u32 = bgr555 >> 5 & 0x1F;
-    const r: u32 = bgr555 & 0x1F;
-
-    // zig fmt: off
-    return (r << 3 | r >> 2) << 24
-        |  (g << 3 | g >> 2) << 16
-        |  (b << 3 | b >> 2) << 8
-        |  0xFF;
-    // zig fmt: on
-}
-
-const io = struct {
-    const nds9_io = @import("nds9/io.zig"); // TODO: rename
-
-    /// Read / Write
-    dispcnt_a: nds9_io.DispcntA = .{ .raw = 0x0000_0000 },
-    /// Read / Write
-    dispstat: nds9_io.Dispstat = .{ .raw = 0x0000 },
-
-    /// Read-Only
-    vcount: nds9_io.Vcount = .{ .raw = 0x0000 },
-
-    /// Write-Only
-    vramcnt_a: nds9_io.Vramcnt.A = .{ .raw = 0x00 },
-    vramcnt_b: nds9_io.Vramcnt.A = .{ .raw = 0x00 },
-    vramcnt_c: nds9_io.Vramcnt.C = .{ .raw = 0x00 },
-    vramcnt_d: nds9_io.Vramcnt.C = .{ .raw = 0x00 },
-};

src/core/ppu/Oam.zig

@@ -0,0 +1,7 @@
+const KiB = 0x400;
+
+buf: [2 * KiB]u8,
+
+pub fn init(self: *@This()) void {
+    @memset(self.buf[0..], 0);
+}

src/core/ppu/Vram.zig

@@ -0,0 +1,290 @@
+const std = @import("std");
+const KiB = 0x400;
+
+const System = @import("../emu.zig").System;
+
+const Allocator = std.mem.Allocator;
+const IntFittingRange = std.math.IntFittingRange;
+
+const page_size = 16 * KiB; // smallest allocation is 16 KiB
+const addr_space_size = 0x0100_0000; // 0x0600_0000 -> 0x06FF_FFFF (inclusive)
+const table_len = addr_space_size / page_size;
+const buf_len = 656 * KiB;
+
+const log = std.log.scoped(.vram);
+
+io: Io = .{},
+
+_buf: *[buf_len]u8,
+nds9_table: *const [table_len]?[*]u8,
+nds7_table: *const [table_len]?[*]u8,
+
+const Io = struct {
+    pub const Vramstat = nds7.Vramstat;
+
+    const nds9 = @import("../nds9/io.zig");
+    const nds7 = @import("../nds7/io.zig");
+
+    stat: nds7.Vramstat = .{ .raw = 0x00 },
+
+    /// Write-Only (according to melonDS these are readable lol)
+    cnt_a: nds9.Vramcnt.A = .{ .raw = 0x00 },
+    cnt_b: nds9.Vramcnt.A = .{ .raw = 0x00 },
+    cnt_c: nds9.Vramcnt.C = .{ .raw = 0x00 },
+    cnt_d: nds9.Vramcnt.C = .{ .raw = 0x00 },
+    cnt_e: nds9.Vramcnt.E = .{ .raw = 0x00 },
+    cnt_f: nds9.Vramcnt.C = .{ .raw = 0x00 },
+    cnt_g: nds9.Vramcnt.C = .{ .raw = 0x00 },
+    cnt_h: nds9.Vramcnt.H = .{ .raw = 0x00 },
+    cnt_i: nds9.Vramcnt.H = .{ .raw = 0x00 },
+};
+
+pub fn init(self: *@This(), allocator: Allocator) !void {
+    const buf = try allocator.create([buf_len]u8);
+    errdefer allocator.destroy(buf);
+    @memset(buf, 0);
+
+    const tables = try allocator.alloc(?[*]u8, 2 * table_len);
+    @memset(tables, null);
+
+    self.* = .{
+        .nds9_table = tables[0..table_len],
+        .nds7_table = tables[table_len .. 2 * table_len],
+        ._buf = buf,
+    };
+
+    // ROMS like redpanda.nds won't write to VRAMCNT before trying to write to VRAM
+    // therefore we assume some default allocation (in this casee VRAMCNT_A -> VRAMCNT_I are 0x00)
+    self.update();
+}
+
+pub fn deinit(self: @This(), allocator: Allocator) void {
+    allocator.destroy(self._buf);
+
+    const ptr: [*]?[*]const u8 = @ptrCast(@constCast(self.nds9_table));
+    allocator.free(ptr[0 .. 2 * table_len]);
+}
+
+/// NDS7 VRAMSTAT
+pub fn stat(self: *const @This()) Io.Vramstat {
+    const vram_c: u8 = @intFromBool(self.io.cnt_c.enable.read() and self.io.cnt_c.mst.read() == 2);
+    const vram_d: u8 = @intFromBool(self.io.cnt_d.enable.read() and self.io.cnt_d.mst.read() == 2);
+
+    return .{ .raw = (vram_d << 1) | vram_c };
+}
+
+const Kind = enum {
+    a,
+    b,
+    c,
+    d,
+    e,
+    f,
+    g,
+    h,
+    i,
+
+    /// In Bytes
+    inline fn size(self: @This()) u32 {
+        return switch (self) {
+            .a => 128 * KiB,
+            .b => 128 * KiB,
+            .c => 128 * KiB,
+            .d => 128 * KiB,
+            .e => 64 * KiB,
+            .f => 16 * KiB,
+            .g => 16 * KiB,
+            .h => 32 * KiB,
+            .i => 16 * KiB,
+        };
+    }
+};
+
+// TODO: Rename
+fn range(comptime kind: Kind, mst: u3, offset: u2) u32 {
+    const ofs: u32 = offset;
+    // panic messages are from GBATEK
+
+    return switch (kind) {
+        .a => switch (mst) {
+            0 => 0x0680_0000,
+            1 => 0x0600_0000 + (0x0002_0000 * ofs),
+            2 => 0x0640_0000 + (0x0002_0000 * (ofs & 0b01)),
+            3 => @panic("VRAMCNT_A: Slot OFS(0-3)"),
+            else => std.debug.panic("Invalid MST for VRAMCNT_{s}", .{[_]u8{std.ascii.toUpper(@tagName(kind)[0])}}),
+        },
+        .b => switch (mst) {
+            0 => 0x0682_0000,
+            1 => 0x0600_0000 + (0x0002_0000 * ofs),
+            2 => 0x0640_0000 + (0x0002_0000 * (ofs & 0b01)),
+            3 => @panic("VRAMCNT_B: Slot OFS(0-3)"),
+            else => std.debug.panic("Invalid MST for VRAMCNT_{s}", .{[_]u8{std.ascii.toUpper(@tagName(kind)[0])}}),
+        },
+        .c => switch (mst) {
+            0 => 0x0684_0000,
+            1 => 0x0600_0000 + (0x0002_0000 * ofs),
+            2 => 0x0600_0000 + (0x0002_0000 * (ofs & 0b01)),
+            3 => @panic("VRAMCNT_C: Slot OFS(0-3)"),
+            4 => 0x0620_0000,
+            else => std.debug.panic("Invalid MST for VRAMCNT_{s}", .{[_]u8{std.ascii.toUpper(@tagName(kind)[0])}}),
+        },
+        .d => switch (mst) {
+            0 => 0x0686_0000,
+            1 => 0x0600_0000 + (0x0002_0000 * ofs),
+            2 => 0x0600_0000 + (0x0002_0000 * (ofs & 0b01)),
+            3 => @panic("VRAMCNT_D: Slot OFS(0-3)"),
+            4 => 0x0660_0000,
+            else => std.debug.panic("Invalid MST for VRAMCNT_{s}", .{[_]u8{std.ascii.toUpper(@tagName(kind)[0])}}),
+        },
+        .e => switch (mst) {
+            0 => 0x0688_0000,
+            1 => 0x0600_0000,
+            2 => 0x0640_0000,
+            3 => @panic("VRAMCNT_E: Slots 0-3"),
+            else => std.debug.panic("Invalid MST for VRAMCNT_{s}", .{[_]u8{std.ascii.toUpper(@tagName(kind)[0])}}),
+        },
+        .f => switch (mst) {
+            0 => 0x0689_0000,
+            1 => 0x0600_0000 + (0x0000_4000 * (ofs & 0b01)) + (0x0001_0000 * (ofs >> 1)),
+            2 => 0x0640_0000 + (0x0000_4000 * (ofs & 0b01)) + (0x0001_0000 * (ofs >> 1)),
+            3 => @panic("VRAMCNT_F: Slot (OFS.0*1)+(OFS.1*4)"),
+            4 => @panic("VRAMCNT_F: Slot 0-1 (OFS=0), Slot 2-3 (OFS=1)"),
+            5 => @panic("VRAMCNT_F: Slot 0"),
+            else => std.debug.panic("Invalid MST for VRAMCNT_{s}", .{[_]u8{std.ascii.toUpper(@tagName(kind)[0])}}),
+        },
+        .g => switch (mst) {
+            0 => 0x0689_4000,
+            1 => 0x0600_0000 + (0x0000_4000 * (ofs & 0b01)) + (0x0001_0000 * (ofs >> 1)),
+            2 => 0x0640_0000 + (0x0000_4000 * (ofs & 0b01)) + (0x0001_0000 * (ofs >> 1)),
+            3 => @panic("VRAMCNT_G: Slot (OFS.0*1)+(OFS.1*4)"),
+            4 => @panic("VRAMCNT_G: Slot 0-1 (OFS=0), Slot 2-3 (OFS=1)"),
+            5 => @panic("VRAMCNT_G: Slot 0"),
+            else => std.debug.panic("Invalid MST for VRAMCNT_{s}", .{[_]u8{std.ascii.toUpper(@tagName(kind)[0])}}),
+        },
+        .h => switch (mst) {
+            0 => 0x0689_8000,
+            1 => 0x0620_0000,
+            2 => @panic("VRAMCNT_H: Slot 0-3"),
+            else => std.debug.panic("Invalid MST for VRAMCNT_{s}", .{[_]u8{std.ascii.toUpper(@tagName(kind)[0])}}),
+        },
+        .i => switch (mst) {
+            0 => 0x068A_0000,
+            1 => 0x0620_8000,
+            2 => 0x0660_0000,
+            3 => @panic("Slot 0"),
+            else => std.debug.panic("Invalid MST for VRAMCNT_{s}", .{[_]u8{std.ascii.toUpper(@tagName(kind)[0])}}),
+        },
+    };
+}
+
+fn buf_offset(comptime kind: Kind) usize {
+    // zig fmt: off
+        return switch (kind) {
+            .a => 0,                                                            // 0x00000
+            .b => (128 * KiB) * 1,                                              // 0x20000 (+ 0x20000)
+            .c => (128 * KiB) * 2,                                              // 0x40000 (+ 0x20000)
+            .d => (128 * KiB) * 3,                                              // 0x60000 (+ 0x20000)
+            .e => (128 * KiB) * 4,                                              // 0x80000 (+ 0x20000)
+            .f => (128 * KiB) * 4 + (64 * KiB),                                 // 0x90000 (+ 0x10000)
+            .g => (128 * KiB) * 4 + (64 * KiB) + (16 * KiB) * 1,                // 0x94000 (+ 0x04000)
+            .h => (128 * KiB) * 4 + (64 * KiB) + (16 * KiB) * 2,                // 0x98000 (+ 0x04000)
+            .i => (128 * KiB) * 4 + (64 * KiB) + (16 * KiB) * 2 + (32 * KiB)    // 0xA0000 (+ 0x08000)
+        };
+        // zig fmt: on
+}
+
+fn CntType(comptime kind: Kind) type {
+    const Vramcnt = @import("../nds9/io.zig").Vramcnt;
+
+    return switch (kind) {
+        .a => Vramcnt.A,
+        .b => Vramcnt.A,
+        .c => Vramcnt.C,
+        .d => Vramcnt.C,
+        .e => Vramcnt.E,
+        .f => Vramcnt.C,
+        .g => Vramcnt.C,
+        .h => Vramcnt.H,
+        .i => Vramcnt.H,
+    };
+}
+
+fn cntValue(self: *const @This(), comptime kind: Kind) CntType(kind) {
+    return switch (kind) {
+        .a => self.io.cnt_a,
+        .b => self.io.cnt_b,
+        .c => self.io.cnt_c,
+        .d => self.io.cnt_d,
+        .e => self.io.cnt_e,
+        .f => self.io.cnt_f,
+        .g => self.io.cnt_g,
+        .h => self.io.cnt_h,
+        .i => self.io.cnt_i,
+    };
+}
+
+// TODO: We always update the entirety of VRAM when that argubably isn't necessary
+pub fn update(self: *@This()) void {
+    const nds9_tbl = @constCast(self.nds9_table);
+    const nds7_tbl = @constCast(self.nds7_table);
+
+    for (nds9_tbl, nds7_tbl, 0..) |*nds9_ptr, *nds7_ptr, i| {
+        const addr = 0x0600_0000 + (i * page_size);
+
+        inline for (std.meta.fields(Kind)) |f| {
+            const kind = @field(Kind, f.name);
+            const cnt = cntValue(self, kind);
+            const ofs = switch (kind) {
+                .e, .h, .i => 0,
+                else => cnt.offset.read(),
+            };
+
+            const min = range(kind, cnt.mst.read(), ofs);
+            const max = min + kind.size();
+            const offset = addr & (kind.size() - 1);
+
+            if (min <= addr and addr < max) {
+                if ((kind == .c or kind == .d) and cnt.mst.read() == 2) {
+                    // Allocate to ARM7
+                    nds7_ptr.* = self._buf[buf_offset(kind) + offset ..].ptr;
+                } else {
+                    nds9_ptr.* = self._buf[buf_offset(kind) + offset ..].ptr;
+                }
+            }
+        }
+    }
+}
+
+pub fn read(self: @This(), comptime T: type, comptime proc: System.Process, address: u32) T {
+    const bits = @typeInfo(IntFittingRange(0, page_size - 1)).Int.bits;
+    const masked_addr = address & (addr_space_size - 1);
+    const page = masked_addr >> bits;
+    const offset = masked_addr & (page_size - 1);
+    const table = if (proc == .nds9) self.nds9_table else self.nds7_table;
+
+    if (table[page]) |some_ptr| {
+        const ptr: [*]const T = @ptrCast(@alignCast(some_ptr));
+
+        return ptr[offset / @sizeOf(T)];
+    }
+
+    log.err("{s}: read(T: {}, addr: 0x{X:0>8}) was in un-mapped VRAM space", .{ @tagName(proc), T, address });
+    return 0x00;
+}
+
+pub fn write(self: *@This(), comptime T: type, comptime proc: System.Process, address: u32, value: T) void {
+    const bits = @typeInfo(IntFittingRange(0, page_size - 1)).Int.bits;
+    const masked_addr = address & (addr_space_size - 1);
+    const page = masked_addr >> bits;
+    const offset = masked_addr & (page_size - 1);
+    const table = if (proc == .nds9) self.nds9_table else self.nds7_table;
+
+    if (table[page]) |some_ptr| {
+        const ptr: [*]T = @ptrCast(@alignCast(some_ptr));
+        ptr[offset / @sizeOf(T)] = value;
+
+        return;
+    }
+
+    log.err("{s}: write(T: {}, addr: 0x{X:0>8}, value: 0x{X:0>8}) was in un-mapped VRA< space", .{ @tagName(proc), T, address, value });
+}

src/core/ppu/engine.zig

@@ -0,0 +1,340 @@
+const std = @import("std");
+const Bus = @import("../nds9/Bus.zig");
+
+const FrameBuffer = @import("../ppu.zig").FrameBuffer;
+
+const DispcntA = @import("../nds9/io.zig").DispcntA;
+const DispcntB = @import("../nds9/io.zig").DispcntB;
+
+const Ppu = @import("../ppu.zig").Ppu;
+
+const width = @import("../ppu.zig").screen_width;
+const height = @import("../ppu.zig").screen_height;
+
+const KiB = 0x400;
+
+const EngineKind = enum { a, b };
+
+pub const EngineA = Engine(.a);
+pub const EngineB = Engine(.b);
+
+fn Engine(comptime kind: EngineKind) type {
+    const log = std.log.scoped(.engine2d); // TODO: specify between 2D-A and 2D-B
+
+    // FIXME: don't commit zig crimes
+    const Type = struct {
+        fn inner(comptime TypeA: type, comptime TypeB: type) type {
+            return if (kind == .a) TypeA else TypeB;
+        }
+    }.inner;
+
+    return struct {
+        dispcnt: Type(DispcntA, DispcntB) = .{ .raw = 0x0000_0000 },
+
+        bg: [4]bg.Text = .{ .{}, .{}, .{}, .{} },
+
+        // TODO: Rename
+        scanline: Scanline,
+
+        pub fn init(allocator: std.mem.Allocator) !@This() {
+            return .{
+                .scanline = try Scanline.init(allocator),
+            };
+        }
+
+        pub fn deinit(self: @This(), allocator: std.mem.Allocator) void {
+            self.scanline.deinit(allocator);
+        }
+
+        pub fn drawScanline(self: *@This(), bus: *Bus, fb: *FrameBuffer) void {
+            const disp_mode = self.dispcnt.display_mode.read();
+
+            switch (disp_mode) {
+                0 => { // Display Off
+                    const buf = switch (kind) {
+                        .a => if (bus.ppu.io.powcnt.display_swap.read()) fb.top(.back) else fb.btm(.back),
+                        .b => if (bus.ppu.io.powcnt.display_swap.read()) fb.btm(.back) else fb.top(.back),
+                    };
+
+                    @memset(buf, 0xFF); // set everything to white
+                },
+                1 => {
+                    const bg_mode = self.dispcnt.bg_mode.read();
+                    const bg_enable = self.dispcnt.bg_enable.read();
+                    const scanline: u32 = bus.ppu.io.nds9.vcount.scanline.read();
+
+                    switch (bg_mode) {
+                        //  BG0     BG1     BG2     BG3
+                        //  Text/3D Text    Text    Text
+                        0 => {
+                            // TODO: Fetch Sprites
+
+                            for (0..4) |layer| {
+                                // TODO: Draw Sprites
+
+                                inline for (0..4) |i| {
+                                    if (layer == self.bg[i].cnt.priority.read() and (bg_enable >> i) & 1 == 1) self.drawBackground(i, bus);
+                                }
+                            }
+
+                            const buf = switch (kind) {
+                                .a => if (bus.ppu.io.powcnt.display_swap.read()) fb.top(.back) else fb.btm(.back),
+                                .b => if (bus.ppu.io.powcnt.display_swap.read()) fb.btm(.back) else fb.top(.back),
+                            };
+
+                            const scanline_buf = blk: {
+                                const rgba_ptr: *[width * height]u32 = @ptrCast(@alignCast(buf));
+                                break :blk rgba_ptr[width * scanline ..][0..width];
+                            };
+
+                            self.renderTextMode(bus.dbgRead(u16, 0x0500_0000), scanline_buf);
+                        },
+                        else => |mode| {
+                            log.err("TODO: Implement Mode {}", .{mode});
+                            @panic("fatal error");
+                        },
+                    }
+                },
+                2 => { // VRAM display
+                    if (kind == .b) return;
+                    // TODO: Master Brightness can still affect this mode
+
+                    const scanline: u32 = bus.ppu.io.nds9.vcount.scanline.read();
+                    const buf = if (bus.ppu.io.powcnt.display_swap.read()) fb.top(.back) else fb.btm(.back);
+
+                    const scanline_buf = blk: {
+                        const rgba_ptr: *[width * height]u32 = @ptrCast(@alignCast(buf));
+                        break :blk rgba_ptr[width * scanline ..][0..width];
+                    };
+
+                    const base_addr: u32 = 0x0680_0000 + (width * @sizeOf(u16)) * @as(u32, scanline);
+
+                    for (scanline_buf, 0..) |*rgba, i| {
+                        const addr = base_addr + @as(u32, @intCast(i)) * @sizeOf(u16);
+                        rgba.* = rgba888(bus.dbgRead(u16, addr));
+                    }
+                },
+                3 => {
+                    if (kind == .b) return;
+
+                    @panic("TODO: main memory display");
+                },
+            }
+        }
+
+        fn drawBackground(self: *@This(), comptime layer: u2, bus: *Bus) void {
+            const screen_base = blk: {
+                const bgcnt_off: u32 = self.bg[layer].cnt.screen_base.read();
+                const dispcnt_off: u32 = if (kind == .a) self.dispcnt.screen_base.read() else 0;
+
+                break :blk (2 * KiB) * bgcnt_off + (64 * KiB) * dispcnt_off;
+            };
+
+            const char_base = blk: {
+                const bgcnt_off: u32 = self.bg[layer].cnt.char_base.read();
+                const dispcnt_off: u32 = if (kind == .a) self.dispcnt.char_base.read() else 0;
+
+                break :blk (16 * KiB) * bgcnt_off + (64 * KiB) * dispcnt_off;
+            };
+
+            const is_8bpp = self.bg[layer].cnt.colour_mode.read();
+            const size = self.bg[layer].cnt.size.read();
+
+            // In 4bpp: 1 byte represents two pixels so the length is (8 x 8) / 2
+            // In 8bpp: 1 byte represents one pixel so the length is 8 x 8
+            const tile_len: u32 = if (is_8bpp) 0x40 else 0x20;
+            const tile_row_offset: u32 = if (is_8bpp) 0x8 else 0x4;
+
+            const vofs: u32 = self.bg[layer].vofs.offset.read();
+            const hofs: u32 = self.bg[layer].hofs.offset.read();
+
+            const y: u32 = vofs + bus.ppu.io.nds9.vcount.scanline.read();
+
+            for (0..width) |idx| {
+                const i: u32 = @intCast(idx);
+                const x = hofs + i;
+
+                // TODO: Windowing
+
+                // Grab the Screen Entry from VRAM
+                const entry_addr = screen_base + tilemapOffset(size, x, y);
+                const entry: bg.Screen.Entry = @bitCast(bus.read(u16, 0x0600_0000 + entry_addr));
+
+                // Calculate the Address of the Tile in the designated Charblock
+                // We also take this opportunity to flip tiles if necessary
+                const tile_id: u32 = entry.tile_id.read();
+
+                // Calculate row and column offsets. Understand that
+                // `tile_len`, `tile_row_offset` and `col` are subject to different
+                // values depending on whether we are in 4bpp or 8bpp mode.
+                const row = @as(u3, @truncate(y)) ^ if (entry.v_flip.read()) 7 else @as(u3, 0);
+                const col = @as(u3, @truncate(x)) ^ if (entry.h_flip.read()) 7 else @as(u3, 0);
+                const tile_addr = char_base + (tile_id * tile_len) + (row * tile_row_offset) + if (is_8bpp) col else col >> 1;
+
+                const tile = bus.read(u8, 0x0600_0000 + tile_addr);
+                // If we're in 8bpp, then the tile value is an index into the palette,
+                // If we're in 4bpp, we have to account for a pal bank value in the Screen entry
+                // and then we can index the palette
+                const pal_addr: u32 = if (!is_8bpp) get4bppTilePalette(entry.pal_bank.read(), col, tile) else tile;
+
+                if (pal_addr != 0) {
+                    self.drawBackgroundPixel(layer, i, bus.read(u16, 0x0500_0000 + pal_addr * 2));
+                }
+            }
+        }
+
+        inline fn get4bppTilePalette(pal_bank: u4, col: u3, tile: u8) u8 {
+            const nybble_tile = tile >> ((col & 1) << 2) & 0xF;
+            if (nybble_tile == 0) return 0;
+
+            return (@as(u8, pal_bank) << 4) | nybble_tile;
+        }
+
+        fn renderTextMode(self: *@This(), backdrop: u16, frame_buf: []u32) void {
+            for (self.scanline.top(), self.scanline.btm(), frame_buf) |maybe_top, maybe_btm, *rgba| {
+                _ = maybe_btm;
+
+                const bgr555 = switch (maybe_top) {
+                    .set => |px| px,
+                    else => backdrop,
+                };
+
+                rgba.* = rgba888(bgr555);
+            }
+
+            self.scanline.reset();
+        }
+
+        // TODO: Comment this + get a better understanding
+        fn tilemapOffset(size: u2, x: u32, y: u32) u32 {
+            // Current Row: (y % PIXEL_COUNT) / 8
+            // Current COlumn: (x % PIXEL_COUNT) / 8
+            // Length of 1 row of Screen Entries: 0x40
+            // Length of 1 Screen Entry: 0x2 is the size of a screen entry
+            @setRuntimeSafety(false);
+
+            return switch (size) {
+                0 => (x % 256 / 8) * 2 + (y % 256 / 8) * 0x40, // 256 x 256
+                1 => blk: {
+                    // 512 x 256
+                    const offset: u32 = if (x & 0x1FF > 0xFF) 0x800 else 0;
+                    break :blk offset + (x % 256 / 8) * 2 + (y % 256 / 8) * 0x40;
+                },
+                2 => blk: {
+                    // 256 x 512
+                    const offset: u32 = if (y & 0x1FF > 0xFF) 0x800 else 0;
+                    break :blk offset + (x % 256 / 8) * 2 + (y % 256 / 8) * 0x40;
+                },
+                3 => blk: {
+                    // 512 x 512
+                    const offset: u32 = if (x & 0x1FF > 0xFF) 0x800 else 0;
+                    const offset_2: u32 = if (y & 0x1FF > 0xFF) 0x800 else 0;
+                    break :blk offset + offset_2 + (x % 256 / 8) * 2 + (y % 512 / 8) * 0x40;
+                },
+            };
+        }
+
+        fn drawBackgroundPixel(self: *@This(), comptime layer: u2, i: u32, bgr555: u16) void {
+            _ = layer;
+
+            self.scanline.top()[i] = Scanline.Pixel.from(.Background, bgr555);
+        }
+    };
+}
+
+const Scanline = struct {
+    const Pixel = union(enum) {
+        // TODO: Rename
+        const Layer = enum { Background, Sprite };
+
+        set: u16,
+        obj_set: u16,
+        unset: void,
+        hidden: void,
+
+        fn from(comptime layer: Layer, bgr555: u16) Pixel {
+            return switch (layer) {
+                .Background => .{ .set = bgr555 },
+                .Sprite => .{ .obj_set = bgr555 },
+            };
+        }
+
+        pub fn isSet(self: @This()) bool {
+            return switch (self) {
+                .set, .obj_set => true,
+                .unset, .hidden => false,
+            };
+        }
+    };
+
+    layers: [2][]Pixel,
+    buf: []Pixel,
+
+    fn init(allocator: std.mem.Allocator) !@This() {
+        const buf = try allocator.alloc(Pixel, width * 2); // Top & Bottom Scanline
+        @memset(buf, .unset);
+
+        return .{
+            // Top & Bototm Layers
+            .layers = [_][]Pixel{ buf[0..][0..width], buf[width..][0..width] },
+            .buf = buf,
+        };
+    }
+
+    fn reset(self: *@This()) void {
+        @memset(self.buf, .unset);
+    }
+
+    fn deinit(self: @This(), allocator: std.mem.Allocator) void {
+        allocator.free(self.buf);
+    }
+
+    fn top(self: *@This()) []Pixel {
+        return self.layers[0];
+    }
+
+    fn btm(self: *@This()) []Pixel {
+        return self.layers[1];
+    }
+};
+
+const bg = struct {
+    const Text = struct {
+        const io = @import("../nds9/io.zig");
+
+        /// Read / Write
+        cnt: io.Bgcnt = .{ .raw = 0x0000 },
+        /// Write Only
+        hofs: io.Hofs = .{ .raw = 0x0000 },
+        /// Write Only
+        vofs: io.Vofs = .{ .raw = 0x0000 },
+    };
+
+    const Screen = struct {
+        const Entry = extern union {
+            const Bitfield = @import("bitfield").Bitfield;
+            const Bit = @import("bitfield").Bit;
+
+            tile_id: Bitfield(u16, 0, 10),
+            h_flip: Bit(u16, 10),
+            v_flip: Bit(u16, 11),
+            pal_bank: Bitfield(u16, 12, 4),
+            raw: u16,
+        };
+    };
+
+    const Affine = @compileError("TODO: Implement Affine Backgrounds");
+};
+
+inline fn rgba888(bgr555: u16) u32 {
+    const b: u32 = bgr555 >> 10 & 0x1F;
+    const g: u32 = bgr555 >> 5 & 0x1F;
+    const r: u32 = bgr555 & 0x1F;
+
+    // zig fmt: off
+    return (r << 3 | r >> 2) << 24
+        |  (g << 3 | g >> 2) << 16
+        |  (b << 3 | b >> 2) << 8
+        |  0xFF;
+    // zig fmt: on
+}

src/main.zig

@@ -1,22 +1,21 @@
 const std = @import("std");
 const clap = @import("zig-clap");
 
-const nds9 = @import("core/nds9.zig");
-const nds7 = @import("core/nds7.zig");
 const emu = @import("core/emu.zig");
 
-const IBus = @import("arm32").Bus;
-const IScheduler = @import("arm32").Scheduler;
-const ICoprocessor = @import("arm32").Coprocessor;
-
 const Ui = @import("platform.zig").Ui;
-const SharedContext = @import("core/emu.zig").SharedContext;
+const SharedCtx = @import("core/emu.zig").SharedCtx;
+const System = @import("core/emu.zig").System;
+const Sync = @import("core/emu.zig").Sync;
+const Scheduler = @import("core/Scheduler.zig");
 
 const Allocator = std.mem.Allocator;
 const ClapResult = clap.Result(clap.Help, &cli_params, clap.parsers.default);
 
 const cli_params = clap.parseParamsComptime(
     \\-h, --help        Display this help and exit.
+    \\-f, --firm <str>  Path to NDS Firmware Directory
+    \\--gdb              Run Turbo in GDB Mode
     \\<str>             Path to the NDS ROM
     \\
 );
@@ -29,45 +28,62 @@ pub fn main() !void {
 
     const allocator = gpa.allocator();
 
-    const result = try clap.parse(clap.Help, &cli_params, clap.parsers.default, .{});
+    const result = try clap.parse(clap.Help, &cli_params, clap.parsers.default, .{ .allocator = allocator });
     defer result.deinit();
 
     const rom_path = try handlePositional(result);
     log.debug("loading rom from: {s}", .{rom_path});
 
-    const rom_file = try std.fs.cwd().openFile(rom_path, .{});
-    defer rom_file.close();
+    const firm_path = result.args.firm;
+    log.debug("loading firmware from from: {?s}", .{firm_path});
 
-    const shared_ctx = try SharedContext.init(allocator);
-    defer shared_ctx.deinit(allocator);
+    var ctx = try SharedCtx.init(allocator);
+    defer ctx.deinit(allocator);
 
-    const nds9_group: nds9.Group = blk: {
-        var scheduler = try nds9.Scheduler.init(allocator);
-        var bus = try nds9.Bus.init(allocator, &scheduler, shared_ctx);
-        var cp15 = nds9.Cp15{};
+    var scheduler = try Scheduler.init(allocator);
+    defer scheduler.deinit();
 
-        var arm946es = nds9.Arm946es.init(IScheduler.init(&scheduler), IBus.init(&bus), ICoprocessor.init(&cp15));
+    const system: System = blk: {
+        const IBus = @import("arm32").Bus;
+        const IScheduler = @import("arm32").Scheduler;
+        const ICoprocessor = @import("arm32").Coprocessor;
 
-        break :blk .{ .cpu = &arm946es, .bus = &bus, .scheduler = &scheduler };
+        var cp15 = System.Cp15{};
+
+        var bus7 = try System.Bus7.init(allocator, &scheduler, ctx);
+        var bus9 = try System.Bus9.init(allocator, &scheduler, ctx);
+
+        // TODO: Think of a better way to do this
+        bus7.io.configure(&bus9.ppu);
+
+        var arm7tdmi = System.Arm7tdmi.init(IScheduler.init(&scheduler), IBus.init(&bus7));
+        var arm946es = System.Arm946es.init(IScheduler.init(&scheduler), IBus.init(&bus9), ICoprocessor.init(&cp15));
+
+        break :blk .{ .arm7tdmi = &arm7tdmi, .arm946es = &arm946es, .bus7 = &bus7, .bus9 = &bus9, .cp15 = &cp15 };
     };
-    defer nds9_group.deinit(allocator);
+    defer system.deinit(allocator);
 
-    const nds7_group: nds7.Group = blk: {
-        var scheduler = try nds7.Scheduler.init(allocator);
-        var bus = try nds7.Bus.init(allocator, &scheduler, shared_ctx);
-        var arm7tdmi = nds7.Arm7tdmi.init(IScheduler.init(&scheduler), IBus.init(&bus));
+    ctx.io.ipc.configure(system); // Shared I/O needs access to both CPUs (e.g. IPCSYNC)
+    const rom_title = try emu.load(allocator, system, rom_path);
+    if (firm_path) |path| try emu.loadFirm(allocator, system, path);
 
-        break :blk .{ .cpu = &arm7tdmi, .bus = &bus, .scheduler = &scheduler };
-    };
-    defer nds7_group.deinit(allocator);
-
-    const rom_title = try emu.load(allocator, nds7_group, nds9_group, rom_file);
+    emu.fastBoot(system);
 
     var ui = try Ui.init(allocator);
     defer ui.deinit(allocator);
 
     ui.setTitle(rom_title);
-    try ui.run(nds7_group, nds9_group);
+
+    const sync = try allocator.create(Sync);
+    defer allocator.destroy(sync);
+
+    sync.init();
+
+    if (result.args.gdb == 0) {
+        try ui.run(&scheduler, system, sync);
+    } else {
+        try emu.debug.run(allocator, &ui, &scheduler, system, sync);
+    }
 }
 
 fn handlePositional(result: ClapResult) ![]const u8 {

src/platform.zig

@@ -3,14 +3,16 @@ const SDL = @import("sdl2");
 const gl = @import("gl");
 const zgui = @import("zgui");
 
-const nds9 = @import("core/nds9.zig");
-const nds7 = @import("core/nds7.zig");
-
 const ppu = @import("core/ppu.zig");
 const imgui = @import("ui/imgui.zig");
 const emu = @import("core/emu.zig");
 
-const KeyInput = @import("core/nds9/io.zig").KeyInput;
+const System = @import("core/emu.zig").System;
+const Sync = @import("core/emu.zig").Sync;
+const KeyInput = @import("core/io.zig").KeyInput;
+const ExtKeyIn = @import("core/io.zig").ExtKeyIn;
+const Scheduler = @import("core/Scheduler.zig");
+const FrameBuffer = @import("core/ppu.zig").FrameBuffer;
 
 const Allocator = std.mem.Allocator;
 
@@ -34,7 +36,7 @@ pub const Ui = struct {
     state: imgui.State,
 
     pub fn init(allocator: Allocator) !Self {
-        var state = imgui.State{};
+        const state = imgui.State{};
 
         if (SDL.SDL_Init(SDL.SDL_INIT_VIDEO | SDL.SDL_INIT_EVENTS | SDL.SDL_INIT_AUDIO) < 0) panic();
         if (SDL.SDL_GL_SetAttribute(SDL.SDL_GL_CONTEXT_PROFILE_MASK, SDL.SDL_GL_CONTEXT_PROFILE_CORE) < 0) panic();
@@ -86,123 +88,161 @@ pub const Ui = struct {
         return SDL.SDL_GL_GetProcAddress(proc.ptr);
     }
 
-    pub fn run(self: *Self, nds7_group: nds7.Group, nds9_group: nds9.Group) !void {
-        // TODO: Sort this out please
+    pub fn setTitle(self: *@This(), title: [12]u8) void {
+        self.state.title = title ++ [_:0]u8{};
+    }
 
-        const vao_id = opengl_impl.vao();
-        defer gl.deleteVertexArrays(1, &[_]GLuint{vao_id});
-
-        const top_tex = opengl_impl.screenTex(nds9_group.bus.ppu.fb.top(.front));
-        const btm_tex = opengl_impl.screenTex(nds9_group.bus.ppu.fb.btm(.front));
-        const top_out_tex = opengl_impl.outTex();
-        const btm_out_tex = opengl_impl.outTex();
-        defer gl.deleteTextures(4, &[_]GLuint{ top_tex, top_out_tex, btm_tex, btm_out_tex });
-
-        const top_fbo = try opengl_impl.frameBuffer(top_out_tex);
-        const btm_fbo = try opengl_impl.frameBuffer(btm_out_tex);
-        defer gl.deleteFramebuffers(2, &[_]GLuint{ top_fbo, btm_fbo });
-
-        const prog_id = try opengl_impl.program();
-        defer gl.deleteProgram(prog_id);
+    pub fn run(self: *Self, scheduler: *Scheduler, system: System, sync: *Sync) !void {
+        const id = try opengl_impl.runInit(&system.bus9.ppu.fb);
+        defer id.deinit();
 
         var event: SDL.SDL_Event = undefined;
 
-        emu_loop: while (true) {
-            emu.runFrame(nds7_group, nds9_group);
+        while (!sync.should_quit.load(.monotonic)) {
+            emu.runFrame(scheduler, system); // TODO: run emu in separate thread
 
             while (SDL.SDL_PollEvent(&event) != 0) {
                 _ = zgui.backend.processEvent(&event);
-
-                switch (event.type) {
-                    SDL.SDL_QUIT => break :emu_loop,
-                    SDL.SDL_WINDOWEVENT => {
-                        if (event.window.event == SDL.SDL_WINDOWEVENT_RESIZED) {
-                            std.log.debug("window resized to: {}x{}", .{ event.window.data1, event.window.data2 });
-
-                            self.state.dim.width = @intCast(event.window.data1);
-                            self.state.dim.height = @intCast(event.window.data2);
-                        }
-                    },
-                    SDL.SDL_KEYDOWN => {
-                        // TODO: Make use of compare_and_xor?
-                        const key_code = event.key.keysym.sym;
-                        var keyinput: KeyInput = .{ .raw = 0x0000 };
-
-                        switch (key_code) {
-                            SDL.SDLK_UP => keyinput.up.set(),
-                            SDL.SDLK_DOWN => keyinput.down.set(),
-                            SDL.SDLK_LEFT => keyinput.left.set(),
-                            SDL.SDLK_RIGHT => keyinput.right.set(),
-                            SDL.SDLK_x => keyinput.a.set(),
-                            SDL.SDLK_z => keyinput.b.set(),
-                            SDL.SDLK_a => keyinput.shoulder_l.set(),
-                            SDL.SDLK_s => keyinput.shoulder_r.set(),
-                            SDL.SDLK_RETURN => keyinput.start.set(),
-                            SDL.SDLK_RSHIFT => keyinput.select.set(),
-                            else => {},
-                        }
-
-                        nds9_group.bus.io.keyinput.fetchAnd(~keyinput.raw, .Monotonic);
-                    },
-                    SDL.SDL_KEYUP => {
-                        // TODO: Make use of compare_and_xor?
-                        const key_code = event.key.keysym.sym;
-                        var keyinput: KeyInput = .{ .raw = 0x0000 };
-
-                        switch (key_code) {
-                            SDL.SDLK_UP => keyinput.up.set(),
-                            SDL.SDLK_DOWN => keyinput.down.set(),
-                            SDL.SDLK_LEFT => keyinput.left.set(),
-                            SDL.SDLK_RIGHT => keyinput.right.set(),
-                            SDL.SDLK_x => keyinput.a.set(),
-                            SDL.SDLK_z => keyinput.b.set(),
-                            SDL.SDLK_a => keyinput.shoulder_l.set(),
-                            SDL.SDLK_s => keyinput.shoulder_r.set(),
-                            SDL.SDLK_RETURN => keyinput.start.set(),
-                            SDL.SDLK_RSHIFT => keyinput.select.set(),
-                            else => {},
-                        }
-
-                        nds9_group.bus.io.keyinput.fetchOr(keyinput.raw, .Monotonic);
-                    },
-                    else => {},
-                }
+                handleInput(&event, system, &self.state, sync);
             }
 
             {
-                gl.bindFramebuffer(gl.FRAMEBUFFER, top_fbo);
+                gl.bindFramebuffer(gl.FRAMEBUFFER, id.top_fbo);
                 defer gl.bindFramebuffer(gl.FRAMEBUFFER, 0);
 
                 gl.viewport(0, 0, nds_width, nds_height);
-                opengl_impl.drawScreen(top_tex, prog_id, vao_id, nds9_group.bus.ppu.fb.top(.front));
+                opengl_impl.drawScreen(id.top_tex, id.prog_id, id.vao_id, system.bus9.ppu.fb.top(.front));
             }
 
             {
-                gl.bindFramebuffer(gl.FRAMEBUFFER, btm_fbo);
+                gl.bindFramebuffer(gl.FRAMEBUFFER, id.btm_fbo);
                 defer gl.bindFramebuffer(gl.FRAMEBUFFER, 0);
 
                 gl.viewport(0, 0, nds_width, nds_height);
-                opengl_impl.drawScreen(btm_tex, prog_id, vao_id, nds9_group.bus.ppu.fb.btm(.front));
+                opengl_impl.drawScreen(id.btm_tex, id.prog_id, id.vao_id, system.bus9.ppu.fb.btm(.front));
             }
 
-            const zgui_redraw = imgui.draw(&self.state, top_out_tex, btm_out_tex, nds9_group.cpu);
+            imgui.draw(&self.state, id.top_out_tex, id.btm_out_tex, system);
 
-            if (zgui_redraw) {
-                // Background Colour
-                const size = zgui.io.getDisplaySize();
-                gl.viewport(0, 0, @intFromFloat(size[0]), @intFromFloat(size[1]));
-                gl.clearColor(0, 0, 0, 1.0);
-                gl.clear(gl.COLOR_BUFFER_BIT);
-
-                zgui.backend.draw();
-            }
+            // Background Colour
+            const size = zgui.io.getDisplaySize();
+            gl.viewport(0, 0, @intFromFloat(size[0]), @intFromFloat(size[1]));
+            gl.clearColor(0, 0, 0, 1.0);
+            gl.clear(gl.COLOR_BUFFER_BIT);
 
+            zgui.backend.draw();
             SDL.SDL_GL_SwapWindow(self.window);
         }
     }
 
-    pub fn setTitle(self: *@This(), title: [12]u8) void {
-        self.state.title = title ++ [_:0]u8{};
+    pub fn debug_run(self: *Self, _: *Scheduler, system: System, sync: *Sync) !void {
+        const id = try opengl_impl.runInit(&system.bus9.ppu.fb);
+        defer id.deinit();
+
+        var event: SDL.SDL_Event = undefined;
+
+        while (!sync.should_quit.load(.monotonic)) {
+            while (SDL.SDL_PollEvent(&event) != 0) {
+                _ = zgui.backend.processEvent(&event);
+                handleInput(&event, system, &self.state, sync);
+            }
+
+            {
+                gl.bindFramebuffer(gl.FRAMEBUFFER, id.top_fbo);
+                defer gl.bindFramebuffer(gl.FRAMEBUFFER, 0);
+
+                gl.viewport(0, 0, nds_width, nds_height);
+                opengl_impl.drawScreen(id.top_tex, id.prog_id, id.vao_id, system.bus9.ppu.fb.top(.front));
+            }
+
+            {
+                gl.bindFramebuffer(gl.FRAMEBUFFER, id.btm_fbo);
+                defer gl.bindFramebuffer(gl.FRAMEBUFFER, 0);
+
+                gl.viewport(0, 0, nds_width, nds_height);
+                opengl_impl.drawScreen(id.btm_tex, id.prog_id, id.vao_id, system.bus9.ppu.fb.btm(.front));
+            }
+
+            imgui.draw(&self.state, id.top_out_tex, id.btm_out_tex, system);
+
+            // Background Colour
+            const size = zgui.io.getDisplaySize();
+            gl.viewport(0, 0, @intFromFloat(size[0]), @intFromFloat(size[1]));
+            gl.clearColor(0, 0, 0, 1.0);
+            gl.clear(gl.COLOR_BUFFER_BIT);
+
+            zgui.backend.draw();
+            SDL.SDL_GL_SwapWindow(self.window);
+        }
+    }
+
+    fn handleInput(event: *SDL.SDL_Event, system: System, state: *imgui.State, sync: *Sync) void {
+        switch (event.type) {
+            SDL.SDL_QUIT => sync.should_quit.store(true, .monotonic),
+            SDL.SDL_WINDOWEVENT => {
+                if (event.window.event == SDL.SDL_WINDOWEVENT_RESIZED) {
+                    std.log.debug("window resized to: {}x{}", .{ event.window.data1, event.window.data2 });
+
+                    state.dim.width = @intCast(event.window.data1);
+                    state.dim.height = @intCast(event.window.data2);
+
+                    zgui.io.setDisplaySize(@floatFromInt(event.window.data1), @floatFromInt(event.window.data2));
+                }
+            },
+            SDL.SDL_KEYDOWN => {
+                // TODO: Make use of compare_and_xor?
+                const key_code = event.key.keysym.sym;
+
+                var keyinput: KeyInput = .{ .raw = 0x0000 };
+                var extkeyin: ExtKeyIn = .{ .raw = 0x0000 };
+
+                switch (key_code) {
+                    SDL.SDLK_UP => keyinput.up.set(),
+                    SDL.SDLK_DOWN => keyinput.down.set(),
+                    SDL.SDLK_LEFT => keyinput.left.set(),
+                    SDL.SDLK_RIGHT => keyinput.right.set(),
+                    SDL.SDLK_c => keyinput.a.set(),
+                    SDL.SDLK_x => keyinput.b.set(),
+                    SDL.SDLK_d => extkeyin.x.set(),
+                    SDL.SDLK_s => extkeyin.y.set(),
+                    SDL.SDLK_a => keyinput.shoulder_l.set(),
+                    SDL.SDLK_f => keyinput.shoulder_r.set(),
+                    SDL.SDLK_RETURN => keyinput.start.set(),
+                    SDL.SDLK_RSHIFT => keyinput.select.set(),
+                    else => {},
+                }
+
+                const input = (@as(u32, extkeyin.raw) << 16) | keyinput.raw;
+                system.bus9.io.shr.input.set(.And, ~input);
+            },
+            SDL.SDL_KEYUP => {
+                // TODO: Make use of compare_and_xor?
+                const key_code = event.key.keysym.sym;
+
+                var keyinput: KeyInput = .{ .raw = 0x0000 };
+                var extkeyin: ExtKeyIn = .{ .raw = 0x0000 };
+
+                switch (key_code) {
+                    SDL.SDLK_UP => keyinput.up.set(),
+                    SDL.SDLK_DOWN => keyinput.down.set(),
+                    SDL.SDLK_LEFT => keyinput.left.set(),
+                    SDL.SDLK_RIGHT => keyinput.right.set(),
+                    SDL.SDLK_c => keyinput.a.set(),
+                    SDL.SDLK_x => keyinput.b.set(),
+                    SDL.SDLK_d => extkeyin.x.set(),
+                    SDL.SDLK_s => extkeyin.y.set(),
+                    SDL.SDLK_a => keyinput.shoulder_l.set(),
+                    SDL.SDLK_f => keyinput.shoulder_r.set(),
+                    SDL.SDLK_RETURN => keyinput.start.set(),
+                    SDL.SDLK_RSHIFT => keyinput.select.set(),
+                    else => {},
+                }
+
+                const input = (@as(u32, extkeyin.raw) << 16) | keyinput.raw;
+                system.bus9.io.shr.input.set(.Or, input);
+            },
+            else => {},
+        }
     }
 };
 
@@ -212,6 +252,46 @@ fn panic() noreturn {
 }
 
 const opengl_impl = struct {
+    const Ids = struct {
+        vao_id: GLuint,
+
+        top_tex: GLuint,
+        btm_tex: GLuint,
+        top_out_tex: GLuint,
+        btm_out_tex: GLuint,
+
+        top_fbo: GLuint,
+        btm_fbo: GLuint,
+
+        prog_id: GLuint,
+
+        fn deinit(self: Ids) void {
+            gl.deleteProgram(self.prog_id);
+            gl.deleteFramebuffers(2, &[_]GLuint{ self.top_fbo, self.btm_fbo });
+            gl.deleteTextures(4, &[_]GLuint{ self.top_tex, self.top_out_tex, self.btm_tex, self.btm_out_tex });
+            gl.deleteVertexArrays(1, &[_]GLuint{self.vao_id});
+        }
+    };
+
+    fn runInit(fb: *const FrameBuffer) !Ids {
+        const top_out_tex = opengl_impl.outTex();
+        const btm_out_tex = opengl_impl.outTex();
+
+        return .{
+            .vao_id = opengl_impl.vao(),
+
+            .top_tex = opengl_impl.screenTex(fb.top(.front)),
+            .btm_tex = opengl_impl.screenTex(fb.btm(.front)),
+            .top_out_tex = top_out_tex,
+            .btm_out_tex = btm_out_tex,
+
+            .top_fbo = try opengl_impl.frameBuffer(top_out_tex),
+            .btm_fbo = try opengl_impl.frameBuffer(btm_out_tex),
+
+            .prog_id = try opengl_impl.program(),
+        };
+    }
+
     fn drawScreen(tex_id: GLuint, prog_id: GLuint, vao_id: GLuint, buf: []const u8) void {
         gl.bindTexture(gl.TEXTURE_2D, tex_id);
         defer gl.bindTexture(gl.TEXTURE_2D, 0);

src/ui/imgui.zig

@@ -3,7 +3,7 @@ const zgui = @import("zgui");
 
 const platform = @import("../platform.zig");
 
-const Arm946es = @import("../core/nds9.zig").Arm946es;
+const System = @import("../core/emu.zig").System;
 const Dimensions = platform.Dimensions;
 
 const nds_height = @import("../core/ppu.zig").screen_height;
@@ -18,8 +18,9 @@ pub const State = struct {
     dim: Dimensions = .{ .width = 1600, .height = 900 },
 };
 
-pub fn draw(state: *const State, top_tex: GLuint, btm_tex: GLuint, arm946es: *Arm946es) bool {
-    _ = arm946es;
+pub fn draw(state: *const State, top_tex: GLuint, btm_tex: GLuint, system: System) void {
+    _ = system;
+
     zgui.backend.newFrame(@floatFromInt(state.dim.width), @floatFromInt(state.dim.height));
 
     {
@@ -35,6 +36,4 @@ pub fn draw(state: *const State, top_tex: GLuint, btm_tex: GLuint, arm946es: *Ar
         zgui.image(@ptrFromInt(top_tex), .{ .w = w, .h = h });
         zgui.image(@ptrFromInt(btm_tex), .{ .w = w, .h = h });
     }
-
-    return true;
 }

src/util.zig

@@ -0,0 +1,153 @@
+const std = @import("std");
+const Log2Int = std.math.Log2Int;
+
+const assert = std.debug.assert;
+
+/// Sign-Extends a `SrcT` value to a `DestT`.
+///
+/// Notes:
+/// - `DestT` can be a signed or unsigned integer
+/// - `value` is of type `anytype` and may be a signed / unsigned / comptime integer
+///
+/// Invariants:
+/// - `SrcT` *must* be a signed Integer (the idea being: "why would we sign extend an unsigned value?")
+/// - `SrcT` must have equal or less bits than DestT
+/// - `SrcT` must have equal or less bits than ValT (`@TypeOf(value)`)
+pub fn sext(comptime DestT: type, comptime SrcT: type, value: anytype) DestT {
+    const ValT = @TypeOf(value);
+    const dst_info = @typeInfo(DestT);
+    const src_info = @typeInfo(SrcT);
+    const val_info = @typeInfo(ValT);
+
+    comptime {
+        // DestT, SrcT and ValT are expected to be integers
+        std.debug.assert(dst_info == .Int);
+        std.debug.assert(src_info == .Int);
+        std.debug.assert(val_info == .ComptimeInt or val_info == .Int);
+
+        // sexting to a type smaller than SrcT isn't "extension" and therefore doesn't make sense
+        // sexting also implies a signed value (we may remove this assumption later)
+        std.debug.assert(src_info.Int.signedness == .signed);
+        std.debug.assert(src_info.Int.bits <= dst_info.Int.bits);
+
+        // ValT is allowed to have more bits than SrcT, we just truncate
+        std.debug.assert(val_info == .ComptimeInt or src_info.Int.bits <= val_info.Int.bits);
+    }
+
+    // signed integers implement Arithmetic Right Shift
+    const SignedSrcT = @Type(.{ .Int = .{ .signedness = .signed, .bits = src_info.Int.bits } });
+    const SignedDestT = @Type(.{ .Int = .{ .signedness = .signed, .bits = dst_info.Int.bits } });
+    const SignedValT = switch (val_info) {
+        .Int => @Type(.{ .Int = .{ .signedness = .signed, .bits = val_info.Int.bits } }),
+        .ComptimeInt => FittingInt(value),
+        else => unreachable,
+    };
+
+    const signed_value: SignedSrcT = switch (val_info) {
+        .Int => switch (val_info.Int.signedness) {
+            .signed => @truncate(value),
+            .unsigned => @truncate(@as(SignedValT, @bitCast(value))),
+        },
+        .ComptimeInt => @truncate(value),
+        else => unreachable,
+    };
+
+    // maybe no shifts are needed at all?
+    return @bitCast(@as(SignedDestT, signed_value));
+}
+
+test "sext" {
+    const expect = std.testing.expectEqual;
+
+    try expect(@as(u4, 0b1111), sext(u4, i2, 0b11));
+    try expect(@as(u4, 0b0001), sext(u4, i2, 0b01));
+
+    try expect(@as(u4, 0b1111), sext(u4, i2, 0b1111_1111));
+    try expect(@as(u4, 0b0001), sext(u4, i2, 0b0000_0001));
+
+    try expect(@as(i4, -1), sext(i4, i2, 0b11));
+    try expect(@as(i4, 1), sext(i4, i2, 0b01));
+
+    try expect(@as(i4, -1), sext(i4, i2, 0b1111_1111));
+    try expect(@as(i4, 1), sext(i4, i2, 0b0000_0001));
+
+    try expect(@as(u4, 0b1111), sext(u4, i2, @as(u2, 0b11)));
+    try expect(@as(u4, 0b0001), sext(u4, i2, @as(u2, 0b01)));
+
+    try expect(@as(u4, 0b1111), sext(u4, i2, @as(u8, 0b1111_1111)));
+    try expect(@as(u4, 0b0001), sext(u4, i2, @as(u8, 0b0000_0001)));
+
+    try expect(@as(i4, -1), sext(i4, i2, @as(i2, -1)));
+    try expect(@as(i4, 1), sext(i4, i2, @as(i2, 1)));
+
+    try expect(@as(i4, -1), sext(i4, i2, @as(i8, -1)));
+    try expect(@as(i4, 1), sext(i4, i2, @as(i8, 1)));
+}
+
+fn FittingInt(comptime value: comptime_int) type {
+    const bits = blk: {
+        var i: comptime_int = 0;
+        while (value >> i != 0) : (i += 1) {}
+
+        break :blk i;
+    };
+
+    return @Type(.{ .Int = .{ .signedness = .signed, .bits = bits } });
+}
+
+test "FittingInt" {
+    try std.testing.expect(FittingInt(0) == i0);
+    try std.testing.expect(FittingInt(0b1) == i1);
+    try std.testing.expect(FittingInt(0b1) == i1);
+    try std.testing.expect(FittingInt(0b11) == i2);
+    try std.testing.expect(FittingInt(0b101) == i3);
+    try std.testing.expect(FittingInt(0b1010) == i4);
+}
+
+/// TODO: Document this properly :)
+pub inline fn shift(comptime T: type, addr: u32) Log2Int(T) {
+    const offset: Log2Int(T) = @truncate(addr & (@sizeOf(T) - 1));
+
+    return offset << 3;
+}
+
+/// TODO: Document this properly :)
+pub inline fn subset(comptime T: type, comptime U: type, addr: u32, left: T, right: U) T {
+    const offset: Log2Int(T) = @truncate(addr & (@sizeOf(T) - 1));
+    const mask = @as(T, std.math.maxInt(U)) << (offset << 3);
+    const value = @as(T, right) << (offset << 3);
+
+    return (value & mask) | (left & ~mask);
+}
+
+test "subset" {
+    const expectEqual = std.testing.expectEqual;
+
+    try expectEqual(@as(u16, 0xABAA), subset(u16, u8, 0x0000_0000, 0xABCD, 0xAA));
+    try expectEqual(@as(u16, 0xAACD), subset(u16, u8, 0x0000_0001, 0xABCD, 0xAA));
+
+    try expectEqual(@as(u32, 0xDEAD_BEAA), subset(u32, u8, 0x0000_0000, 0xDEAD_BEEF, 0xAA));
+    try expectEqual(@as(u32, 0xDEAD_AAEF), subset(u32, u8, 0x0000_0001, 0xDEAD_BEEF, 0xAA));
+    try expectEqual(@as(u32, 0xDEAA_BEEF), subset(u32, u8, 0x0000_0002, 0xDEAD_BEEF, 0xAA));
+    try expectEqual(@as(u32, 0xAAAD_BEEF), subset(u32, u8, 0x0000_0003, 0xDEAD_BEEF, 0xAA));
+
+    try expectEqual(@as(u32, 0xDEAD_AAAA), subset(u32, u16, 0x0000_0000, 0xDEAD_BEEF, 0xAAAA));
+    try expectEqual(@as(u32, 0xAAAA_BEEF), subset(u32, u16, 0x0000_0002, 0xDEAD_BEEF, 0xAAAA));
+
+    try expectEqual(@as(u64, 0xBAAD_F00D_DEAD_CAAA), subset(u64, u8, 0x0000_0000, 0xBAAD_F00D_DEAD_CAFE, 0xAA));
+    try expectEqual(@as(u64, 0xBAAD_F00D_DEAD_AAFE), subset(u64, u8, 0x0000_0001, 0xBAAD_F00D_DEAD_CAFE, 0xAA));
+    try expectEqual(@as(u64, 0xBAAD_F00D_DEAA_CAFE), subset(u64, u8, 0x0000_0002, 0xBAAD_F00D_DEAD_CAFE, 0xAA));
+    try expectEqual(@as(u64, 0xBAAD_F00D_AAAD_CAFE), subset(u64, u8, 0x0000_0003, 0xBAAD_F00D_DEAD_CAFE, 0xAA));
+    try expectEqual(@as(u64, 0xBAAD_F0AA_DEAD_CAFE), subset(u64, u8, 0x0000_0004, 0xBAAD_F00D_DEAD_CAFE, 0xAA));
+    try expectEqual(@as(u64, 0xBAAD_AA0D_DEAD_CAFE), subset(u64, u8, 0x0000_0005, 0xBAAD_F00D_DEAD_CAFE, 0xAA));
+    try expectEqual(@as(u64, 0xBAAA_F00D_DEAD_CAFE), subset(u64, u8, 0x0000_0006, 0xBAAD_F00D_DEAD_CAFE, 0xAA));
+    try expectEqual(@as(u64, 0xAAAD_F00D_DEAD_CAFE), subset(u64, u8, 0x0000_0007, 0xBAAD_F00D_DEAD_CAFE, 0xAA));
+
+    try expectEqual(@as(u64, 0xBAAD_F00D_DEAD_AAAA), subset(u64, u16, 0x0000_0000, 0xBAAD_F00D_DEAD_CAFE, 0xAAAA));
+    try expectEqual(@as(u64, 0xBAAD_F00D_AAAA_CAFE), subset(u64, u16, 0x0000_0002, 0xBAAD_F00D_DEAD_CAFE, 0xAAAA));
+    try expectEqual(@as(u64, 0xBAAD_AAAA_DEAD_CAFE), subset(u64, u16, 0x0000_0004, 0xBAAD_F00D_DEAD_CAFE, 0xAAAA));
+    try expectEqual(@as(u64, 0xAAAA_F00D_DEAD_CAFE), subset(u64, u16, 0x0000_0006, 0xBAAD_F00D_DEAD_CAFE, 0xAAAA));
+
+    try expectEqual(@as(u64, 0xBAAD_F00D_AAAA_AAAA), subset(u64, u32, 0x0000_0000, 0xBAAD_F00D_DEAD_CAFE, 0xAAAA_AAAA));
+    try expectEqual(@as(u64, 0xAAAA_AAAA_DEAD_CAFE), subset(u64, u32, 0x0000_0004, 0xBAAD_F00D_DEAD_CAFE, 0xAAAA_AAAA));
+}